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CN3010-500 CP - Cavium
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Cavium CN3010-500 CP
cn3005-15.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN3010-500 CP
Part NumberCN3010-500BG525-CP
MarketEmbedded
IntroductionJanuary 30, 2006 (announced)
May 1, 2006 (launched)
General Specs
FamilyOCTEON
SeriesCN3000
Frequency500 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Core NamecnMIPS
Process130 nm
TechnologyCMOS
Word Size64 bit
Cores1
Threads1
Max CPUs1 (Uniprocessor)
Max Memory2 GiB
Electrical
Power dissipation4 W

The CN3010-500 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the CN3005 equivalent, double DDR2 memory access, as well as support for TDM/PCM (VoIP support).

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$24 KiB
0.0234 MiB
24,576 B
2.288818e-5 GiB
L1I$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1x16 KiB2-way set associative 
L1D$8 KiB
0.00781 MiB
8,192 B
7.629395e-6 GiB
1x8 KiB64-way set associativeWrite-through

L2$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
  1x128 KiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-533
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth1.986 GiB/s
Bandwidth
Single 1.986 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI
Width32 bit
Clock66.66 MHz
Rate254.31 MiB/s
Featureshost or slave
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2

GP I/OYes

Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 3)
TDM/PCMYes

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Networking
TCPYes
QoSYes

Block diagram[edit]

cn3010 block diagram.png

Datasheet[edit]

base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count1 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3010-500bg525-cp +
has ecc memory supporttrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.0234 MiB (24 KiB, 24,576 B, 2.288818e-5 GiB) +
l1d$ description64-way set associative +
l1d$ size0.00781 MiB (8 KiB, 8,192 B, 7.629395e-6 GiB) +
l1i$ description2-way set associative +
l1i$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
l2$ description4-way set associative +
l2$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:cn3005-15.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3010-500 CP +
nameCavium CN3010-500 CP +
part numberCN3010-500BG525-CP +
power dissipation4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3000 +
supported memory typeDDR2-533 +
technologyCMOS +
thread count1 +
word size64 bit (8 octets, 16 nibbles) +