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Godson-2F
Godson-2F chip
General Info
Designer	Loongson
Manufacturer	STMicroelectronics
Model Number	2F
Part Number	PLA80
Market	Desktop
Introduction	July 31, 2007 (announced) June, 2008 (launched)
General Specs
Family	Godson 2
Series	Godson 2
Frequency	800 MHz
Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	GS464
Core Name	GS464
Process	90 nm
Transistors	51,000,000
Technology	CMOS
Die	43 mm²
Word Size	64 bit
Cores	1
Threads	1
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Power dissipation	5 W
Vcore	1.2 V

Godson-2F (龙芯2F) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in mid-2008, the Godson-2F operates at up to 800 MHz consuming 5 W. This chip was manufactured on STMicroelectronics' 90 nm process.

The Godson-2F features a faster memory controller (supporting up to DDR2-667) and integrates some of the functionality of the southbridge including a PCI-X controller and more general-purpose I/O pins.

Cache

Main article: GS464 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 4-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB 4-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-667 Supports ECC Yes Max Mem 4 GiB Controllers 1 Channels 1 Max Bandwidth 9.934 GiB/s 10,172.416 MiB/s 10.667 GB/s 10,666.551 MB/s 0.0097 TiB/s 0.0107 TB/s Bandwidth Single 9.934 GiB/s

Expansions

This chip has integrated HyperTransport 1.0 operating at 400 MHz.

[Edit/Modify Expansions Info]

	Expansion Options
	PCI Revision 2.3 Width 32 bit Clock 66 MHz PCI-X Revision 1.0b Width 32 bit Clock 133 MHz LPC Revision 1.1

Graphics

This chip had no integrated graphics processing unit.

Die Shot

• 90 nm process
• 51,000,000 transistors
• 43 mm² die size

Datasheet

• Godson 2F Datasheet (V1.1)

References

• Hu, Wei-Wu, and Jian Wang. "Making effective decisions in computer architects’ real-world: Lessons and experiences with Godson-2 processor designs." Journal of Computer Science and Technology 23.4 (2008): 620-632.