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ARMADA 610 - Marvell
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ARMADA 610
General Info
DesignerMarvell
ManufacturerTSMC
Model Number610
Part Number88AP610
MarketMobile
IntroductionOctober 19, 2009 (announced)
January 5, 2010 (launched)
General Specs
FamilyARMADA 600
Series600
Frequency1,000 MHz
Microarchitecture
ISAARMv6 (ARM), ARMv5
MicroarchitectureSheeva PJ4
PlatformARMADA
Core NameSheeva PJ4
Process55 nm
Word Size32 bit
Cores1
Threads1
Max CPUs1 (Uniprocessor)
Max Memory2 GiB
Electrical
VI/O1.5 V ± 0.3 V, 3.0 V, 3.3 V

ARMADA 610 was a 32-bit ARM microprocessor introduced by Marvell in 2010. This processor, which is based on Marvell's Sheeva PJ4 microarchitecture, operated at 1 GHz and supported up to 2 GiB of DDR3-1066 memory. The ARMADA 610 also integrated a Vivante GC860 IGP as well as an EPD display controller which eliminates page turn lag.

Cache[edit]

Main article: Sheeva PJ4 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
L1I$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
1x32 KiB  
L1D$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
1x32 KiB  

L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-800
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels1
Max Bandwidth7.942 GiB/s
Bandwidth
Single 7.942 GiB/s

Static Memory Controller[edit]

  • 4 chip selects, up to 256 MB each
  • Asynch/Sync operation up to 78 MHz
  • A/D and AA/D Mode, x8 & x16 NOR Flash interface
  • Support for VLIO or companion chips

NAND Flash Controller[edit]

  • ONFI compliant controller supporting SLC and MLC NAND, x8 & x16, small block and large block
  • 2 Chip Selects with up to 64GB of address space
  • Support for 2 KB and 4 KB page sizes
  • 2-bit detect/1-bit correct ECC & 16-bit correct BCH

MMC, SD and SDIO Controller[edit]

  • 4x MMC/SD/SDIO/CE-ATA Controllers
  • Supports MMC/eMMC v4.2, 4.3 and 4.4
  • SDIO v 2.0, SDcard v2.1 and v3.0 (UHS-I)
  • CE-ATA 1/4/8-Bit, SPI mode and boot suppor

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports3
Features2x HSIC, 1x FSIC/12pin ULPI
UART
Ports4
I²C
Ports6

JTAGYes

Graphics[edit]

The 618 incorporates a Vivante GC860 GPU capable of 45 million triangle strips per second, 250 Mpixel/s fill rate.

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUGC860
DesignerVivante
Frequency? MHz
"? MHz" is not a number.
OutputHDMI, DSI

Max Resolution
HDMI1920x1080
DSI1920x1080

Standards
DirectX11
OpenGL3.0
OpenCL1.1
OpenGL ES2.0
  • 1080p decode support for H.264 high profile, VC-1/WMV, MPEG-4, MPEG-2, H.263, On-2.
  • 1080p encode support for h.264 high profile, MPEG-4, MPEG-2, H.263 and On-2.

Hardware Accelerators[edit]

Marvell Wireless Trusted Module v3[edit]

  • Hashing units: MD5, SHA-1, HMAC-SHA-1; SHA-224/SHA256 and HMAC, SHA-512 and HMAC, MD5 and HMAC-MD5
  • Symmetric crypto: AES (128 to 256 & ECB, CBC, CTR/XTS modes), DES/3DES (ECB & CBC), RC4
  • Asymmetric crypto: ECC (Prime field ECC, FIPS std curve EC-224/256, EC-DSA) & RSA (RSA key gen, PKCS#1 v1.5/v2.1 Digital Signatures, x.509 Digital Certificate), & DiffieHellman Key exchange. True HW RNG, FIPS 140-2 certification

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
VFPv3-D16Vector Floating Point (VFP) v3 (16 Regs) Extension
WMMXWireless MMX
WMMX 2Wireless MMX 2

Block Diagram[edit]

armada 610 block.png

Documents[edit]

Facts about "ARMADA 610 - Marvell"
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
core count1 +
core nameSheeva PJ4 +
designerMarvell +
familyARMADA 600 +
first announcedOctober 19, 2009 +
first launchedJanuary 5, 2010 +
full page namemarvell/armada/610 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuGC860 +
integrated gpu designerVivante +
io voltage1.5 V (15 dV, 150 cV, 1,500 mV) +, 3 V (30 dV, 300 cV, 3,000 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
io voltage tolerance0.3 V +
isaARMv6 + and ARMv5 +
isa familyARM +
l1$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
l1d$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
l1i$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateJanuary 5, 2010 +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory channels1 +
microarchitectureSheeva PJ4 +
model number610 +
nameARMADA 610 +
part number88AP610 +
platformARMADA +
process55 nm (0.055 μm, 5.5e-5 mm) +
series600 +
supported memory typeDDR3-1066 + and DDR2-800 +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +