| Edit Values |
| Cavium CN3840-400 EXP |
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| Designer | Cavium |
| Manufacturer | TSMC |
| Model Number | CN3840-400 EXP |
| Part Number | CN3840-400BG1521-EXP |
| Market | Networking |
| Introduction | August 22, 2005 (announced) August 22, 2005 (launched) |
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| Family | OCTEON |
| Series | CN3800 |
| Frequency | 400 MHz |
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| ISA | MIPS64 (MIPS) |
| Microarchitecture | cnMIPS |
| Core Name | cnMIPS |
| Process | 130 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 8 |
| Threads | 8 |
| Max Memory | 16 GiB |
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| Max SMP | 1-Way (Uniprocessor) |
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| Package | FCBGA-1521 (BGA) |
| Ball Count | 1521 |
| Interconnect | BGA-1521 |
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The CN3840-400 EXP is a 64-bit octa-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates eight cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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| L1$ | 320 KiB 327,680 B 0.313 MiB
| | L1I$ | 256 KiB 262,144 B 0.25 MiB
| 8x32 KiB | 64-way set associative | |
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| L1D$ | 64 KiB 65,536 B 0.0625 MiB
| 8x8 KiB | 64-way set associative | Write-through |
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| | L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB
| | | | 1x1 MiB | 8-way set associative | |
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Memory controller[edit]
[Edit/Modify Memory Info]
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Integrated Memory Controller
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| Max Type | DDR2-800 |
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| Supports ECC | Yes |
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| Max Mem | 16 GiB |
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| Controllers | 1 |
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| Channels | 1 |
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| Width | 128 bit |
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| Max Bandwidth | 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s
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| Bandwidth |
Single 11.92 GiB/s
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Expansions[edit]
Networking[edit]
Hardware Accelerators[edit]
Block diagram[edit]
Datasheet[edit]