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Difference between revisions of "3 µm lithography process"

(Industry)
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  |Voltage
 
  |Voltage
 
  | 
 
  | 
  |Contacted Gate Pitch
+
  |Gate Length
 
  |Interconnect Pitch (M1P)
 
  |Interconnect Pitch (M1P)
 
  |SRAM bit cell
 
  |SRAM bit cell

Revision as of 06:05, 4 April 2017

The 3 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s.

Industry

Fab
Process Name​
1st Production​
Voltage​
 ​
Gate Length​
Interconnect Pitch (M1P)​
SRAM bit cell
Hitachi
Hi-CMOS I
 ?
5 V
Value
3 µm
3 µm
 ? µm²

3 μm Microprocessors

This list is incomplete; you can help by expanding it.

3 μm Microcontrollers

3 μm Chips

References

  • Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.