The 8 µm lithography process was the semiconductor process technology used by some semiconductor companies during the late 1960s through the early 1970s. This process had an effective channel length of roughly 8 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process at companies such as Fairchild and TI were 2 inch (51 mm). This process was later superseded by 6 µm, 5 µm, and 3 µm processes.

Industry

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch​
Metal Layers​
Technology​
Wafer

Intel	TI	Fairchild	MOS Technology
1970	1969	1969	1974
? nm	? nm	? nm	? nm
? nm	? nm	? nm	? nm
2	2	2
pMOS	pMOS	pMOS	depletion-mode nMOS
51 mm

8 µm Microprocessors

• TI
  • TMS1000
• MOS Technology
  • MCS6500

This list is incomplete; you can help by expanding it.

8 µm Chips

• Intel
  • 1103, 1Kb DRAM, worlds first commercial DRAM

This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information.