The 16 µm lithography process was the semiconductor process technology used by semiconductor companies during the late 1960s. This process had an effective channel length of roughly 16 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process at companies such as Fairchild was 1.25 inch (32 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages.

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