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Difference between revisions of "3 µm lithography process"
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== Industry == | == Industry == | ||
− | {{ | + | |
− | | | + | {{nodes comp |
− | | | + | <!-- Hitachi --> |
− | | | + | | process 1 fab = [[Hitachi]] |
− | | | + | | process 1 name = Hi-CMOS I |
− | | | + | | process 1 date = 1978 |
− | | | + | | process 1 lith = |
− | | | + | | process 1 immersion = |
+ | | process 1 exposure = | ||
+ | | process 1 wafer type = Bulk | ||
+ | | process 1 wafer size = | ||
+ | | process 1 transistor = Planar | ||
+ | | process 1 volt = 5 V | ||
+ | | process 1 layers = 1 | ||
+ | | process 1 delta from = N/A | ||
+ | | process 1 gate len = 3 µm² | ||
+ | | process 1 gate len Δ = - | ||
+ | | process 1 cpp = | ||
+ | | process 1 cpp Δ = - | ||
+ | | process 1 mmp = | ||
+ | | process 1 mmp Δ = - | ||
+ | | process 1 sram hp = | ||
+ | | process 1 sram hp Δ = - | ||
+ | | process 1 sram hd = 896 µm² | ||
+ | | process 1 sram hd Δ = - | ||
+ | | process 1 sram lv = | ||
+ | | process 1 sram lv Δ = - | ||
+ | | process 1 dram = | ||
+ | | process 1 dram Δ = - | ||
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== 3 μm Microprocessors == | == 3 μm Microprocessors == | ||
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== References == | == References == | ||
− | * Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798. | + | * Hitachi |
− | * Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984. | + | ** Sakai, Yoshio, et al. "High packing density, high speed CMOS (Hi-CMOS) device technology." Japanese Journal of Applied Physics 18.S1 (1979): 73. |
+ | ** Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798. | ||
+ | ** Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984. | ||
[[Category:Lithography]] | [[Category:Lithography]] |
Revision as of 17:30, 8 April 2017
The 3 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s.
Industry
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Metal Layers | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Hitachi | |
---|---|
Hi-CMOS I | |
1978 | |
Bulk | |
Planar | |
5 V | |
1 | |
Value | N/A |
3 µm² | N/A |
896 µm² | |
3 μm Microprocessors
- Intel
- Novix NC4016
- Dec
- Siemens
- Fairchild
- Toshiba
- National
- ARM
This list is incomplete; you can help by expanding it.
3 μm Microcontrollers
3 μm Chips
References
- Hitachi
- Sakai, Yoshio, et al. "High packing density, high speed CMOS (Hi-CMOS) device technology." Japanese Journal of Applied Physics 18.S1 (1979): 73.
- Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
- Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.