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Difference between revisions of "3 µm lithography process"
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== References == | == References == | ||
+ | * Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798. | ||
* Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984. | * Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984. | ||
[[Category:Lithography]] | [[Category:Lithography]] |
Revision as of 05:40, 4 April 2017
The 3 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s.
Industry
Fab |
---|
Process Name |
1st Production |
Voltage |
|
Gate Length |
Interconnect Pitch (M1P) |
SRAM bit cell |
Hitachi |
---|
Hi-CMOS I |
? |
5 V |
Value |
3 µm |
3 µm |
896 µm² |
3 μm Microprocessors
- Intel
- Novix NC4016
- Dec
- Siemens
- Fairchild
- Toshiba
- National
- ARM
This list is incomplete; you can help by expanding it.
3 μm Microcontrollers
3 μm Chips
References
- Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
- Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.