Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "16 µm lithography process"
m (Bot: Automated text replacement (-Category:Lithography +category:lithography)) |
|||
| (One intermediate revision by one other user not shown) | |||
| Line 1: | Line 1: | ||
{{lithography processes}} | {{lithography processes}} | ||
| − | The '''16 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the late 1960s. This process had an effective channel length of roughly 16 µm between the source and drain (Poly-SI channel implant). The typical [[wafer]] | + | The '''16 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the late 1960s. This process had an effective channel length of roughly 16 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this process was 1.1-inch (28 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages. |
{{stub}} | {{stub}} | ||
| − | [[ | + | [[category:lithography]] |
Latest revision as of 22:04, 20 May 2018
Semiconductor lithography processes technology
The 16 µm lithography process was the semiconductor process technology used by semiconductor companies during the late 1960s. This process had an effective channel length of roughly 16 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process was 1.1-inch (28 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages.
 |
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |