Semiconductor & Computer Engineering
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Difference between revisions of "20 µm lithography process"
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| − | The '''20 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the | + | The '''20 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the mid 1960s. 20 µm was roughly the pitch between the centers of two smallest-sized transistors. The typical [[wafer]] size for this process at companies such as [[Fairchild]] was 0.875 inch (22 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages. |
Revision as of 02:22, 26 April 2016
Semiconductor lithography processes technology
The 20 µm lithography process was the semiconductor process technology used by semiconductor companies during the mid 1960s. 20 µm was roughly the pitch between the centers of two smallest-sized transistors. The typical wafer size for this process at companies such as Fairchild was 0.875 inch (22 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages.
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