Search results for "ROM" - WikiChip

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Property:rom

This is a '''[[has type::quantity]]''' property representing the size of the ROM of the microcontroller/IC.

379 bytes (49 words) - 01:02, 19 May 2016
Property:rom breakdown

This is a '''[[has type::string]]''' property representing the size of the ROM in breakdown representation.

152 bytes (23 words) - 03:20, 20 January 2016

Page text matches

mirc/component object model

VRAM,SRAM,RAM,ROM,Flash,EEPROM,FEPROM,EPROM,CDRAM,3DRAM,SDRAM,SGRAM, $&

27 KB (3,608 words) - 11:41, 25 October 2018
intel/mcs-4/4004

...onal data bus pins || rowspan="4" | Address and data communication to the ROM and RAM occurs on D0-D3. | 8 || Sync || ROM & RAM Sync || Synchronizes the ROM and RAM by signaling the clock is on the rising edge.

5 KB (748 words) - 21:37, 21 November 2021
microprocessor

...icroprocessor that contains a few additional components such as [[RAM]], [[ROM]], and programmable [[I/O]] ports primarily designed to control and drive o

8 KB (1,149 words) - 00:41, 16 September 2019
toshiba/t3400/t3472

| rom = 768 B | rom break = 256x24 bit

1 KB (119 words) - 14:45, 3 February 2016
fairchild/pps-25

| {{\|3810}} || Program ROM

2 KB (291 words) - 23:48, 10 July 2017
hitachi/hmcs-4

...d for the family with the exception of the ROM chip which used an existing ROM chip. | {{hitachi|HN35600}} || ROM

2 KB (266 words) - 00:54, 19 May 2016
microprocessors used in spacecrafts

...discrete logic|discrete IC]] RTL || 2.048 MHz || 4 KB (RAM)<br />73.73 KB (ROM) || 70 lb

11 KB (1,334 words) - 18:26, 10 May 2019
general instrument/sba

! Part !! [[RAM]] !! [[ROM]] !! I/O Ports !! Notes

2 KB (244 words) - 00:33, 19 May 2016
general instrument/sba/sba-1

...chip ROM. ROM data lines instead were brought out allowing external RAM or ROM to be hooked up.

1 KB (140 words) - 05:28, 22 January 2016
hitachi/hmcs40

...10-bit ea) of program [[ROM]]. Additional 128 Words (10-bit ea) of pattern ROM. 32 to 160 digits (4-bit ea) of data [[RAM]]. Chips also contained Event/Ti ! Model !! ROM !! RAM !! Registers !! Stack Registers !! I/O Lines !! Part No.

4 KB (400 words) - 19:05, 24 May 2016
matsushita/mn1400

| {{\|MN1400}} || 1024x8 ROM, 64x4 RAM || NMOS || General Purpose | {{\|MN1402}} || 7684x8 ROM, 32x4 RAM || NMOS ||

4 KB (462 words) - 19:14, 13 October 2019
matsushita/mn1500

| {{matsushita|MN1542}} || 2048x8 ROM, 152x4 RAM, 28 I/O || NMOS || | {{matsushita|MN1544}} || 4096x8 ROM, 256x4 RAM, 28 I/O || NMOS ||

3 KB (301 words) - 19:23, 13 October 2019
national semiconductor/cops i

| {{\|MM5781}} || [[Control Unit]] (16k ROM) | {{\|MM5129}} || [[Control Unit]] (32k ROM)

2 KB (274 words) - 18:29, 5 February 2016
national semiconductor/cops ii

! Part !! ROM !! RAM !! Frequency !! Package !! Notes | {{\|COP402}} || || 256 b || 250 kHz - 500 kHz || DIP40 || ROM-less version of {{\|COP420}}, for prototyping

6 KB (685 words) - 22:49, 5 February 2016
western digital/cr1872 series

| {{wd|CR1872}} || 32x4-bit RAM, 512x10-bit ROM | {{wd|CR2272}} (WD40) || 32x4-bit RAM, 512x10-bit ROM, LED driver, [[DIL-40]]

732 bytes (87 words) - 01:08, 6 November 2015
mitsubishi/melps 4

! Part !! ROM !! RAM !! Frequency !! I/O<br>Ports !! Package !! Notes ...kHz - 600 kHz || 25 || DIP64 || MELPS 4 System Evaluation Device (external ROM)

4 KB (388 words) - 19:48, 6 February 2016
fujitsu/mb8840

! Part !! ROM !! RAM !! I/O Ports !! Instructions !! Notes

2 KB (263 words) - 14:57, 4 February 2016
fujitsu/mb88500

| {{fujitsu|MB88501}} || 4k x 8-bit ROM, 196x4-bit RAM | {{fujitsu|MB88501H}} || 4k x 8-bit ROM, 256x4-bit RAM

2 KB (215 words) - 14:55, 4 February 2016
fujitsu/mb8850

! Part !! ROM !! RAM !! I/O Ports !! Instructions !! Notes

2 KB (230 words) - 07:46, 28 February 2017
national semiconductor/maps

| {{\|MM5703}} || Control ROM (extension) | {{\|MM5705}} || Control ROM

2 KB (276 words) - 18:29, 29 January 2016
national semiconductor/mm5700

| {{national|MM57123}} || Scientific Calculator ROM | {{national|MM57136}} || RPN Scientific calculator control ROM

2 KB (231 words) - 05:26, 10 November 2015
american microsystems/s2000

! Part !! ROM !! RAM !! Notes

2 KB (280 words) - 00:57, 19 May 2016
epson/s1c63

! Part !! RAM !! ROM !! I/O Ports !! Package ! Part !! RAM !! ROM !! I/O Ports !! Package

5 KB (620 words) - 21:04, 7 February 2016
ti/tms1000

...market in 1974. A few dozen different variations were created with various ROM and RAM sizes. Due to its cheap price, the TMS1000 family enjoyed a tremend ! Part Number !! ROM !! RAM !! I/O Pins !! Technology !! Notes

6 KB (711 words) - 04:39, 26 April 2017
intel/mcs-4

The MCS-4 can be minimally functioning with just the [[/4001|4001]] [[ROM]] and the [[/4004|4004]] [[CPU]], however its designed to be fully function | [[/4001|4001]] || [[ROM]]

4 KB (433 words) - 22:40, 27 June 2019
epson/s1c60

! Part !! RAM !! ROM !! In Ports !! Out Ports !! Package

2 KB (295 words) - 21:03, 7 February 2016
microcontroller

...roprocessor]] that contains a few additional components such as [[RAM]], [[ROM]], and programmable I/O ports primarily designed to control and drive other

2 KB (344 words) - 15:51, 21 March 2024
dec/lsi-11

| {{\|3007}} || Instruction Set ROM (1) || {{wd|MCP-1600/CP1631-07|CP1631-07}} | {{\|3010}} || Instruction Set ROM (2) || {{wd|MCP-1600/CP1631-10|CP1631-10}}

2 KB (253 words) - 00:33, 19 May 2016
western digital/mcp-1600

| {{\|CP1631-07}} || Instruction Set ROM (1) | {{\|CP1631-10}} || Instruction Set ROM (2)

1 KB (148 words) - 01:04, 19 May 2016
general instrument/pic

...GI introduce the first members of the PIC family the {{\|PIC1650}} and its rom-less version, the {{\|PIC1664}}. Realizing its potential as a stand-alone c ! Part !! I/O Ports !! ROM !! Notes

3 KB (423 words) - 00:33, 19 May 2016
rockwell international/pps-4

...ght corner along with the {{\|10706}} clock generator, GP I/O {{\|10696}}, ROM ({{\|A05|A05xx}}), RAM ({{\|10432}}), and a [[7400 series]] 74154 decoder. | {{\|A05xx}} || [[ROM]] ||

3 KB (359 words) - 17:26, 19 May 2016
nec/μcom-42

<tr><th>Model</th><th>Part</th><th>Introduction</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?rom breakdown

2 KB (316 words) - 00:54, 19 May 2016
nec/μcom-42/μpd548

| rom = 2.4 kB | rom break = 1920x10 bit

2 KB (183 words) - 05:49, 20 January 2016
Property:ram

* [[Property:rom]]

379 bytes (49 words) - 01:02, 19 May 2016
Property:rom

This is a '''[[has type::quantity]]''' property representing the size of the ROM of the microcontroller/IC.

379 bytes (49 words) - 01:02, 19 May 2016
Property:ram breakdown

* [[Property:rom breakdown]]

152 bytes (23 words) - 03:20, 20 January 2016
Property:rom breakdown

This is a '''[[has type::string]]''' property representing the size of the ROM in breakdown representation.

152 bytes (23 words) - 03:20, 20 January 2016
nec/μcom-42/μpd555

| rom = | rom break =

2 KB (198 words) - 07:26, 20 January 2016
nec/μcom-43

<tr><th>Model</th><th>Part</th><th>Introduction</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?rom breakdown

2 KB (288 words) - 16:58, 8 November 2016
nec/μcom-43/μpd546

| rom = 2.5 kB | rom break = 2000x10 bit

1 KB (149 words) - 18:28, 20 January 2016
nec/μcom-43/μpd556

| rom = | rom break =

2 KB (258 words) - 05:24, 1 August 2018
nec/μcom-44

<tr><th>Model</th><th>Part</th><th>Introduction</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?rom breakdown

2 KB (280 words) - 01:00, 19 May 2016
nec/μcom-45

<tr><th>Model</th><th>Part</th><th>Introduction</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?rom breakdown

2 KB (290 words) - 01:00, 19 May 2016
nec/μcom-44/μpd547

| rom = 1.25 kB | rom break = 1000x10 bit

1 KB (144 words) - 08:59, 20 January 2016
nec/μcom-45/μpd550

| rom = 640 B | rom break = 640x8 bit

1 KB (159 words) - 09:30, 20 January 2016
nec/μcom-43/μpd553

| rom = 2 kB | rom break = 2000x8 bit

2 KB (180 words) - 11:43, 22 January 2016
nec/μcom-43/μpd650

| rom = 2.5 kB | rom break = 2000x10 bit

1 KB (162 words) - 21:12, 20 January 2016
nec/μcom-44/μpd547l

| rom = 1.25 kB | rom break = 1000x10 bit

1 KB (170 words) - 22:35, 20 January 2016
nec/μcom-44/μpd651

| rom = 1.25 kB | rom break = 1000x10 bit

1 KB (168 words) - 22:58, 20 January 2016
nec/μcom-44/μpd552

| rom = 1.25 kB | rom break = 1000x10 bit

1 KB (159 words) - 22:58, 20 January 2016
nec/μcom-45/μpd554

| rom = 1 kB | rom break = 1000x8 bit

2 KB (184 words) - 13:17, 22 January 2016
nec/μcom-45/μpd652

| rom = 1 kB | rom break = 1000x8 bit

1 KB (160 words) - 00:35, 21 January 2016
general instrument/sba/sba

| rom = 1.024 kB | rom break = 1024x8 bits

1 KB (114 words) - 05:27, 22 January 2016
nec/μcom-43/μpd557l

| rom = 2 kB | rom break = 2000x8 bit

2 KB (244 words) - 06:13, 1 August 2018
nec/μcom-45/μpd550l

| rom = 640 B | rom break = 640x8 bit

1 KB (171 words) - 13:22, 22 January 2016
nec/μcom-45/μpd554l

| rom = 1 kB | rom break = 1000x8 bit

1 KB (184 words) - 13:22, 22 January 2016
rockwell international/pps-4-1

! Part !! RAM !! ROM !! I/O Ports !! Notes

2 KB (219 words) - 01:00, 19 May 2016
intel/mcs-40

| {{\|4308}} || 1024x8 bits [[ROM]] (equivalent of [[intel/mcs-4/4001|4001]]) | {{\|4316}} || 2048x8 bits [[ROM]]

2 KB (177 words) - 15:36, 12 May 2016
toshiba/t3400

<tr><th>Model</th><th>Part</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?rom breakdown

2 KB (233 words) - 15:20, 3 February 2016
toshiba/t3400/t3444

| rom = 768 B | rom break = 256x24 bit

1 KB (146 words) - 11:49, 23 May 2021
hitachi/hd404720

! Part !! program ROM !! pattern ROM !! RAM !! I/O Ports !! Notes

2 KB (214 words) - 15:55, 4 February 2016
hitachi/hmcs400

! Part !! ROM !! RAM !! Line !! Notes

9 KB (1,127 words) - 20:43, 8 February 2016
rca/epic

| {{\|GP301}} || [[ROM]] (4096x4-bit) | {{\|GP302}} || [[ROM]] (4096x4-bit)

3 KB (297 words) - 22:54, 24 April 2016
atmel/marc4

! Part !! ROM<br>(Prog) !! ROM<br>(Data) !! RAM !! I/O Ports !! Package !! Mem Type !! Notes | {{\|ATAR080}} || 2 kB || || 256x4 b || 12 || SO20 || ROM ||

6 KB (787 words) - 21:05, 7 February 2016
oki/olms-64

! Part !! ROM !! RAM !! I/O !! Stack !! Package !! Notes

3 KB (275 words) - 23:03, 7 February 2016
oki/olms-65

! Part !! ROM !! RAM !! I/O !! Stack !! Package !! Notes

2 KB (224 words) - 22:21, 7 February 2016
oki/olms-60

! Part !! ROM !! RAM !! I/O !! Stack !! Inst. !! Frequency !! Package !! Notes

2 KB (200 words) - 22:58, 7 February 2016
oki/olms-50

! Part !! ROM !! RAM !! I/O !! Stack !! Inst. !! Frequency !! Package !! Notes

2 KB (235 words) - 22:56, 7 February 2016
oki/olms-40

! Part !! ROM !! RAM !! I/O !! Stack !! Inst. !! Frequency !! Package !! Notes

2 KB (225 words) - 22:47, 7 February 2016
sharp corporation/sm

! Part !! Tech !! ROM !! RAM !! Description

2 KB (260 words) - 19:14, 8 February 2016
fairchild/f8

| {{\|3851}} || [[ROM]] ! Part !! I/O Lines !! Regs !! RAM !! ROM !! Description

2 KB (172 words) - 17:18, 12 December 2016
intel/mcs-80

| {{intel|2716}} || 2048x8 bit || EPROM (pin compatible with {{intel|2316E}} ROM) | {{intel|8308}} || 1024x8 bit || MOS ROM (pin compatible with {{intel|8708}} PROM)

4 KB (406 words) - 16:10, 26 January 2019
intel/microarchitectures/bonnell

...directly. Those selected few get diverted into the '''micro-code sequencer ROM''' ('''MSROM''') for decoding producing much more sane RISCish instructions

38 KB (5,468 words) - 20:29, 23 May 2019
intel/microarchitectures/haswell (client)

...µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads.

27 KB (3,750 words) - 06:57, 18 November 2023
intel/microarchitectures/sandy bridge (client)

...ur µOPs, the instruction detours through the [[microcode sequencer]] (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode seq ...he two threads and can also hold pointers to the [[microcode sequencer]] [[ROM]]. It's also virtually addressed and is a strict subset of the L1 instructi

84 KB (13,075 words) - 00:54, 29 December 2020
intel/microarchitectures/skylake (client)

...ur µOPs, the instruction detours through the [[microcode sequencer]] (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode seq

79 KB (11,922 words) - 06:46, 11 November 2022
exponential technology/x704

...ify their ROM. In mid-April Apple agreed to provide clones with a modified ROM but at higher charge (supposedly proportional to the processor speed used). ...ount of time. As a last straw; Apple never delivered the promised modified ROM.

8 KB (1,228 words) - 20:49, 2 June 2019
p-rating

...s CD-ROM (PC Magazine Labs)]; Ziff-Davis Publishing Group PC Benchmarks CD-ROM, including Winstone 96 and Winbench 96 benchmarks. From PC Magazine Labs, i

3 KB (456 words) - 06:30, 8 July 2020
amd/microarchitectures/zen

...at end up emitting more than two macro-ops will be redirected to microcode ROM. When this happens the OP Queue is stalled (possibly along with the decoder ...a secured kernel with the firmware which sits externally (e.g., on an SPI ROM). The secure processor is responsible for the cryptographic functionalities

79 KB (12,095 words) - 15:27, 9 June 2023
amd/microarchitectures/zen 2

...nd at this stage probably represented by a macro-op containing a microcode ROM entry address. In the Zen/Zen+ microarchitecture AVX-256 instructions which ...f macro-ops from the micro-op queue. A patch RAM supplements the microcode ROM and can hold additional sequences. The microcode sequencer supports branchi

57 KB (8,701 words) - 22:11, 9 October 2022
mos technology

*{{mos|6530}} ROM/RAM I/O Timer (RRIOT)

2 KB (269 words) - 18:40, 31 August 2021
acorn/microarchitectures/arm1

...number of separate units is because the ARM1 makes use of [[microcode]] [[ROM]]s ([[PLA]]). Each instruction is decoded into up to four [[µOP]] signal-w

12 KB (1,886 words) - 12:56, 14 January 2021
dec/microarchitectures/alpha 21064

* Directly serial ROM interface

4 KB (527 words) - 02:09, 4 August 2017
acorn/microarchitectures/arm2

...number of separate units is because the ARM2 makes use of [[microcode]] [[ROM]]s ([[PLA]]). Each instruction is decoded into up to four [[µOP]] signal-w

14 KB (2,093 words) - 04:42, 10 July 2018
renesas/r-car/h2

* Flash ROM and SRAM, Data bus width: 8 or 16 bits

3 KB (420 words) - 16:32, 13 December 2017
renesas/r-car/m2

* Flash ROM and SRAM, Data bus width: 8 or 16 bits

3 KB (409 words) - 16:32, 13 December 2017
renesas/r-car/e2

* Flash ROM and SRAM, Data bus width: 8 or 16 bits

3 KB (409 words) - 16:32, 13 December 2017
renesas/r-car/v2h

* Flash ROM and SRAM Data bus width: 8/16 bit

2 KB (346 words) - 16:32, 13 December 2017
ti/tms1000/tms1099

The TMS1099JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 64x4 bits of RAM, 8 bits o This ROM-less version addresses 1024 x 8 bits on an external memory (EPROM).

824 bytes (121 words) - 14:56, 13 December 2017
ti/tms1000/tms1098

The TMS1098JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 128x4 bits of RAM, 8 bits This ROM-less version addresses 2048 x 8 bits on an external memory (EPROM).

900 bytes (128 words) - 14:56, 13 December 2017
intel/documents

...', a complete offerings of their products including [[microprocessors]], [[ROM]]s, [[RAM]]s, [[memory]] peripherals, and various other [[ICs]].

4 KB (448 words) - 15:02, 3 October 2019
amd/packages/socket tr4

|PSP_ROM_CS_L<br/>SPI_TPM_CS_L||O-IO18-S||SPI Chip Select for {{abbr|PSP}} ROM or {{abbr|TPM}}

86 KB (17,313 words) - 02:48, 13 March 2023
amd/packages/socket sp3

|PSP_ROM_CS_L<br/>SPI_TPM_CS_L||O-IO18-S||SPI Chip Select for {{abbr|PSP}} ROM or {{abbr|TPM}} |LPC||ROM,||1=SPI ROM (default)

110 KB (21,122 words) - 02:46, 13 March 2023
intel/microarchitectures/sunny cove

...ur µOPs, the instruction detours through the [[microcode sequencer]] (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode seq

34 KB (5,187 words) - 06:27, 17 February 2023
centaur/microarchitectures/cha

*** Instruction ROM ...simultaneously controls all the compute slices and memory. The instruction ROM is used for executing validation code as well as commonly-used functions. T

24 KB (3,792 words) - 04:37, 30 September 2022
amd/List of AMD publications

|24406||||AMD Mobile Thermal Kit Documentation and Software CD–ROM||||Family 6 {{amd publ|an|key=AMD-Au1000-BootROM|rev=1.2|title=Mapping a Boot ROM on Alchemy™ Au1000™ Processor from AMD|url=https://web.archive.org/web/

181 KB (24,861 words) - 16:02, 17 April 2022
eta compute/ecm353x/ecm3532

* 8 KiB ROM

3 KB (460 words) - 02:24, 12 February 2020
amd/packages/fp6

|SPI_CS(1-3)_L||Chip Select for SPI ROM or other devices |SPI_ROM_REQ||SPI ROM Request

20 KB (3,273 words) - 17:47, 10 May 2023
alchemy/au1200-333mgc

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

6 KB (862 words) - 01:16, 19 March 2022
alchemy/au1000-266mcc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (607 words) - 00:41, 16 March 2022
alchemy/au1000-266mci

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (614 words) - 00:45, 16 March 2022
alchemy/au1000-400mcc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (594 words) - 00:47, 16 March 2022
alchemy/au1000-500mcc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (594 words) - 00:50, 16 March 2022
alchemy/au1500-333mbc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (562 words) - 01:07, 16 March 2022
alchemy/au1500-333mbd

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (559 words) - 01:10, 16 March 2022
alchemy/au1500-333mbf

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (566 words) - 01:12, 16 March 2022
alchemy/au1500-333mbi

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (573 words) - 01:15, 16 March 2022
alchemy/au1500-400mbc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (553 words) - 01:17, 16 March 2022
alchemy/au1500-400mbd

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (546 words) - 01:20, 16 March 2022
alchemy/au1500-500mbc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (553 words) - 01:25, 16 March 2022
alchemy/au1500-500mbd

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (546 words) - 01:29, 16 March 2022
alchemy/au1100-333mbc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (621 words) - 08:44, 17 March 2022
alchemy/au1100-333mbd

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (624 words) - 08:46, 17 March 2022
alchemy/au1100-333mbf

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (631 words) - 08:49, 17 March 2022
alchemy/au1100-333mbi

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (632 words) - 08:51, 17 March 2022
alchemy/au1100-400mbc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (612 words) - 08:55, 17 March 2022
alchemy/au1100-400mbd

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (611 words) - 08:58, 17 March 2022
alchemy/au1100-500mbc

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (612 words) - 09:00, 17 March 2022
alchemy/au1100-500mbd

...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su

4 KB (611 words) - 09:02, 17 March 2022
alchemy/au1550-333mbc

...d 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O perip

4 KB (613 words) - 09:17, 17 March 2022
alchemy/au1550-333mbd

...d 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O perip

4 KB (616 words) - 09:23, 17 March 2022
alchemy/au1550-333mbf

...d 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O perip

4 KB (623 words) - 09:25, 17 March 2022
alchemy/au1550-333mbi

...d 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O perip

4 KB (624 words) - 09:28, 17 March 2022
alchemy/au1550-400mbc

...d 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O perip

4 KB (604 words) - 09:30, 17 March 2022
alchemy/au1550-400mbd

...d 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O perip

4 KB (603 words) - 09:32, 17 March 2022
alchemy/au1550-500mbc

...d 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O perip

4 KB (604 words) - 09:33, 17 March 2022
alchemy/au1550-500mbd

...d 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O perip

4 KB (603 words) - 09:38, 17 March 2022
alchemy/au1200-333mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

6 KB (865 words) - 01:18, 19 March 2022
alchemy/au1200-333mgf

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

6 KB (872 words) - 01:19, 19 March 2022
alchemy/au1200-333mgi

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

6 KB (873 words) - 01:23, 19 March 2022
alchemy/au1200-400mgc

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

6 KB (859 words) - 01:24, 19 March 2022
alchemy/au1200-400mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

6 KB (858 words) - 01:26, 19 March 2022
alchemy/au1200-500mgc

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

6 KB (853 words) - 01:27, 19 March 2022
alchemy/au1200-500mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

6 KB (852 words) - 01:30, 19 March 2022
alchemy/au1210-333mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (645 words) - 01:47, 19 March 2022
alchemy/au1210-333mgf

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (652 words) - 01:50, 19 March 2022
alchemy/au1210-400mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (645 words) - 01:51, 19 March 2022
alchemy/au1210-400mgf

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (652 words) - 01:53, 19 March 2022
alchemy/au1250-400mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (661 words) - 01:55, 19 March 2022
alchemy/au1250-400mgf

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (668 words) - 01:57, 19 March 2022
alchemy/au1250-500mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (661 words) - 01:58, 19 March 2022
alchemy/au1250-500mgf

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (668 words) - 01:59, 19 March 2022
alchemy/au1250-600mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (648 words) - 02:00, 19 March 2022
alchemy/au1250-700mgd

...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,

5 KB (641 words) - 02:05, 19 March 2022
alchemy/alchemy

...address bus and supports SRAM, ROM, standard Flash memory, page mode Flash/ROM, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD c ...as an interface with 32-bit data and 29-bit address bus and supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, and I/O peripherals.

31 KB (4,972 words) - 03:09, 20 March 2022
amd/packages/socket sp5

...I/ESPI}}. These busses are generally used to access firmware ({{abbr|PSP}} ROM and BIOS) i.e. flash memory, and a {{abbr|TPM}}. Socket SP5 also reserves s

105 KB (21,123 words) - 02:59, 13 March 2023
amd/packages/socket am5

...I/ESPI}}. These busses are generally used to access firmware ({{abbr|PSP}} ROM and BIOS) i.e. flash memory, and a {{abbr|TPM}}. It is worth noting that th |SPI/SPI1_CS(1-2)_L||Chip Select for SPI ROM

19 KB (3,162 words) - 17:35, 11 May 2023

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