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- ...ors can be cascaded to produce any conventional (e.g. [[4-bit architecture|4-bit]], [[8-bit architecture|8-bit]], [[16-bit architecture|16-bit]]) as wel | || Intel || National || AMD || MMI || TI || Fairchild || Motorola || RCA ||2 KB (253 words) - 07:12, 13 March 2019
- | arch = 4-bit bit-slice | word = 4 bit2 KB (179 words) - 00:03, 3 February 2016
- ...[[microprocessor family|family]] of chips known as the {{nec|μCOM-4|μCOM-4 family}}. [[Category:4-bit microprocessors]]730 bytes (96 words) - 05:05, 18 February 2020
- ...eloped by [[NEC]] in December of 1971, just a month after the {{intel|4004|Intel 4004}}. The 4004 served an inspiration for NEC which went on to combine the After hearing about the {{intel|4004|Intel 4004}}, NEC later combined the two chips in the {{nec|μPD751}} - the first1 KB (171 words) - 08:04, 20 November 2018
- {{intel title|3000}} | title = Intel 3000 Series3 KB (308 words) - 05:03, 18 February 2020
- {{national title|IMP-4}} | title = National IMP-42 KB (247 words) - 00:32, 19 May 2016
- #REDIRECT [[intel/mcs-4/4004]]30 bytes (3 words) - 00:33, 24 December 2015
- [[File:intel mask.jpg|right|thumb|Modern Intel 6" [[14 nm]]/[[10 nm]] test reticle.]] Below is a 5-inch IBM reticle next to a 4-inch AMI Semi photomask.3 KB (533 words) - 17:17, 29 January 2024
- | image = <!-- Image representation of the IC family, e.g. "MCS-4.jpg" --> | word = 4 bit6 KB (711 words) - 04:39, 26 April 2017
- {{intel title|MCS-4}} | title = Intel MCS-44 KB (433 words) - 22:40, 27 June 2019
- #REDIRECT [[intel/mcs-4/4004]]30 bytes (3 words) - 00:32, 24 December 2015
- #REDIRECT [[intel/mcs-4/4004]]30 bytes (3 words) - 00:34, 24 December 2015
- #REDIRECT [[intel/mcs-4]]25 bytes (3 words) - 00:34, 24 December 2015
- #REDIRECT [[intel/mcs-4]]25 bytes (3 words) - 02:28, 24 December 2015
- {{title|System/4 - Decision Data}} ...reintroduction of the [[UNIVAC BC/7]]. Unlike the UNIVAC BC/7, the System/4 came with an accompanying 9610 Interperting Data Recorder and printers.1 KB (157 words) - 00:03, 26 December 2015
- {{intel title|Core i7-4950HQ}} | name = Intel Core i7-4950HQ4 KB (404 words) - 16:22, 13 December 2017
- {{intel title|Core i7-4960HQ}} | name = Intel Core i7-4960HQ3 KB (401 words) - 14:24, 12 February 2019
- {{intel title|Core i7-4980HQ}} | name = Intel Core i7-4980HQ3 KB (399 words) - 16:22, 13 December 2017
- {{intel title|Core i7-4850HQ}} | name = Intel Core i7-4850HQ3 KB (400 words) - 16:22, 13 December 2017
- {{intel title|Core i7-4860HQ}} | name = Intel Core i7-4860HQ3 KB (399 words) - 16:22, 13 December 2017
- {{intel title|Core i7-4870HQ}} |name=Intel Core i7-4870HQ3 KB (386 words) - 09:14, 26 December 2017
- {{intel title|Core i7-4750HQ}} | name = Intel Core i7-4750HQ3 KB (401 words) - 16:22, 13 December 2017
- {{intel title|Core i7-4760HQ}} | name = Intel Core i7-4760HQ3 KB (397 words) - 16:22, 13 December 2017
- {{intel title|Core i7-4770HQ}} | name = Intel Core i7-4770HQ3 KB (398 words) - 16:22, 13 December 2017
- {{intel title|Core i7-4770R}} | name = Intel Core i7-4770R4 KB (406 words) - 16:22, 13 December 2017
- {{intel title|Core i5-4670R}} | name = Intel Core i5-4670R4 KB (404 words) - 16:19, 13 December 2017
- {{intel title|Core i5-4570R}} | name = Intel Core i5-4570R3 KB (401 words) - 16:19, 13 December 2017
- {{intel title|Core i7-4860EQ}} | name = Intel Core i7-4860EQ3 KB (396 words) - 16:22, 13 December 2017
- {{intel title|Core i7-4850EQ}} | name = Intel Core i7-4850EQ3 KB (391 words) - 16:22, 13 December 2017
- {{intel title|Xeon E3-1284L v3}} | name = Intel Xeon E3-1284L v33 KB (399 words) - 16:27, 13 December 2017
- {{intel title|Celeron 3855U}} |designer=Intel4 KB (596 words) - 16:15, 13 December 2017
- {{intel title|Celeron 3955U}} |designer=Intel4 KB (596 words) - 16:15, 13 December 2017
- {{intel title|Core i3-6098P}} |designer=Intel4 KB (627 words) - 16:17, 13 December 2017
- {{intel title|Core i5-6402P}} |designer=Intel4 KB (627 words) - 16:20, 13 December 2017
- {{intel title|Core i7-6498DU}} |designer=Intel4 KB (640 words) - 02:21, 16 January 2019
- {{intel title|Core i5-6198DU}} |name=Intel Core i5-6198DU4 KB (650 words) - 02:21, 16 January 2019
- {{intel title|Core i7-5500DU}} | name = Intel Core i7-5500DU5 KB (469 words) - 16:22, 13 December 2017
- {{intel title|Iris Pro Graphics}} | title = Intel Iris Pro Graphics1 KB (176 words) - 17:29, 3 December 2016
- {{intel title|Core i7-5950HQ}} | name = Intel Core i7-5950HQ4 KB (407 words) - 16:22, 13 December 2017
- {{intel title|Core i7-5850HQ}} | name = Intel Core i7-5850HQ4 KB (401 words) - 16:22, 13 December 2017
- {{intel title|Core i7-5850EQ}} | name = Intel Core i7-5850EQ4 KB (395 words) - 16:22, 13 December 2017
- {{intel title|Core i7-5750HQ}} | name = Intel Core i7-5750HQ4 KB (424 words) - 16:22, 13 December 2017
- {{intel title|Core i7-5775R}} | name = Intel Core i7-5775R4 KB (405 words) - 16:22, 13 December 2017
- {{intel title|Core i7-5775C}} |name=Intel Core i7-5775C4 KB (460 words) - 15:03, 24 March 2019
- {{intel title|Core i5-5675R}} | name = Intel Core i5-5675R4 KB (409 words) - 16:19, 13 December 2017
- {{intel title|Core i5-5675C}} | name = Intel Core i5-5675C4 KB (454 words) - 18:17, 2 November 2019
- {{intel title|Core i5-5575R}} | name = Intel Core i5-5575R4 KB (409 words) - 16:19, 13 December 2017
- {{intel title|Core i5-5350H}} | name = Intel Core i5-5350H4 KB (415 words) - 16:19, 13 December 2017
- {{intel title|Iris Graphics}} | title = Intel Iris Graphics2 KB (181 words) - 13:08, 18 March 2017
- {{intel title|Core i3-6167U}} |designer=Intel4 KB (631 words) - 16:18, 13 December 2017
- {{intel title|Core i5-6287U}} |designer=Intel4 KB (649 words) - 16:20, 13 December 2017
- ...idth or a highest [[operand]] width (i.e. natural word size) of 32 bits or 4 [[octet]]s. These architectures typically have a matching [[register file]] '''Intel'''1 KB (137 words) - 19:55, 5 December 2019
- | package 4 = DIP64 ...600, however was losing market share due to increasing competition (e.g. {{intel|8086}}, {{motorola|68K}}, et al). One of the major shortcomings of the CP163 KB (423 words) - 00:33, 19 May 2016
- {{rockwell title|PPS-4}} | title = Rockwell PPS-43 KB (359 words) - 17:26, 19 May 2016
- {{intel title|MCS-40}} | title = Intel MCS-402 KB (177 words) - 15:36, 12 May 2016
- {{intel title|Atom}} | title = Intel Atom17 KB (2,292 words) - 09:32, 16 July 2019
- | successor = Athlon 4 | successor link = amd/athlon 410 KB (1,163 words) - 10:41, 26 February 2019
- | developer = Intel | clock max = 4 MHz5 KB (683 words) - 23:46, 7 March 2018
- {{intel title|Pentium}} | title = Intel Pentium10 KB (1,057 words) - 19:30, 1 November 2021
- {{intel title|MCS-8}} | title = Intel MCS-83 KB (382 words) - 17:58, 19 May 2016
- {{intel title|8008 ISA}} | developer = Intel13 KB (2,079 words) - 09:11, 29 September 2019
- {{intel title|8008}} |image=Intel 8008.jpg2 KB (254 words) - 19:24, 23 March 2022
- {{intel title|8008-1}} | image = KL Intel C8008-1.jpg1 KB (151 words) - 16:24, 13 December 2017
- {{intel title|MCS-80}} | title = Intel MCS-804 KB (406 words) - 16:10, 26 January 2019
- | process 2 cpp = 113.4 nm | process 4 fab = [[SMIC]]6 KB (711 words) - 17:01, 26 March 2019
- TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the [[self-aligned vi <!-- Intel -->10 KB (1,090 words) - 19:14, 8 July 2021
- <!-- Intel --> | process 1 fab = [[Intel]]17 KB (2,243 words) - 19:32, 25 May 2023
- {{intel title|Atom x7-Z8750}} | designer = Intel4 KB (462 words) - 16:15, 13 December 2017
- {{intel title|Atom x7-Z8700}} | designer = Intel4 KB (472 words) - 16:15, 13 December 2017
- {{intel title|Atom x5-E8000}} |name=Intel Atom x5-E80004 KB (475 words) - 17:42, 27 March 2018
- {{intel title|Atom x5-Z8500}} | name = Intel Atom x5-Z85005 KB (573 words) - 16:15, 13 December 2017
- {{intel title|Atom x5-Z8550}} | name = Intel Atom x5-Z85505 KB (572 words) - 16:15, 13 December 2017
- {{intel title|Atom x5-Z8300}} | name = Intel Atom x5-Z83006 KB (744 words) - 18:35, 14 January 2019
- {{intel title|Atom x5-Z8350}} |name=Intel Atom x5-Z83505 KB (736 words) - 03:44, 19 August 2023
- {{intel title|Atom x5-Z8330}} | name = Intel Atom x5-Z83305 KB (558 words) - 16:15, 13 December 2017
- {{intel title|Atom x3-C3130}} | designer = Intel4 KB (424 words) - 16:15, 13 December 2017
- {{intel title|Atom x3-C3230RK}} | designer = Intel4 KB (449 words) - 16:15, 13 December 2017
- {{intel title|Atom x3-C3445}} | designer = Intel4 KB (467 words) - 16:15, 13 December 2017
- {{intel title|Atom x3-C3405}} | designer = Intel4 KB (418 words) - 16:15, 13 December 2017
- {{intel title|Atom x3-C3200RK}} | designer = Intel4 KB (412 words) - 16:15, 13 December 2017
- ...ity in Oregon, {{intel|Fab 32}} in Arizona and {{intel|Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used ! colspan="2" | [[Intel]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[TI]] !! colspan="2" | [[T5 KB (602 words) - 05:51, 20 July 2018
- {{intel title|Bonnell|arch}} |designer=Intel38 KB (5,468 words) - 20:29, 23 May 2019
- {{intel title|Saltwell|arch}} | designer = Intel7 KB (872 words) - 19:42, 30 November 2017
- {{intel title|Silvermont|arch}} | designer = Intel9 KB (1,160 words) - 09:35, 25 September 2019
- {{intel title|Airmont|arch}} | designer = Intel5 KB (568 words) - 19:40, 30 November 2017
- {{intel title|Goldmont|arch}} |designer=Intel7 KB (956 words) - 23:05, 23 March 2020
- {{intel title|Pentium}}{{confuse|intel/pentium|l1=Pentium Extended family (1992-present)}} | title = Intel Pentium20 KB (2,661 words) - 00:45, 11 October 2017
- {{intel title|Celeron}} | title = Intel Celeron25 KB (3,201 words) - 03:13, 22 September 2018
- {{intel title|Pentium J3710}} |name=Intel Pentium J37104 KB (529 words) - 17:41, 27 March 2018
- {{intel title|Pentium N3710}} |name=Intel Pentium N37105 KB (701 words) - 17:40, 27 March 2018
- {{intel title|Pentium N3700}} |designer=Intel4 KB (540 words) - 17:40, 27 March 2018
- {{intel title|Celeron N3000}} |name=Intel Celeron N30004 KB (544 words) - 17:43, 27 March 2018
- {{intel title|Celeron N3050}} |name=Intel Celeron N30504 KB (580 words) - 09:40, 8 July 2022
- {{intel title|Celeron N3150}} |name=Intel Celeron N31505 KB (724 words) - 06:10, 2 December 2018
- {{intel title|Celeron N3010}} |name=Intel Celeron N30104 KB (539 words) - 17:39, 27 March 2018
- {{intel title|Celeron N3160}} |name=Intel Celeron N31604 KB (535 words) - 17:39, 27 March 2018
- {{intel title|Celeron N3060}} |name=Intel Celeron N30605 KB (722 words) - 01:50, 24 November 2018
- {{intel title|Celeron J3160}} |name=Intel Celeron J31604 KB (533 words) - 17:41, 27 March 2018
- {{intel title|Celeron J3060}} |name=Intel Celeron J30604 KB (539 words) - 17:39, 27 March 2018
- {{intel title|Xeon D}} | title = Intel Xeon D13 KB (1,784 words) - 08:04, 6 April 2019
- {{intel title|Xeon D-1540}} |designer=Intel4 KB (593 words) - 02:17, 1 April 2019
- {{intel title|Xeon D-1520}} |designer=Intel4 KB (593 words) - 02:18, 1 April 2019
- {{intel title|Xeon D-1518}} |designer=Intel4 KB (582 words) - 02:21, 1 April 2019
- {{intel title|Xeon D-1521}} |designer=Intel4 KB (596 words) - 02:18, 1 April 2019
- {{intel title|Xeon D-1527}} |designer=Intel4 KB (595 words) - 02:16, 1 April 2019
- {{intel title|Xeon D-1528}} |designer=Intel4 KB (595 words) - 02:16, 1 April 2019
- {{intel title|Xeon D-1531}} |designer=Intel4 KB (593 words) - 02:17, 1 April 2019
- {{intel title|Xeon D-1537}} |designer=Intel4 KB (595 words) - 02:16, 1 April 2019
- {{intel title|Xeon D-1541}} |designer=Intel4 KB (596 words) - 02:17, 1 April 2019
- {{intel title|Xeon D-1548}} |designer=Intel4 KB (595 words) - 09:36, 14 May 2021
- {{intel title|Xeon D-1577}} |designer=Intel4 KB (595 words) - 02:16, 1 April 2019
- {{intel title|Xeon D-1567}} |designer=Intel4 KB (595 words) - 02:18, 1 April 2019
- {{intel title|Xeon D-1571}} |designer=Intel4 KB (595 words) - 02:16, 1 April 2019
- {{intel title|Xeon D-1557}} |designer=Intel4 KB (595 words) - 02:17, 1 April 2019
- {{intel title|Broadwell|arch}} |designer=Intel14 KB (1,891 words) - 14:37, 6 January 2022
- {{intel title|Haswell|arch}} |designer=Intel27 KB (3,750 words) - 06:57, 18 November 2023
- {{intel title|Core i7 Extreme Edition (i7EE)}} | title = Intel Core i7 Extreme Edition4 KB (572 words) - 16:03, 1 June 2017
- {{intel title|Core i7-920XM Extreme Edition}} | designer = Intel4 KB (522 words) - 20:46, 4 October 2018
- {{intel title|Core i7-940XM Extreme Edition}} | designer = Intel4 KB (537 words) - 15:01, 13 December 2019
- {{intel title|Ivy Bridge|arch}} | designer = Intel5 KB (689 words) - 13:44, 2 May 2020
- {{intel title|Sandy Bridge (client)|arch}} |designer=Intel84 KB (13,075 words) - 00:54, 29 December 2020
- {{intel title|Westmere|arch}} | designer = Intel10 KB (1,258 words) - 21:07, 9 March 2018
- {{intel title|Nehalem|arch}} | designer = Intel4 KB (459 words) - 21:44, 26 December 2023
- {{intel title|P6|arch}} | designer = Intel3 KB (325 words) - 21:34, 22 February 2020
- {{intel title|Skylake (client)|arch}} |designer=Intel79 KB (11,922 words) - 06:46, 11 November 2022
- {{intel title|Kaby Lake|arch}} |designer=Intel38 KB (5,431 words) - 10:41, 8 April 2024
- {{intel title|Cannon Lake|arch}} |designer=Intel7 KB (887 words) - 12:53, 5 August 2019
- {{intel title|Ice Lake (client)|arch}} |designer=Intel23 KB (3,613 words) - 12:31, 20 June 2021
- {{intel title|Tiger Lake|arch}} |designer=Intel3 KB (406 words) - 10:46, 19 July 2023
- {{intel title|Core i7-975 Extreme Edition}} | designer = Intel4 KB (415 words) - 16:24, 13 December 2017
- {{intel title|Core i7-965 Extreme Edition}} | designer = Intel4 KB (415 words) - 16:24, 13 December 2017
- {{intel title|Core i7-980X Extreme Edition}} | designer = Intel4 KB (419 words) - 16:24, 13 December 2017
- {{intel title|Core i7-990X Extreme Edition}} | designer = Intel4 KB (414 words) - 16:24, 13 December 2017
- ! colspan="2" | [[Intel]] !! colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] !! colspan="2 ! colspan="4" | Intel 65nm Design Rules4 KB (407 words) - 05:55, 20 July 2018
- {{intel title|Core i7-3960X Extreme Edition}} | designer = Intel5 KB (517 words) - 23:32, 22 September 2019
- {{intel title|Core i7-3970X Extreme Edition}} | designer = Intel4 KB (456 words) - 16:24, 13 December 2017
- {{intel title|Core i7-4960X Extreme Edition}} |designer=Intel4 KB (492 words) - 23:23, 12 March 2019
- {{intel title|Core i7-5960X Extreme Edition}} | designer = Intel5 KB (524 words) - 16:24, 13 December 2017
- {{intel title|Core i7-6950X Extreme Edition}} |designer=Intel4 KB (564 words) - 14:29, 24 March 2019
- {{intel title|Core i7-2920XM Extreme Edition}} |designer=Intel5 KB (710 words) - 16:24, 13 December 2017
- {{intel title|Core i7-2960XM Extreme Edition}} |designer=Intel5 KB (710 words) - 03:49, 26 June 2018
- {{intel title|Core i7-3940XM Extreme Edition}} | designer = Intel5 KB (573 words) - 16:24, 13 December 2017
- {{intel title|Core i7-3920XM Extreme Edition}} |designer=Intel4 KB (558 words) - 23:13, 12 March 2019
- {{intel title|Core i7-4930MX Extreme Edition}} | designer = Intel5 KB (544 words) - 16:24, 13 December 2017
- {{intel title|Core i7-4940MX Extreme Edition}} | designer = Intel5 KB (542 words) - 16:24, 13 December 2017
- {{intel title|Core i7-6650U}} |designer=Intel4 KB (649 words) - 16:22, 13 December 2017
- {{intel title|Core i7-6660U}} |designer=Intel4 KB (649 words) - 16:22, 13 December 2017
- {{intel title|Core i7-6600U}} |designer=Intel4 KB (654 words) - 17:22, 26 March 2018
- ! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [ ! colspan="4" | Intel 130nm Design Rules5 KB (500 words) - 16:02, 13 May 2020
- Introduced in late 2002, Intel's 90 nm process became the first volume production to introduce [[strained ! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [3 KB (354 words) - 03:09, 17 August 2023
- ! colspan="2" | [[Intel]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[TSMC]] !! colspan="2" | [ | 5.59 µm<sup>2</sup> || 0.54x || 4.18 µm<sup>2</sup> || ?x || 4.65 µm<sup>2</sup> || 0.62x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup4 KB (413 words) - 03:04, 17 August 2023
- ...are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]]. ...to Intel's 10nm (e.g., Samsung's metal pitch just 1 nanometer shorter than Intel's 14nm).14 KB (1,903 words) - 06:52, 17 February 2023
- ...four companies are currently planning or developing a 7-nanometer node: [[Intel]], [[TSMC]], [[Samsung]] and [[SMIC]]. === Intel ===13 KB (1,941 words) - 02:40, 5 November 2022
- ...the fins and double patterning for the rest of the metal stack. Note that Intel [[7 nm process]] is comparable to the foundry 5-nanometer node. ...three companies are currently planning or developing a 5-nanometer node: [[Intel]], [[TSMC]], and [[Samsung]].11 KB (1,662 words) - 02:58, 2 October 2022
- The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A secon ! colspan="4" | [[Intel]] || colspan="2" | [[IBM]] || colspan="2" | [[AMD]] || colspan="2" | [[TI]]6 KB (661 words) - 16:18, 21 August 2022
- ! colspan="2" | [[Intel]] || colspan="2" | [[IBM]] || colspan="2" | [[AMD]] || colspan="2" | [[AMD] ...|| colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 3 || colspan="2" | 4 || colspan="2" | 5 || colspan="2" | || colspan="2" |5 KB (586 words) - 22:44, 4 April 2022
- ! colspan="2" | [[Intel]] || colspan="2" | [[AMD]] || colspan="2" | [[DEC]] || colspan="2" | [[Fuji ...|| colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 4 || colspan="2" | 4 || colspan="2" | || colspan="2" |4 KB (438 words) - 06:15, 20 July 2018
- ! [[Intel]] || [[Intel]] || [[Motorola]] * Intel1 KB (122 words) - 06:21, 20 July 2018
- ...was used in Intel's {{intel|P55C}} ({{x86|MMX}}) and {{intel|P6|l=arch}} {{intel|Klamath|l=core}} core-based and models. The semi-shrink which resulted in s ! [[Intel]] || [[Motorola]]2 KB (225 words) - 06:11, 20 July 2018
- {{intel title|Turbo Boost Technology (TBT)}} ...a [[microprocessor]] [[instance of::technology]] developed by [[designer::Intel]] that attempts to enable temporary higher performance by opportunistically7 KB (990 words) - 14:39, 23 July 2022
- * {{mil|MF7???}}, second source of [[Intel]]'s {{intel|1103}} 1K DRAM * {{mil|MF7114}}, second source/enhanced version of [[Intel]]'s {{intel|4004}}2 KB (289 words) - 07:23, 29 April 2016
- * April 1: [[Intel]] releases the [[Micro Computer Set-8]] featuring the {{intel|8008}} * August: [[Rockwell International]] releases the {{rockwell|PPS-4}}, a 4-bit microprocessor.375 bytes (44 words) - 09:10, 6 April 2018
- {{intel title|Mobile Pentium II}} | developer = Intel5 KB (635 words) - 09:54, 11 November 2017
- {{intel title|Mobile Pentium II 233}} | designer = Intel3 KB (316 words) - 16:25, 13 December 2017
- {{intel title|Mobile Pentium II 266}} | designer = Intel3 KB (319 words) - 16:25, 13 December 2017
- {{intel title|Mobile Pentium II 300}} | designer = Intel3 KB (313 words) - 16:25, 13 December 2017
- {{intel title|Mobile Pentium II 266PE}} | designer = Intel3 KB (366 words) - 16:25, 13 December 2017
- {{intel title|Mobile Pentium II 300PE}} | designer = Intel3 KB (360 words) - 16:25, 13 December 2017
- {{intel title|Mobile Pentium II 333}} | designer = Intel3 KB (320 words) - 16:25, 13 December 2017
- {{intel title|Mobile Pentium II 366}} | designer = Intel3 KB (309 words) - 16:25, 13 December 2017
- {{intel title|Mobile Pentium II 400}} | designer = Intel3 KB (345 words) - 16:25, 13 December 2017
- {{intel title|80386}} | title = Intel 803864 KB (400 words) - 08:43, 5 December 2022
- {{intel title|Xeon E3-1280 v5}} |designer=Intel3 KB (485 words) - 00:29, 7 April 2018
- {{intel title|Xeon E3-1275 v5}} |designer=Intel4 KB (620 words) - 00:27, 7 April 2018
- {{intel title|Xeon E3-1270 v5}} |designer=Intel3 KB (490 words) - 00:29, 7 April 2018
- {{intel title|Xeon E3-1260L v5}} |designer=Intel3 KB (489 words) - 16:26, 13 December 2017
- {{intel title|Xeon E3-1245 v5}} |designer=Intel4 KB (609 words) - 00:29, 7 April 2018
- {{intel title|Xeon E3-1240L v5}} |designer=Intel3 KB (484 words) - 16:26, 13 December 2017
- {{intel title|Xeon E3-1240 v5}} |designer=Intel3 KB (490 words) - 00:29, 7 April 2018
- {{intel title|Xeon E3-1235L v5}} |designer=Intel4 KB (608 words) - 16:26, 13 December 2017
- {{intel title|Xeon E3-1230 v5}} |designer=Intel3 KB (506 words) - 00:29, 7 April 2018
- {{intel title|Xeon E3-1225 v5}} |designer=Intel4 KB (620 words) - 00:24, 7 April 2018
- {{intel title|Xeon E3-1220 v5}} |designer=Intel3 KB (490 words) - 00:29, 7 April 2018
- {{intel title|Xeon E3-1268L v5}} |designer=Intel4 KB (624 words) - 00:27, 7 April 2018
- {{intel title|Xeon E3-1535M V5}} |designer=Intel4 KB (648 words) - 16:27, 13 December 2017
- {{intel title|Xeon E3-1505M v5}} |designer=Intel4 KB (646 words) - 05:24, 14 July 2018
- {{intel title|Xeon E3-1575M v5}} |designer=Intel4 KB (654 words) - 16:27, 13 December 2017
- {{intel title|Xeon E3-1545M v5}} |designer=Intel4 KB (654 words) - 16:27, 13 December 2017
- {{intel title|Xeon E3-1515M v5}} |designer=Intel4 KB (663 words) - 16:27, 13 December 2017
- {{intel title|Xeon E3-1505L v5}} |designer=Intel4 KB (640 words) - 16:27, 13 December 2017
- {{intel title|Pentium G4520}} |designer=Intel4 KB (607 words) - 16:25, 13 December 2017
- {{intel title|Pentium G4500T}} |designer=Intel4 KB (610 words) - 16:25, 13 December 2017
- {{intel title|Pentium G4500}} |designer=Intel4 KB (616 words) - 16:25, 13 December 2017
- {{intel title|Pentium G4400}} |designer=Intel4 KB (623 words) - 06:18, 5 November 2020
- {{intel title|Pentium G4400T}} |designer=Intel4 KB (610 words) - 16:25, 13 December 2017
- {{intel title|Pentium G4400TE}} |designer=Intel4 KB (606 words) - 16:25, 13 December 2017
- {{intel title|Pentium 4405Y}} |designer=Intel4 KB (581 words) - 17:57, 28 August 2018
- {{intel title|Pentium 4405U}} |designer=Intel4 KB (597 words) - 16:25, 13 December 2017
- {{intel title|Xeon D-1529}} |designer=Intel4 KB (613 words) - 02:20, 1 April 2019
- {{intel title|Xeon D-1539}} |designer=Intel4 KB (596 words) - 02:16, 1 April 2019
- {{intel title|Xeon D-1559}} |designer=Intel4 KB (596 words) - 02:16, 1 April 2019
- | package 4 = PQFP-100 ...y [[AMD]] in [[1991]]. Am386 chips were 100%-compatible with [[Intel]]'s {{intel|80386}}, had better performance, ran cooler, used less power, and introduce8 KB (1,077 words) - 14:50, 2 April 2020
- | designer = Intel | manufacturer = Intel6 KB (626 words) - 19:52, 6 October 2020
- | designer = Intel | manufacturer = Intel6 KB (603 words) - 16:24, 13 December 2017
- | designer = Intel | manufacturer = Intel6 KB (601 words) - 16:24, 13 December 2017
- | designer = Intel | manufacturer = Intel6 KB (603 words) - 16:24, 13 December 2017
- | designer = Intel | manufacturer = Intel6 KB (623 words) - 16:24, 13 December 2017
- | designer = Intel | manufacturer = Intel6 KB (623 words) - 16:24, 13 December 2017
- | designer = Intel | manufacturer = Intel6 KB (627 words) - 16:24, 13 December 2017
- {{intel title|Core m7-6Y75}} |designer=Intel4 KB (613 words) - 17:58, 28 August 2018
- {{intel title|Core m5-6Y54}} |designer=Intel4 KB (613 words) - 17:58, 28 August 2018
- {{intel title|Core m5-6Y57}} |designer=Intel4 KB (613 words) - 17:58, 28 August 2018
- {{intel title|Core m3-6Y30}} |designer=Intel4 KB (613 words) - 17:58, 28 August 2018
- {{intel title|80486}} | title = Intel 804868 KB (953 words) - 08:27, 29 October 2022
- {{intel title|i486DX-20}} | name = Intel i486DX-202 KB (215 words) - 16:13, 13 December 2017
- {{intel title|i486DX-25}} | name = Intel i486DX-253 KB (256 words) - 16:13, 13 December 2017
- {{intel title|i486DX-33}} | name = Intel i486DX-333 KB (321 words) - 02:59, 18 December 2017
- {{intel title|i486DX-50}} | name = Intel i486DX-503 KB (265 words) - 16:13, 13 December 2017
- {{intel title|i486DX2-40}} | name = Intel i486DX2-402 KB (240 words) - 16:13, 13 December 2017
- {{intel title|i486DX2-50}} | name = Intel i486DX2-503 KB (345 words) - 16:13, 13 December 2017
- {{intel title|i486DX2-66}} | name = Intel i486DX2-664 KB (372 words) - 06:28, 15 February 2024
- {{intel title|i486DX4-75}} | name = Intel i486DX4-753 KB (354 words) - 16:13, 13 December 2017
- {{intel title|i486DX4-100}} | name = Intel i486DX4-1004 KB (414 words) - 16:13, 13 December 2017
- {{intel title|i486SL-20}} | name = Intel i486SL-202 KB (234 words) - 16:13, 13 December 2017
- {{intel title|i486SL-25}} | name = Intel i486SL-253 KB (260 words) - 16:14, 13 December 2017
- {{intel title|i486SL-33}} | name = Intel i486SL-333 KB (244 words) - 16:14, 13 December 2017
- {{intel title|i486GX-33}} | name = Intel i486GX-332 KB (214 words) - 16:13, 13 December 2017
- {{intel title|i486SX-16}} | name = Intel i486SX-163 KB (240 words) - 16:14, 13 December 2017
- {{intel title|i486SX-20}} | name = Intel i486SX-203 KB (251 words) - 16:14, 13 December 2017
- {{intel title|i486SX-25}} | name = Intel i486SX-254 KB (332 words) - 16:14, 13 December 2017
- {{intel title|i486SX-33}} | name = Intel i486SX-334 KB (345 words) - 16:14, 13 December 2017
- {{intel title|i486SX2-50}} | name = Intel i486SX2-502 KB (253 words) - 16:14, 13 December 2017
- {{intel title|i486SX2-66}} | name = Intel i486SX2-662 KB (220 words) - 16:14, 13 December 2017
- #REDIRECT [[intel/mcs-4]]25 bytes (3 words) - 18:13, 12 May 2016
- #REDIRECT [[intel/mcs-4]]25 bytes (3 words) - 18:13, 12 May 2016
- #REDIRECT [[intel/mcs-4]]25 bytes (3 words) - 18:13, 12 May 2016
- {{intel title|Core i3-6100U}} |designer=Intel4 KB (616 words) - 16:17, 13 December 2017
- {{intel title|Core i3-6300}} |designer=Intel4 KB (609 words) - 16:18, 13 December 2017
- {{intel title|Core i3-6300T}} |designer=Intel4 KB (618 words) - 16:18, 13 December 2017
- {{intel title|Core i3-6100TE}} |designer=Intel4 KB (612 words) - 16:17, 13 December 2017
- {{intel title|Core i3-6320}} |designer=Intel4 KB (611 words) - 16:18, 13 December 2017
- {{intel title|Core i3-6100}} |designer=Intel4 KB (615 words) - 16:17, 13 December 2017
- {{intel title|Core i3-6100T}} |designer=Intel4 KB (615 words) - 16:17, 13 December 2017
- {{intel title|Core i3-6102E}} |designer=Intel4 KB (613 words) - 16:17, 13 December 2017
- {{intel title|Core i3-6100H}} |designer=Intel4 KB (613 words) - 02:11, 16 January 2019
- {{intel title|Core i3-6100E}} |designer=Intel4 KB (613 words) - 16:17, 13 December 2017
- {{intel title|Core i3-6320T}} |designer=Intel4 KB (609 words) - 16:16, 13 December 2017
- {{intel title|Core i3-6120T}} |designer=Intel4 KB (606 words) - 16:16, 13 December 2017
- {{intel title|Core i3}} | title = Intel Core i325 KB (3,397 words) - 03:12, 3 October 2022
- {{intel title|Sample-Specification (S-Spec)}} ...''), also '''sSpec''' or simply '''Specification Number''', is a string of 4-6 alphanumeric characters that represent an exact IC batch (or set of batch1 KB (216 words) - 01:25, 14 May 2016
- {{intel title|Core i5}} | title = Intel Core i534 KB (4,663 words) - 20:38, 20 February 2023
- | part number 4 = | max memory = 4 GiB2 KB (218 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB2 KB (227 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (270 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (237 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB2 KB (235 words) - 15:18, 13 December 2017
- |max memory=4 GiB '''Am486DX2-80''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1994. This proce1 KB (209 words) - 21:53, 7 February 2024
- | part number 4 = | max memory = 4 GiB3 KB (286 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB2 KB (235 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB2 KB (235 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (254 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB2 KB (235 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB2 KB (237 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (242 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (242 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB2 KB (231 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (235 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (235 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (256 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (256 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (251 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (318 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (289 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (295 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (282 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (280 words) - 15:18, 13 December 2017
- | part number 4 = Am486DX2-66V16BGI | max memory = 4 GiB3 KB (400 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (348 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (301 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (279 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (264 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (337 words) - 15:18, 13 December 2017
- | part number 4 = Am486DX4-100V16BGI | max memory = 4 GiB3 KB (386 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (314 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (288 words) - 08:06, 28 September 2020
- | part number 4 = | max memory = 4 GiB3 KB (277 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (257 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (257 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (342 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (290 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (283 words) - 15:18, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (329 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (367 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (300 words) - 15:19, 13 December 2017
- | part number 4 = | max memory = 4 GiB3 KB (343 words) - 15:19, 13 December 2017
- ...ing 486-based systems. This family solidified AMD position as the official Intel competition. ...Cyrix|Cyrix 5x86}}) - people were more likely to buy a system with "5" vs "4". AMD took this opportunity to utilize their latest technology and release7 KB (1,043 words) - 16:50, 14 June 2020
- | clock multiplier = 4 | max memory = 4 GiB3 KB (324 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (358 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (342 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (337 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (336 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (372 words) - 16:35, 9 July 2018
- | clock multiplier = 4 | max memory = 4 GiB3 KB (303 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (295 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (298 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (289 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (289 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (289 words) - 15:19, 13 December 2017
- | clock multiplier = 4 | max memory = 4 GiB3 KB (289 words) - 15:19, 13 December 2017
- | max memory = 4 GiB {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}3 KB (298 words) - 21:32, 10 April 2021
- | max memory = 4 GiB {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}3 KB (298 words) - 15:19, 13 December 2017
- | max memory = 4 GiB {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}3 KB (298 words) - 20:13, 15 March 2021
- | clock multiplier = 4 | max memory = 4 GiB4 KB (419 words) - 15:19, 13 December 2017
- | developer = Intel | package 4 =9 KB (1,192 words) - 01:35, 29 May 2016
- | designer = Intel | part number 4 =3 KB (288 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (290 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (290 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (260 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (261 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (275 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (274 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (289 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (281 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (252 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (235 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (235 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (235 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (240 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (241 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =2 KB (241 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (270 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (291 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (296 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (278 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (277 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (241 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (241 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (240 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (240 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =2 KB (240 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (279 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (279 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (259 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =2 KB (239 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (263 words) - 15:17, 13 December 2017
- | part number 4 = {{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}}3 KB (339 words) - 15:18, 13 December 2017
- | part number 4 = {{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}}3 KB (339 words) - 15:18, 13 December 2017
- | part number 4 = {{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}}3 KB (309 words) - 15:18, 13 December 2017
- | part number 4 = {{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}}3 KB (309 words) - 15:18, 13 December 2017
- | designer = Intel | part number 4 =3 KB (275 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (273 words) - 15:17, 13 December 2017
- | developer = Intel | package 4 = TQFP-685 KB (602 words) - 18:20, 3 June 2016
- | designer = Intel | part number 4 =3 KB (269 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (255 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (271 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (263 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (255 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (265 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (256 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (258 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (267 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (267 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (267 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (267 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (267 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (267 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (261 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (264 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (277 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (277 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (278 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (278 words) - 15:17, 13 December 2017
- | part number 4 = | package 0 height = 4.58 mm3 KB (280 words) - 04:32, 22 October 2019
- | part number 4 = | package 0 height = 4.58 mm3 KB (281 words) - 15:17, 13 December 2017
- | part number 4 = | bus speed = 4 MHz3 KB (286 words) - 15:17, 13 December 2017
- | part number 4 = | package 0 height = 4.58 mm3 KB (281 words) - 15:17, 13 December 2017
- | part number 4 = | package 0 height = 4.58 mm3 KB (281 words) - 15:17, 13 December 2017
- | part number 4 = | package 0 height = 4.58 mm3 KB (290 words) - 15:17, 13 December 2017
- | part number 4 = | package 0 height = 4.58 mm3 KB (296 words) - 15:17, 13 December 2017
- | part number 4 = | bus speed = 4 MHz3 KB (296 words) - 15:17, 13 December 2017
- | part number 4 = | package 0 height = 4.58 mm3 KB (296 words) - 15:17, 13 December 2017
- | part number 4 = '''S80C186''' is an {{intel|80186}}-based microprocessor manufactured by [[AMD]] in PQFP-80 packages. T3 KB (279 words) - 15:17, 13 December 2017
- | part number 4 = '''S80C186-12''' is an {{intel|80186}}-based microprocessor manufactured by [[AMD]] in PQFP-80 packages. T3 KB (284 words) - 15:17, 13 December 2017
- | part number 4 = | bus speed = 4 MHz3 KB (284 words) - 15:17, 13 December 2017
- | part number 4 = '''S80C186-20''' is an {{intel|80186}}-based microprocessor manufactured by [[AMD]] in PQFP-80 packages. T3 KB (284 words) - 15:17, 13 December 2017
- | part number 4 = '''S80C186-25''' is an {{intel|80186}}-based microprocessor manufactured by [[AMD]] in PQFP-80 packages. T3 KB (284 words) - 15:17, 13 December 2017
- | part number 4 = '''SB80C186''' is an {{intel|80186}}-based microprocessor manufactured by [[AMD]] in TQFP-80 packages. T3 KB (279 words) - 15:17, 13 December 2017
- | part number 4 = '''SB80C186-12''' is an {{intel|80186}}-based microprocessor manufactured by [[AMD]] in TQFP-80 packages. T3 KB (284 words) - 15:17, 13 December 2017
- | part number 4 = | bus speed = 4 MHz3 KB (284 words) - 15:17, 13 December 2017
- | part number 4 = '''SB80C186-20''' is an {{intel|80186}}-based microprocessor manufactured by [[AMD]] in TQFP-80 packages. T3 KB (284 words) - 15:17, 13 December 2017
- | part number 4 = '''SB80C186-25''' is an {{intel|80186}}-based microprocessor manufactured by [[AMD]] in TQFP-80 packages. T3 KB (284 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (269 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (275 words) - 15:16, 13 December 2017
- | designer = Intel | part number 4 =3 KB (269 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (275 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (260 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (260 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (260 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (260 words) - 15:17, 13 December 2017
- | designer = Intel | part number 4 =3 KB (250 words) - 15:17, 13 December 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (319 words) - 16:55, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (319 words) - 16:56, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (319 words) - 16:56, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (319 words) - 16:56, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (330 words) - 16:54, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (330 words) - 16:55, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (319 words) - 16:55, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (319 words) - 16:55, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (319 words) - 16:56, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (319 words) - 16:56, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (329 words) - 16:55, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (329 words) - 16:56, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (330 words) - 16:54, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (330 words) - 16:55, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (387 words) - 17:00, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (387 words) - 17:01, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (387 words) - 17:01, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (387 words) - 17:01, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (402 words) - 16:59, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (402 words) - 17:00, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (387 words) - 17:00, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (387 words) - 17:00, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (387 words) - 17:01, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (387 words) - 17:01, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (397 words) - 17:00, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (397 words) - 17:01, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (400 words) - 16:59, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (400 words) - 17:00, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (351 words) - 16:53, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (351 words) - 16:53, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (351 words) - 16:54, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (351 words) - 16:54, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (366 words) - 16:52, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (366 words) - 16:52, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (351 words) - 16:53, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (351 words) - 16:53, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (351 words) - 16:54, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (351 words) - 16:54, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (366 words) - 16:52, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (366 words) - 16:52, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (362 words) - 16:53, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (362 words) - 16:53, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (334 words) - 16:57, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (334 words) - 16:58, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (334 words) - 16:58, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (333 words) - 16:59, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (344 words) - 16:57, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (344 words) - 16:58, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (344 words) - 16:58, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (343 words) - 16:59, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (334 words) - 16:57, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (334 words) - 16:57, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (334 words) - 16:58, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (333 words) - 16:59, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (345 words) - 16:57, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (345 words) - 16:57, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (345 words) - 16:58, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}3 KB (344 words) - 16:59, 30 June 2017
- | part number 4 = ...perating at 25 MHz and incorporates a USB peripheral controller along with 4 dedicated DMA channels for it.4 KB (364 words) - 16:51, 30 June 2017
- | part number 4 = ...perating at 40 MHz and incorporates a USB peripheral controller along with 4 dedicated DMA channels for it.3 KB (364 words) - 16:51, 30 June 2017
- | part number 4 = ...perating at 50 MHz and incorporates a USB peripheral controller along with 4 dedicated DMA channels for it.4 KB (364 words) - 16:52, 30 June 2017
- | part number 4 = ...perating at 25 MHz and incorporates a USB peripheral controller along with 4 dedicated DMA channels for it. This model supports industrial temperate ran4 KB (374 words) - 16:51, 30 June 2017
- | part number 4 = ...perating at 40 MHz and incorporates a USB peripheral controller along with 4 dedicated DMA channels for it. This model supports industrial temperate ran4 KB (374 words) - 16:52, 30 June 2017
- | part number 4 = ...MHz and incorporates a number of High-level Data Link Controls along with 4 dedicated DMA channels for it.3 KB (367 words) - 16:50, 30 June 2017
- | part number 4 = ...MHz and incorporates a number of High-level Data Link Controls along with 4 dedicated DMA channels for it.3 KB (367 words) - 16:51, 30 June 2017
- | part number 4 = ...MHz and incorporates a number of High-level Data Link Controls along with 4 dedicated DMA channels for it.3 KB (367 words) - 16:51, 30 June 2017
- | part number 4 = ...MHz and incorporates a number of High-level Data Link Controls along with 4 dedicated DMA channels for it. This model has industrial temperature range4 KB (378 words) - 16:50, 30 June 2017
- | part number 4 = ...MHz and incorporates a number of High-level Data Link Controls along with 4 dedicated DMA channels for it. This model has industrial temperature range4 KB (378 words) - 16:51, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (390 words) - 16:49, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (390 words) - 16:50, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (390 words) - 16:50, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (402 words) - 16:50, 30 June 2017
- | part number 4 = {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}}4 KB (402 words) - 16:50, 30 June 2017
- | developer = Intel | package 4 = CLCC-405 KB (616 words) - 14:24, 1 May 2019
- {{intel title|Xeon E7}} | title = Intel Xeon E74 KB (482 words) - 05:08, 18 February 2020
- {{intel title|Xeon E7-4807}} | designer = Intel4 KB (473 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-2803}} | designer = Intel4 KB (475 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-8830}} | designer = Intel4 KB (520 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-8837}} | designer = Intel4 KB (528 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-4820}} | designer = Intel4 KB (520 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-4830}} | designer = Intel4 KB (522 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-2820}} | designer = Intel4 KB (518 words) - 05:10, 18 February 2020
- {{intel title|Xeon E7-2830}} | designer = Intel4 KB (518 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-8850}} | designer = Intel4 KB (539 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-8870}} | designer = Intel4 KB (539 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-4850}} | designer = Intel4 KB (539 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-8867L}} | designer = Intel4 KB (542 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-8860}} | designer = Intel4 KB (539 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-4860}} | designer = Intel4 KB (539 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-2860}} | designer = Intel4 KB (537 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-4870}} | designer = Intel4 KB (541 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-2850}} | designer = Intel4 KB (537 words) - 16:28, 13 December 2017
- {{intel title|Xeon E7-2870}} | designer = Intel4 KB (537 words) - 16:28, 13 December 2017
- * March 22: Intel phased out their {{intel|Tick-Tock}} model in favor of a {{intel|Process-Architecture-Optimization}} model. * April 4: [[Brocade]] acquires [[Ruckus Wireless]] for $1.2 Billion5 KB (593 words) - 01:28, 5 August 2018
- ...chips ran over three times the clock rate as [[Motorola]]'s/[[IBM]]'s or [[Intel]]'s (albeit not as fast in direct performance). Exponential experienced a f ...erably faster than the fastest chips on the market at the time - Intel's {{intel|Pentium II|Klamath}} which ran as high as 233 MHz.8 KB (1,228 words) - 20:49, 2 June 2019
- | max memory = 4 GiB ...croarchitectures/k6|K6 microarchitecture}} and was marketed as a 166 MHz {{intel|Pentium II}}-equivalent processor. The PR2 rating was actually superfluous3 KB (333 words) - 16:09, 13 December 2017
- | max memory = 4 GiB ...croarchitectures/k6|K6 microarchitecture}} and was marketed as a 200 MHz {{intel|Pentium II}}-equivalent processor. The PR2 rating was actually superfluous3 KB (333 words) - 16:09, 13 December 2017
- ...gained as much popularity as {{x86|SSE}} did, a later implementation by [[Intel]]. ...K6}} chips which was the last socket specification AMD retained rights to. Intel ditched that socket in favor of [[Slot 1]] partially in an attempt to lock13 KB (1,969 words) - 18:07, 2 October 2019
- {{intel title|Coffee Lake|arch}} |designer=Intel30 KB (4,192 words) - 13:48, 10 December 2023
- {{intel title|Tick-Tock}} ..."Tick" and "Tock". Intel no longer uses this model, instead they use the {{intel|Process-Architecture-Optimization}} (PAO).3 KB (317 words) - 22:13, 30 April 2017