From WikiChip
Zen 2 - Microarchitectures - AMD
< amd‎ | microarchitectures(Redirected from amd/zen 2)

Edit Values
Zen 2 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerGlobalFoundries, TSMC
Introduction2019
Process14 nm, 7 nm, 12 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages19
Decode4-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, RDRND, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SHA, CLZERO
Cores
Core NamesRome
Succession

Zen 2 is AMD's successor to Zen+, a 7 nm process microarchitecture for mainstream mobile, desktops, workstations, and servers. Zen 2 will eventually be replaced by Zen 3.

For performance desktop and mobile computing, Zen is branded as Ryzen 3, Ryzen 5, Ryzen 7 and Ryzen Threadripper processors. For servers, Zen is branded as EPYC.


Under construction icon-blue.svg This article is a work in progress!


History

Zen 2

Zen 2 is set to succeed Zen in 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later Zen 3. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize 7 nm process. Initial details of Zen 2 and Rome were unveiled during AMD's Next Horizon event on November 6 2018.

Codenames

Zen 2 on the roadmap
Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core C/T Target
Rome Up to 64/128 High-end server multiprocessors
Castle Peak Up to 64/128? workstation & enthusiasts market processors
Matisse Up to 16/32 Mainstream to high-end desktops & enthusiasts market processors
Renoir Up to 4/8? Mainstream APUs with Navi GPUs
River Hawk Up to 2/4 Low-power/Cost-sensitive embedded processors with Navi GPU

Process technology

Zen 2 is fabricated on TSMC's 7 nm process. Some components of the chips (e.g., I/O die) are fabricated on GlobalFoundries 12 nm process.

Compiler support

Compiler Arch-Specific Arch-Favorable
GCC -march=znver2 -mtune=znver2
LLVM -march=znver2 -mtune=znver2
  • Note: Initial support in GCC 9 and LLVM 9.

Architecture

Zen 2 inherits most of the design from Zen+ but improves the instruction stream bandwidth and floating-point throughput performance.


Under construction icon-blue.svg This article is a work in progress!


Key changes from Zen+

  • 7 nm process (from 12 nm)
  • Core
    • Higher IPC (AMD self-reported up to 15% IPC)
    • Front-end
      • Improved branch prediction unit
        • Improved prefetcher
      • Improved µOP cache tags
      • Improved µOP cache
        • Larger µOP cache (4096 entries, up from 2048)
      • Increased dispatch bandwidth
    • Back-end
      • Increased retire bandwidth (??-wide, up from 8-wide)
      • FPU
        • 2x wider datapath (256-bit, up from 128-bit)
        • 2x wider EUs (256-bit FMAs, up from 128-bit FMAs)
        • 2x wider LSU (2x256-bit L/S, up from 128-bit)
        • Improved mul latency (3 cycles, down from 4)
      • Integer
        • Increased number of registers (180, up from 168)
        • Additional AGU (3, up from 2)
        • Larger scheduler (4x16 ALU + 1x28 AGU, up from 4x14 ALU + 2x14 AGU
        • Larger Reorder Buffer (224, up from 192)
    • Memory subsystem
      • 0.5x L1 instruction cache (32 KiB, down from 64 KiB)
      • 8-way associativity (from 4-way)
      • 1.33 larger L2 DTLB (2048-entry, up from 1536)
      • 48 entry store queue (was 44)
  • CCX
    • 2x L3 cache slice (16 MiB, up from 8 MiB)
    • Increased L3 latency (~40 cycles, up from ~35 cycles)
  • Security
    • In-silicon Spectre enhancements
    • Increase number of keys/VMs supported
  • I/O
    • PCIe 4.0 (from 3.0)
    • Infinity Fabric 2
      • 2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s)
    • Decoupling of MemClk from FClk, allowing 2:1 ratio in addition to 1:1
    • DDR4-3200 support, up from DDR4-2933

This list is incomplete; you can help by expanding it.

New instructions

Zen 2 introduced a number of new x86 instructions:

  • CLWB - Write back modified cache line and may retain line in cache hierarchy
  • WBNOINVD - Write back and do not flush internal caches, initiate same of external caches
  • RDPID - Read Processor ID

Block Diagram

Individual Core

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

New text document.svg This section is empty; you can help add the missing info by editing this page.

Core

Zen 2 largely builds on Zen. Most of the fine details have not been revealed by AMD yet.


Under construction icon-blue.svg This article is a work in progress!


Front End

In order to feed the backend, which has been widened to support 256-bit operation, the front-end throughput was improved. AMD reported that the branch prediction unit has been reworked. This includes improvements to the prefetcher and various undisclosed optimizations to the instruction cache. The µOP cache was also tweaked including changes to the µOP cache tags and the µOP cache itself which has been enlarged to improve the instruction stream throughput.

Execution Engine

AMD stated that both the dispatch bandwidth and the retire bandwidth has been increased.

Floating Point

The floating-point unit underwent major modifications in Zen 2. In Zen, AVX2 256 bit single and double precision vector floating-point data types were supported through the use of two 128 bit micro-ops per instruction. Likewise, the floating-point load and store operations were 128 bits wide. In Zen 2, the datapath and the execution units were widened to 256 bits, doubling the vector throughput of the core.

With two 256-bit FMAs, Zen 2 is capable of 16 FLOPs/cycle.

Rome

Rome is codename for AMD's server chip based on the Zen 2 core. Like prior generation (Naples), Rome utilizes a chiplet multi-chip package design. Each chip comprises of nine dies - one centralized I/O die and eight compute dies. The compute dies are fabricated on TSMC's 7 nm process in order to take advantage of the lower power and higher density. On the other hand, the I/O makes use of GlobalFoundries mature 14 nm process.

The centralized I/O die incorporates eight Infinity Fabric links, 128 PCIe Gen 4 lanes, and eight DDR4 memory channels. The full capabilities of the I/O have not been disclosed yet. Attached to the I/O die are eight compute dies - each with eight Zen 2 core - for a total of 64 cores and 128 threads per chip.

All Zen 2 chips

 List of Zen 2 Processors
ModelFamilyPriceLaunchedCoresThreadsL3$BaseTurboTDPMem Type
3600Ryzen 5$ 199.00
€ 179.10
£ 161.19
¥ 20,562.67
7 July 201961232 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
65 W
65,000 mW
0.0872 hp
0.065 kW
DDR4-3200
3600XRyzen 5$ 249.00
€ 224.10
£ 201.69
¥ 25,729.17
7 July 201961232 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
4.4 GHz
4,400 MHz
4,400,000 kHz
95 W
95,000 mW
0.127 hp
0.095 kW
DDR4-3200
3700XRyzen 7$ 329.00
€ 296.10
£ 266.49
¥ 33,995.57
7 July 201981632 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
4.4 GHz
4,400 MHz
4,400,000 kHz
65 W
65,000 mW
0.0872 hp
0.065 kW
DDR4-3200
3800XRyzen 7$ 399.00
€ 359.10
£ 323.19
¥ 41,228.67
7 July 201981632 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.9 GHz
3,900 MHz
3,900,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
105 W
105,000 mW
0.141 hp
0.105 kW
DDR4-3200
3900XRyzen 9$ 499.00
€ 449.10
£ 404.19
¥ 51,561.67
7 July 2019122464 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
4.6 GHz
4,600 MHz
4,600,000 kHz
105 W
105,000 mW
0.141 hp
0.105 kW
DDR4-3200
3950XRyzen 9$ 749.00
€ 674.10
£ 606.69
¥ 77,394.17
September 2019163264 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.5 GHz
3,500 MHz
3,500,000 kHz
4.7 GHz
4,700 MHz
4,700,000 kHz
105 W
105,000 mW
0.141 hp
0.105 kW
DDR4-3200
Count: 6

Bibliography

  • AMD 'Tech Day', February 22, 2017
  • AMD 2017 Financial Analyst Day, May 16, 2017
  • AMD GCC 9 znver2 enablement patch
  • AMD 'Next Horizon', November 6, 2018
  • AMD. Lisa Su Keynote. May 26, 2019
  • AMD 'Next Horizon Gaming' event at E3, June 10, 2019

See Also

codenameZen 2 +
designerAMD +
first launched2019 +
full page nameamd/microarchitectures/zen 2 +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerGlobalFoundries + and TSMC +
microarchitecture typeCPU +
nameZen 2 +
pipeline stages19 +
process14 nm (0.014 μm, 1.4e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +