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Ryzen 7 4800HS
General Info
Designer	AMD
Manufacturer	TSMC
Model Number	4800HS
Market	Mobile
Introduction	March 16, 2020 (announced) March 16, 2020 (launched)
Shop	Amazon
General Specs
Family	Ryzen 7
Series	4000
Locked	Yes
Frequency	2,900 MHz
Turbo Frequency	4,200 MHz
Clock multiplier	29
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen 2
Core Name	Renoir
Core Family	23
Core Model	96
Core Stepping	A1
Process	7 nm
Transistors	9,800,000,000
Technology	CMOS
Die	156 mm²
Word Size	64 bit
Cores	8
Threads	16
Max Memory	64 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	35 W
Tcase	0 °C – 105 °C
Packaging
Package	BGA-1140 (FC-OBGA)
Dimension	35 mm × 25 mm × 1.38 mm
Pitch	0.65 mm
Contacts	1140

Ryzen 7 4800HS is a 64-bit octa-core high-end performance x86 mobile microprocessor introduced by AMD in early 2020. Fabricated on TSMC's 7-nanometer process and based on AMD's Zen 2 microarchitecture, the 4800HS operates at a base frequency of 2.9 GHz with a TDP of 35 W and a boost frequency of up to 4.2 GHz. This APU supports up to 64 GiB of DDR4-3200 or up to 32 GiB of quad-channel LPDDR4x-4266 memory. The 4800HS integrates Radeon Vega 7 graphics operating at up to 1.6 GHz.

This processor is identical to the 4800H except for its lower TDP.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative write-back L2$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     8x512 KiB 8-way set associative write-back L3$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     2x4 MiB 16-way set associative write-back

Memory controller

This SoC features two memory controllers, each supporting DDR4 or LPDDR4x. This chip supports up to 64 GiB of dual-channel DDR4 memory with data rates of up to 3200 MT/s (51.2 GB/s) or up to 32 GiB of quad-channel LPDDR4x with data rates of up to 4266 MT/s (68.27 GB/s).

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-3200, LPDDR4x-4266 Max Mem 64 GiB Controllers 2 Channels 4 Max Bandwidth 68.27 GB/s 63.581 GiB/s 65,107.346 MiB/s 68,270 MB/s 0.0621 TiB/s 0.0683 TB/s Bandwidth Single 17.07 GB/s Double 34.13 GB/s Quad 68.27 GB/s

Expansions

This processor has 16 PCIe lanes, 1x8 designated for a discrete GPU, 1x4 additional lanes for storage (e.g., NVMe), and 1x4 additional lanes reserved for additional peripherals (e.g., WiFi or LTE).

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 16 Configuration: 1x8+1x4+1x4, 2x4+1x4+1x4

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Radeon Vega 7 Designer AMD Execution Units 7 Max Displays 4 Unified Shaders 448 Burst Frequency 1,600 MHz 1.6 GHz 1,600,000 KHz Output DP, HDMI

[Edit] Zen 2 with Radeon Vega Hardware Accelerated Video Capabilities
Codec	Encode	Decode
VP9 8bpc/10bpc		1080p240 4K 60 FPS
MPEG-2 (H.262) 8b	1080p240 4K 60 FPS	1080p480 4K 120 FPS
HEVC (H.265) 8bpc/10bpc	1080p240 4K 60 FPS	1080p240 4K 60 FPS

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute SMT Simultaneous Multithreading AMD-Vi AMD-Vi (I/O MMU virtualization) AMD-V AMD Virtualization SenseMI SenseMI Technology

Die

Main article: Zen 2 § Die

Renoir microprocessors are fabricated on TSMC's 7-nanometer process. This SoC integrates 9.8 billion transistors on a single 156 mm² monolithic die which includes both the Zen 2 CPU cores along with the Vega GPU and various other additional components.

• 7-nanometer process (N7)
• 9,800,000,000 transistors
• 156 mm² die size