|package 0 pitch=2.54 mm |package 1 pitch=2.3 mm

|Contacted Gate Pitch |Interconnect Pitch

|Contacted Gate Pitch |Interconnect Pitch

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

...and early 1990s. A '''"0.8 µm process"''' refers to a process which has a gate length of 0.8 µm. This process was later replaced by [[650 nm]], [[600 nm] |Gate Length

...a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's what the leading fou ...nsity doubling, the [[contacted poly pitch]] (CPP) and the [[minimum metal pitch]] (MMP) need to scale by roughly 0.7x each node. In other words, a scaling

| process 1 gate len = 30 nm | process 1 gate len Δ =  

...on of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and has been replaced by the [[ | process 1 fin pitch = 42 nm

...Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-volume manufacturing process. |Contacted Gate Pitch

...is the first high-volume manufacturing process to introduce High-k + metal gate transistors. | Gate Pitch || 180 nm

...[[FinFET]] transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.0706 µm² and 0.0499 µm² for high perfo | Fin Pitch || 60 nm || 42 || 0.70x

|Contacted Gate Pitch |Interconnect Pitch

...on of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 22 nm process began ...ransistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new pro

...on of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with [[10 nm lithography process|10 | process 1 fin pitch = 48 nm

...on of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 20 nm process began | process 1 gate len =  

...hancements. Ivy Bridge became Intel's first microarchitecture to use [[tri-gate transistor]]s for their commercial products. ...eneration of [[FinFET]]. This correlates to 8 nm Fin width and a 60 nm Fin pitch (shown below). SRAM cell is at 0.1080 µm² and 0.092 µm² for high perfor

...oyed a roughly 0.7x scaling compared to the [[45 nm process]] for the gate pitch and metal 1 interconnect. ! !! Nehalem !! Westmere !! Δ !! rowspan="7" | [[File:intel 32nm gate.png|250px]]

...is the first high-volume manufacturing process to introduce High-k + metal gate transistors. ! !! Core !! Nehalem !! Δ !! rowspan="7" | [[File:intel 45nm gate.png|250px]]

| Contacted Gate Pitch​ || 550 nm || 500 nm || 0.91x | Interconnect Pitch || 880 nm || 640 nm || 0.73x

| Fin Pitch ||  42 nm ||  34 nm || 0.81x | Gate Pitch ||  70 nm ||  54 nm || 0.77x

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

...a certain size and its technology, as opposed to [[gate length]] or [[half pitch]]. The 10 nm node is currently being introduced and is set to get replaced ...ypically have a [[gate pitch]] in range of 50-60s nm and a [[minimum metal pitch]] in the range of 30-40s nm. Due to the small feature sizes, for the [[crit

...a fourth-generation [[FinFET]], fifth-generation [[HKMG]], gate-last, dual gate oxide process. ...ate pitch has been further scaled down to 57 nm, however, the interconnect pitch halted at the 40 nm point in order to keep patterning at the [[SADP]] point

[[File:N5 mx rc and vx rc.png|right|thumb|200px|Tightest pitch Mx RC and Vx RC on 5nm was kept at similar levels to N7.]] ...r to reduce cell spacing. Additionally, TSMC added the ability to drop the gate contact over the active region (COAG). Although originally experimented wit

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Gate Oxide |Contacted Gate Pitch

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Gate Length |Interconnect Pitch (M1P)

|Gate Length |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch

|Contacted Gate Pitch |Interconnect Pitch

|Contacted Gate Pitch |Interconnect Pitch (M1P)

...m process was a standard CMOS process. Featuring a smaller transistor gate pitch, the process shared similar metal layer sizes to the [[0.35 µm]] (this is |Contacted Gate Pitch

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

|Contacted Gate Pitch |Interconnect Pitch (M1P)

...nsistor geometry, the "14nm++" actually uses a more relaxed contacted poly pitch of 84 nm (from previously 70nm). There is no real density change despite th | Gate Pitch || 70 nm || 84 nm || 1.20x

| process 1 fin pitch =   | process 1 fin pitch Δ =  

...iance in SRAM-to-logic ratio between popular chips. Furthermore, the metal pitch does not play a role in limiting SRAM as it does with other standard cells. ...has a poly pitch of 54 nm and cells on Intel's 10 nm use a single [[dummy gate]]. For 0.6 NAND2 + 0.4 SFF, Intel's 10nm has a density of 100.76 MTr/mm² a

...n]] or improve the device performance through the relaxation of the [[gate pitch]]. An example of recent nodelets include [[12 nm]], [[11 nm]], and [[8 nm]]

...d]] loss due to misalignment and partial overlaps of the contacts over the gate. ...a need to be able to length much closer to the gate and even on top of the gate. In addition to the lack of space, problems with landing the contacts are e

...ocess nodes]] continues to shrink, classical scaling vectors (e.g., [[gate pitch]]) becomes increasingly challenging. There are multiple reasons for this in ...proving the yield by preventing yield loss due to the contact shorting the gate.

...or process flow technique that eliminates the need for an additional dummy gate padding at the cell boundaries. SDB is [[scaling booster|used to enable agg ...[poly gate]] [[gate length|length]]. In practice, there is no actual dummy gate. Instead, just the trench isolation remains.