Latest revision as of 14:27, 9 June 2023

Zen (family 17h) is the microarchitecture developed by AMD as a successor to both Excavator and Puma. Zen is an entirely new design, built from the ground up for optimal balance of performance and power capable of covering the entire computing spectrum from fanless notebooks to high-performance desktop computers. Zen was officially launched on March 2, 2017. Zen was replaced by Zen+ in 2018.

For performance desktop and mobile computing, Zen is branded as Athlon, Ryzen 3, Ryzen 5, Ryzen 7, Ryzen 9 and Ryzen Threadripper processors. For servers, Zen is branded as EPYC.

Etymology[edit]

Zen was picked by Michael Clark, AMD's senior fellow and lead architect. Zen was picked to represent the balance needed between the various competing aspects of a microprocessor - transistor allocation/die size, clock/frequency restriction, power limitations, and new instructions to implement.

Codenames[edit]

Brands[edit]

Ryzen brand logo

AMD Zen-based processor brands
Logo	Family	General Description	Differentiating Features
			Cores	Unlocked	AVX2	SMT	XFR	IGP	ECC	MP
Mainstream
	Ryzen 3	Entry level Performance	Quad	✔	✔	✘	✔	✔/✘	✔	✘
	Ryzen 5	Mid-range Performance	Quad	✔	✔	✔	✔	✔/✘	✔	✘
			Hexa	✔	✔	✔	✔	✘	✔	✘
	Ryzen 7	High-end Performance	Octa	✔	✔	✔	✔	✘	✔	✘
	Ryzen 9	High-end Performance	12-16	✔	✔	✔	✔	✘	✔	✘
Enthusiasts / Workstations
	Ryzen Threadripper	Enthusiasts	8-16	✔	✔	✔	✔	✘	✔	✘
Servers
	EPYC	High-performance Server Processor	8-32	✘	✔	✔		✘	✔	✔
Embedded / Edge
	EPYC Embedded	Embedded / Edge Server Processor	8-16	✘	✔	✔/✘		✘	✔	✘
	Ryzen Embedded	Embedded APUs	4		✔	✔/✘		✔	✔	✘

• Note: While a model has an unlocked multiplier, not all chipsets support overclocking. (see §Sockets)
• Note: 'X' models will enjoy "Full XFR" providing an additional +100 MHz (200 for 1500X and Threadripper line) when sufficient thermo/electric requirements are met. Non-X models are limited to just +50 MHz.

Identification[edit]

Release Dates[edit]

First 16-core HEDT market CPU

The first set of processors, as part of the Ryzen 7 family were introduced at an AMD event on February 22, 2017 before the Game Developer Conference (GDC). However initial models don't get shipped until March 2. Ryzen 5 hexa-core and quad-core variants were released on April 11, 2017. Server processors are set to be released in by the end of Q2, 2017. In October 2017, AMD launched mobile Zen-based processors featuring Vega GPUs.

Process Technology[edit]

See also: 14 nm process

Zen is manufactured on Global Foundries' 14 nm process Low Power Plus (14LPP). AMD's previous microarchitectures were based on 32 and 28 nanometer processes. The jump to 14 nm was part of AMD's attempt to remain competitive against Intel (Both Skylake and Kaby Lake are also manufactured on 14 nm). The move to 14 nm will bring along related benefits of a smaller node such as reduced heat, reduced power consumption, and higher density for identical designs.

Compatibility[edit]

Linux added initial support for Zen starting with Linux Kernel 4.10. Microsoft will only support Windows 10 for Zen.

Compiler support[edit]

With the release of Ryzen, AMD introduced their own compiler: AMD Optimizing C/C++ Compiler (AOCC). AOCC is an LLVM port especially modified to generate optimized x86 code for the Zen microarchitecture.

CPUID[edit]

See also: AMD CPUIDs

Architecture[edit]

AMD Zen is an entirely new design from the ground up which introduces considerable amount of improvements and design changes over Excavator. Mainstream Zen-based microprocessors utilize AMD's Socket AM4 unified platform along with the Promontory chipset.

Key changes from Excavator[edit]

• Zen was designed to succeed both Excavator (High-performance) and Puma (Low-power) covering the entire range in one architecture
  • Cover the entire spectrum from fanless notebooks to high-performance desktops
  • More aggressive clock gating with multi-level regions
  • Power focus from design, employs low-power design methodologies
    • >15% switching capacitance (C_AC) improvement
• Utilizes 14 nm process (from 28 nm)
• 52% improvement in IPC per core for a single-thread (AMD Claim)
  • From Piledriver to Zen
  • Based on the industry-standardized SPECint_base2006 score compiled with GCC 4.6 -O2 at a fixed 3.4GHz
• Up to 3.7× performance/watt improvment
• Return to conventional high-performance x86 design
  • Traditional design for cores without shared blocks (e.g. shared SIMD units)
  • Large beefier core design
• Core engine
  • Simultaneous Multithreading (SMT) support, 2 threads/core (see § Simultaneous MultiThreading for details)
  • Branch Predictor
    • Improved branch mispredictions
      • Better branch predicitons with 2 branches per BTB entry
      • Lower miss latency penalty
    • BP is now decoupled from fetch stage
  • Large μop cache (2K instructions)
  • Wider μop dispatch (6, up from 4)
  • Larger instruction scheduler
    • Integer (84, up from 48)
    • Floating Point (96, up from 60)
  • Larger retire throughput (8, up from 4)
  • Larger Retire Queue (192, up from 128)
    • duplicated for each thread
  • Larger Load Queue (72, up from 44)
  • Larger Store Queue (44, up from 32)
    • duplicated for each thread
  • Quad-issue FPU (up from 3-issue)
  • Faster Load to FPU (down to 7, from 9 cycles)
• Cache system
  • L1
    • 64 KiB (double from previous capacity of 32 KiB)
    • Write-back L1 cache eviction policy (From write-through)
    • 2× the bandwidth
  • L2
    • 2× the bandwidth
    • Faster L2 cache
  • Faster L3 cache
  • Better L1$ and L2$ data prefetcher
  • 5× L3 bandwidth
  • Move elimination block added
  • Page Table Entry (PTE) Coalescing

New instructions[edit]

Zen introduced a number of new x86 instructions:

• ADX - Multi-Precision Add-Carry Instruction extension
• RDSEED - Hardware-based RNG
• SMAP - Supervisor Mode Access Prevention
• SHA - SHA extensions
• CLFLUSHOPT - Flush Cache Line
• XSAVE - Privileged Save/Restore
• CLZERO - Zero-out Cache Line (AMD exclusive)

While not new, Zen also supports AVX, AVX2, FMA3, BMI1, BMI2, AES, RdRand, SMEP. Note that with Zen, AMD dropped support for XOP, TBM, and LWP.

Note: WikiChip's testing shows FMA4 still works despite not being officially supported and not even reported by CPUID. This has also been confirmed by Agner here. Those tests were not exhaustive. Never use them in production.

Block Diagram[edit]

Client Configuration[edit]

Entire SoC Overview[edit]

Individual Core[edit]

Single/Multi-chip Packages[edit]

Single-die[edit]

Single-die as used in Summit Ridge:

2-die MCP[edit]

2-die MCP used for Threadripper:

4-die MCP[edit]

4-die MCP used for EPYC:

4-die CCX configs[edit]

32-core configuration:

24-core configuration:

16-core configuration:

8-core configuration:

Memory Hierarchy[edit]

• Cache
  • L0 µOP cache:
    • 2,048 µOPs, 8-way set associative
      • 32-sets, 8-µOP line size
    • Parity protected
  • L1I Cache:
    • 64 KiB 4-way set associative
      • 256-sets, 64 B line size
      • Shared by the two threads, per core
    • Parity protected
  • L1D Cache:
    • 32 KiB 8-way set associative
      • 64-sets, 64 B line size
      • Write-back policy
    • 4-5 cycles latency for Int
    • 7-8 cycles latency for FP
    • SEC-DED ECC
  • L2 Cache:
    • 512 KiB 8-way set associative
    • 1,024-sets, 64 B line size
    • Write-back policy
    • Inclusive of L1
    • Latency:
      • 17 cycles latency (ONLY Summit Ridge)
      • 12 cycles latency (All others)
    • DEC-TED ECC
  • L3 Cache:
    • Victim cache
    • Summit Ridge, Naples: 8 MiB/CCX, shared across all cores.
    • Raven Ridge: 4 MiB/CCX, shared across all cores.
    • 16-way set associative
      • 8,192-sets, 64 B line size
    • 40 cycles latency
    • DEC-TED ECC
  • System DRAM:
    • 2 channels per die
    • Summit Ridge: up to PC4-21300U (DDR4-2666 UDIMM), ECC supported
    • Raven Ridge: up to PC4-23466U (DDR4-2933 UDIMM), ECC supported by PRO models
    • Naples: up to PC4-21300L (DDR4-2666 RDIMM/LRDIMM), ECC supported
    • ECC: x4 DRAM device failure correction (Chipkill), x8 SEC-DED ECC, Patrol and Demand scrubbing, Data poisoning

Zen TLB consists of dedicated level one TLB for instruction cache and another one for data cache.

• TLBs
  • ITLB
    • 8 entry L0 TLB, all page sizes
    • 64 entry L1 TLB, all page sizes
    • 512 entry L2 TLB, no 1G pages
    • Parity protected
  • DTLB
    • 64 entry L1 TLB, all page sizes
    • 1,532-entry L2 TLB, no 1G pages
    • Parity protected

Core[edit]

Pipeline[edit]

Zen presents a major design departure from the previous couple of microarchitectures. In the pursuit of remaining competitive against Intel, AMD went with a similar approach to Intel's: large beefier core with SoC design that can scale from extremely low TDP (fanless devices) to supercomputers utilizing dozens of cores. As such, Zen is aimed at replacing both Excavator (AMD's previous performance microarchitecture) and Puma (AMD's previous ultra-low power arch). In addition to covering the entire computing spectrum through power efficiency and core scalability, another major design goal was 40% uplift in single-thread performance (i.e. 40% IPC increase) from Excavator. The large increase in performance is the result of major redesigns in all four areas of the core (the front end, the execution engine, and the memory subsystem) as well as Zen's new SoC CCX (CPU Complex) modular design. The core itself is wider and all around bigger (roughly every component had its capacity substantially increased). The improvement in power efficiency is the result of the 14 nm process used as well as many low-power design methodologies that were utilized early on in the design process (Excavator has been manufactured on GF's 28 nm process). AMD introduced various components (such as their new prediction flow and forwarding mechanisms) that eliminate the need for operations to go through the high power ALUs and decoders, increasing the overall power efficiency and throughput.

Broad Overview[edit]

While Zen is an entirely new design, AMD continued to maintain their traditional design philosophy which shows throughout their design choice such as a split scheduler and split FP and int&memory execution units. At a very broad view, Zen shares many similarities with its predecessor but introduces new elements and major changes. Each core is composed of a front end (in-order area) that fetches instructions, decodes them, generates µOPs and fused µOPs, and sends them to the Execution Engine (out-of-order section). Instructions are either fetched from the L1I$ or come from the µOPs cache (on subsequent fetches) eliminating the decoding stage altogether. Zen decodes 4 instructions/cycle into the µOP Queue. The µOP Queue dispatches separate µOPs to the Integer side and the FP side (dispatching to both at the same time when possible).

The biggest departure from previous generation is Zen's return to traditional core partitioning - every core is an independent core with its own floating-point/SIMD units and a L2 cache. Previously, those units were shared between two cores; they are now once again completely private.

Unlike many of Intel's recent microarchitectures (such as Skylake and Kaby Lake) which make use of a unified scheduler, AMD continue to use a split pipeline design. µOP are decoupled at the µOP Queue and are sent through the two distinct pipelines to either the Integer side or the FP side. The two sections are completely separate, each featuring separate schedulers, queues, and execution units. The Integer side splits up the µOPs via a set of individual schedulers that feed the various ALU units. On the floating point side, there is a different scheduler to handle the 128-bit FP operations. Zen support all modern x86 extensions including AVX/AVX2, BMI1/BMI2, and AES. Zen also supports SHA, secure hash implementation instructions that are currently only found in Intel's ultra-low power microarchitectures (e.g. Goldmont) but not in their mainstream processors.

From the memory subsystem point of view, data is fed into the execution units from the L1D$ via the load and store queue (both of which were almost doubled in capacity) via the two Address Generation Units (AGUs) at the rate of 2 loads and 1 store per cycle. Each core also has a 512 KiB level 2 cache. L2 feeds both the the level 1 data and level 1 instruction caches at 32B per cycle (32B can be sent in either direction (bidirectional bus) each cycle). L2 is connected to the L3 cache which is shared across all cores. As with the L1 to L2 transfers, the L2 also transfers data to the L3 and vice versa at 32B per cycle (32B in either direction each cycle).

Front End[edit]

The Front End of the Zen core deals with the in-order operations such as instruction fetch and instruction decode. The instruction fetch is composed of two paths: a traditional decode path where instructions come from the instruction cache and a µOPs cache that are determined by the branch prediction (BP) unit. The instruction stream and the branch prediction unit track instructions in 64B windows. Zen is AMD's first design to feature a µOPs cache, a unit that not only improves performance, but also saves power (the µOPs cache was first introduced by Intel in their Sandy Bridge microarchitecture).

The branch prediction unit is decoupled and can start working as soon as it receives a desired operation such as a redirect, ahead of traditional instruction fetches. AMD still uses a hashed perceptron system similar to the one used in Jaguar and Bobcat, albeit likely much more finely tuned. AMD stated it's also larger than previous architectures but did not disclose actual sizes. Once the BP detects an indirect target operation, the branch is moved to the Indirect Target Array (ITA) which is 512 entry deep. The BP includes a 32-entry return stack.

In Zen, AMD moved the instruction TLB to BP (to much earlier in the pipeline than in previous architectures). This was done to allow for more-aggressive prefetching by allowing the physical address to be retrieved at an earlier stage. The BP is capable of storing 2 branches per BTB (Branch Target Buffer) entry, reducing the number of BTB reads necessary. ITLB is composed of:

• 8-entry L0 TLB, all page sizes
• 64-entry L1 TLB, all page sizes
• 512-entry L2 TLB, no 1G pages

Fetching[edit]

Instructions are fetched from the L2 cache at the rate of 32B/cycle. Zen features an asymmetric level 1 cache with a 64 KiB instruction cache, double the size of the L1 data cache. Depending on the branch prediction decision instructions may be fetched from the instruction cache or from the µOPs cache in which eliminates the need for performing the costly instruction decoding.