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This is the talk page for discussing improvements to the amd/microarchitectures/zen page.
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Additional numbers[edit]

Given we have a source in the know, here are some additional numbers we posted that might require double-checking once Zen is fully published:

  • instruction byte buffer -> 20 x 16B
  • Op cache -> 2K instructions
    • 8 inst/cycle

Other numbers that obtained were corroborated by AMD already so I've left them out.

--ChipIt (talk) 18:13, 6 February 2017 (EST)

neural network[edit]

seriously what's up with AMD calling their hash perceptron predictor a "neural network predictor" all of a sudden? Sure it's a NN, but common! they've been using that for YEARS. Nothing has changed. And all those review sites are running with it like are working for AMD's own marketing department (even Wikipedia). Like it's some kind of a new revolutionary thing. lol --David (talk) 14:35, 2 May 2017 (EDT)

Zen Athlons have SMT[edit]

In Section 20 "All Zen Chips" the table correctly shows the four Athlon SKUs as having two cores and four threads but incorrectly shows SMT as not available. 12:54, 12 May 2019 (EDT)

Fixed! thank you. --David (talk) 13:50, 12 May 2019 (EDT)