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  • Property:ram
    This is a '''[[has type::quantity]]''' property representing the size of the RAM of the microcontroller/IC.
    379 bytes (49 words) - 01:02, 19 May 2016
  • Property:ram breakdown
    This is a '''[[has type::string]]''' property representing the size of the RAM in breakdown representation.
    152 bytes (23 words) - 03:20, 20 January 2016
  • nanotube-ram
    {{title|Nanotube-RAM (NRAM)}} ...nge]] [[memory-class storage|memory-class storage]] [[random access memory|RAM]]. NRAM is proprietary technology developed by [[Nantero]] licenseable to m
    6 KB (1,010 words) - 02:42, 31 January 2019

Page text matches

  • mirc/component object model
    === RAM information === # RAM Info #
    27 KB (3,608 words) - 11:41, 25 October 2018
  • intel/mcs-4/4004
    ...e chip was capable of accessing 4KB of [[program memory]] and 640 bytes of RAM. The 4004 was part of the [[Intel MCS-4]] system. ...a bus pins || rowspan="4" | Address and data communication to the ROM and RAM occurs on D0-D3.
    5 KB (748 words) - 21:37, 21 November 2021
  • intel/quark
    ! Number !! Launch Date !! GP I/O !! Timers !! RAM !! Flash (Inst/Prog) !! Cores !! Threads !! Clock !! TDP !! L2$ !! Package
    4 KB (434 words) - 03:31, 15 February 2016
  • microprocessor
    ...'') - a microprocessor that contains a few additional components such as [[RAM]], [[ROM]], and programmable [[I/O]] ports primarily designed to control an
    8 KB (1,149 words) - 00:41, 16 September 2019
  • 3 µm lithography process
    ** Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
    3 KB (314 words) - 23:04, 20 May 2018
  • 2 µm lithography process
    * Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
    8 KB (969 words) - 12:31, 22 February 2019
  • toshiba/t3400/t3472
    | ram = 8 B | ram break = 16x4 bit
    1 KB (119 words) - 14:45, 3 February 2016
  • hitachi/hmcs-4
    ...plete system was made of 4 chips. The chipset included a [[ROM]] chip, a [[RAM]] chip, [[shift register]], and a [[4-bit architecture|4-bit]] [[microproce | {{hitachi|HD35402}} || RAM
    2 KB (266 words) - 00:54, 19 May 2016
  • resident set size
    ...ent set size''' ('''RSS''') is the amount of space of [[physical memory]] (RAM) held by a [[process]]. The value is typically specified in [[bytes]] or [[
    5 KB (692 words) - 10:20, 3 June 2020
  • microprocessors used in spacecrafts
    ...nce Computer]] || [[discrete logic|discrete IC]] RTL || 2.048 MHz || 4 KB (RAM)<br />73.73 KB (ROM) || 70 lb
    11 KB (1,334 words) - 18:26, 10 May 2019
  • intel
    '''RAM:'''
    9 KB (1,150 words) - 00:03, 2 October 2022
  • List of digital circuits
    * [[RAM]]s
    615 bytes (65 words) - 16:22, 21 July 2014
  • general instrument/sba
    ! Part !! [[RAM]] !! [[ROM]] !! I/O Ports !! Notes
    2 KB (244 words) - 00:33, 19 May 2016
  • general instrument/sba/sba-1
    | ram = 120 b | ram break = 120x1 bits
    1 KB (140 words) - 05:28, 22 January 2016
  • amd/am2900
    ...oller supporting 16K and 64K [[mosfet|MOS]] dynamic [[random access memory|RAM]] || 40, 44 ...supporting 16K, 64K and 256K [[mosfet|MOS]] dynamic [[random access memory|RAM]] || 48, 68
    9 KB (1,061 words) - 22:55, 18 June 2019
  • hitachi/hmcs40
    ...28 Words (10-bit ea) of pattern ROM. 32 to 160 digits (4-bit ea) of data [[RAM]]. Chips also contained Event/Timer-Counter and 22-44 I/O lines. Output was ! Model !! ROM !! RAM !! Registers !! Stack Registers !! I/O Lines !! Part No.
    4 KB (400 words) - 19:05, 24 May 2016
  • matsushita/mn1400
    | {{\|MN1400}} || 1024x8 ROM, 64x4 RAM || NMOS || General Purpose | {{\|MN1402}} || 7684x8 ROM, 32x4 RAM || NMOS ||
    4 KB (462 words) - 19:14, 13 October 2019
  • matsushita/mn1500
    | {{matsushita|MN1542}} || 2048x8 ROM, 152x4 RAM, 28 I/O || NMOS || | {{matsushita|MN1544}} || 4096x8 ROM, 256x4 RAM, 28 I/O || NMOS ||
    3 KB (301 words) - 19:23, 13 October 2019
  • motorola/10800
    | {{\|10806}} || 32 words x 9-bit RAM
    2 KB (179 words) - 00:03, 3 February 2016
  • national semiconductor/cops i
    | {{\|MM57140}} || Single-chip; 630x8-bit ROM, 55x4-bit RAM | {{\|MM5785}} || [[RAM]] interface (between {{\|MM5782}} and {{\|MM5799}})
    2 KB (274 words) - 18:29, 5 February 2016
  • national semiconductor/cops ii
    ! Part !! ROM !! RAM !! Frequency !! Package !! Notes ...lations independently of each other and capable of accessing the same ROM, RAM, and I/O ports.
    6 KB (685 words) - 22:49, 5 February 2016
  • fairchild/9400
    | {{fairchild|9410}} || 16x4 Clocked RAM (16x4-bit)
    2 KB (223 words) - 23:04, 5 October 2017
  • western digital/cr1872 series
    | {{wd|CR1872}} || 32x4-bit RAM, 512x10-bit ROM | {{wd|CR2272}} (WD40) || 32x4-bit RAM, 512x10-bit ROM, LED driver, [[DIL-40]]
    732 bytes (87 words) - 01:08, 6 November 2015
  • fairchild/4700
    | {{\|4710}} || 16x4-bit RAM Register Stack | {{\|4720}} || 256x1-bit RAM Register Stack
    3 KB (283 words) - 17:18, 12 December 2016
  • mitsubishi/melps 4
    ! Part !! ROM !! RAM !! Frequency !! I/O<br>Ports !! Package !! Notes
    4 KB (388 words) - 19:48, 6 February 2016
  • fujitsu/mb8840
    ! Part !! ROM !! RAM !! I/O Ports !! Instructions !! Notes
    2 KB (263 words) - 14:57, 4 February 2016
  • fujitsu/mb88500
    | {{fujitsu|MB88501}} || 4k x 8-bit ROM, 196x4-bit RAM | {{fujitsu|MB88501H}} || 4k x 8-bit ROM, 256x4-bit RAM
    2 KB (215 words) - 14:55, 4 February 2016
  • fujitsu/mb8850
    ! Part !! ROM !! RAM !! I/O Ports !! Instructions !! Notes
    2 KB (230 words) - 07:46, 28 February 2017
  • american microsystems/s2000
    ! Part !! ROM !! RAM !! Notes | {{\|S2000}} || 1k x 8-bit || 64x4-bit RAM || 51 instructions
    2 KB (280 words) - 00:57, 19 May 2016
  • epson/s1c63
    ! Part !! RAM !! ROM !! I/O Ports !! Package ! Part !! RAM !! ROM !! I/O Ports !! Package
    5 KB (620 words) - 21:04, 7 February 2016
  • 7400 series
    ...and gates]] and [[or gates]] as well as [[register]]s, [[decoder]]s, and [[RAM]] units.
    7 KB (851 words) - 20:53, 29 July 2021
  • ti/tms1000
    ...n 1974. A few dozen different variations were created with various ROM and RAM sizes. Due to its cheap price, the TMS1000 family enjoyed a tremendous succ ! Part Number !! ROM !! RAM !! I/O Pins !! Technology !! Notes
    6 KB (711 words) - 04:39, 26 April 2017
  • intel/mcs-4
    ...[/4004|4004]] [[CPU]], however its designed to be fully functioning with [[RAM]] and [[shift register]]. Additionally two more chips, the [[/4008|4008]] a | [[/4002|4002]] || [[RAM]]
    4 KB (433 words) - 22:40, 27 June 2019
  • epson/s1c60
    ! Part !! RAM !! ROM !! In Ports !! Out Ports !! Package
    2 KB (295 words) - 21:03, 7 February 2016
  • microcontroller
    ...s a [[microprocessor]] that contains a few additional components such as [[RAM]], [[ROM]], and programmable I/O ports primarily designed to control and dr
    2 KB (344 words) - 15:51, 21 March 2024
  • rockwell international/pps-4
    ...he {{\|10706}} clock generator, GP I/O {{\|10696}}, ROM ({{\|A05|A05xx}}), RAM ({{\|10432}}), and a [[7400 series]] 74154 decoder. | {{\|10432}} || [[RAM]] ||
    3 KB (359 words) - 17:26, 19 May 2016
  • nec/μcom-42
    <tr><th>Model</th><th>Part</th><th>Introduction</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?ram breakdown
    2 KB (316 words) - 00:54, 19 May 2016
  • nec/μcom-42/μpd548
    | ram = 48 B | ram break = 96x4 bit
    2 KB (183 words) - 05:49, 20 January 2016
  • Property:ram
    This is a '''[[has type::quantity]]''' property representing the size of the RAM of the microcontroller/IC.
    379 bytes (49 words) - 01:02, 19 May 2016
  • Property:rom
    * [[Property:ram]]
    379 bytes (49 words) - 01:02, 19 May 2016
  • Property:ram breakdown
    This is a '''[[has type::string]]''' property representing the size of the RAM in breakdown representation.
    152 bytes (23 words) - 03:20, 20 January 2016
  • Property:rom breakdown
    * [[Property:ram breakdown]]
    152 bytes (23 words) - 03:20, 20 January 2016
  • nec/μcom-42/μpd555
    | ram = 48 B | ram break = 96x4 bit
    2 KB (198 words) - 07:26, 20 January 2016
  • nec/μcom-43
    <tr><th>Model</th><th>Part</th><th>Introduction</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?ram breakdown
    2 KB (288 words) - 16:58, 8 November 2016
  • nec/μcom-43/μpd546
    | ram = 48 B | ram break = 96x4 bit
    1 KB (149 words) - 18:28, 20 January 2016
  • nec/μcom-43/μpd556
    | ram = 48 B | ram break = 96x4 bit
    2 KB (258 words) - 05:24, 1 August 2018
  • nec/μcom-44
    <tr><th>Model</th><th>Part</th><th>Introduction</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?ram breakdown
    2 KB (280 words) - 01:00, 19 May 2016
  • nec/μcom-45
    <tr><th>Model</th><th>Part</th><th>Introduction</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?ram breakdown
    2 KB (290 words) - 01:00, 19 May 2016
  • nec/μcom-44/μpd547
    | ram = 32 B | ram break = 64x4 bit
    1 KB (144 words) - 08:59, 20 January 2016
  • nec/μcom-45/μpd550
    | ram = 16 B | ram break = 32x4 bit
    1 KB (159 words) - 09:30, 20 January 2016
  • nec/μcom-43/μpd553
    | ram = 48 B | ram break = 96x4 bit
    2 KB (180 words) - 11:43, 22 January 2016
  • nec/μcom-43/μpd650
    | ram = 48 B | ram break = 96x4 bit
    1 KB (162 words) - 21:12, 20 January 2016
  • nec/μcom-44/μpd547l
    | ram = 32 B | ram break = 64x4 bit
    1 KB (170 words) - 22:35, 20 January 2016
  • nec/μcom-44/μpd651
    | ram = 32 B | ram break = 64x4 bit
    1 KB (168 words) - 22:58, 20 January 2016
  • nec/μcom-44/μpd552
    | ram = 32 B | ram break = 64x4 bit
    1 KB (159 words) - 22:58, 20 January 2016
  • nec/μcom-45/μpd554
    | ram = 16 B | ram break = 32x4 bit
    2 KB (184 words) - 13:17, 22 January 2016
  • nec/μcom-45/μpd652
    | ram = 16 B | ram break = 32x4 bit
    1 KB (160 words) - 00:35, 21 January 2016
  • nec/μcom-4/isa
    | INM || 1D || 1 || 1 + skip || (DP) = (DP) + 1 || Increment RAM content pointed by DP, skip if result is zero || on (DP) = 0 | DEM || 1F || 1 || 1 + skip || (DP) = (DP) - 1 || Decrement RAM content pointed by DP, skip if result is 0Fh || on (DP) = 0Fh
    7 KB (889 words) - 13:27, 29 October 2023
  • general instrument/sba/sba
    | ram = 120 b | ram break = 120x1 bits
    1 KB (114 words) - 05:27, 22 January 2016
  • nec/μcom-43/μpd557l
    | ram = 48 B | ram break = 96x4 bit
    2 KB (244 words) - 06:13, 1 August 2018
  • nec/μcom-45/μpd550l
    | ram = 16 B | ram break = 32x4 bit
    1 KB (171 words) - 13:22, 22 January 2016
  • nec/μcom-45/μpd554l
    | ram = 16 B | ram break = 32x4 bit
    1 KB (184 words) - 13:22, 22 January 2016
  • rockwell international/pps-4-1
    ! Part !! RAM !! ROM !! I/O Ports !! Notes
    2 KB (219 words) - 01:00, 19 May 2016
  • intel/mcs-40
    | {{\|4101}} || [[RAM]]
    2 KB (177 words) - 15:36, 12 May 2016
  • toshiba/t3400
    <tr><th>Model</th><th>Part</th><th>ROM</th><th>RAM</th><th>Pins</th></tr> |?ram breakdown
    2 KB (233 words) - 15:20, 3 February 2016
  • toshiba/t3400/t3444
    | ram = 16 B | ram break = 16x8 bit
    1 KB (146 words) - 11:49, 23 May 2021
  • hitachi/hd404720
    ! Part !! program ROM !! pattern ROM !! RAM !! I/O Ports !! Notes ...\|HD404720}} || 16,384x10-bit || 8,192x10-bit || 512x 4-bit + 64-digit VFD RAM || 56 ||
    2 KB (214 words) - 15:55, 4 February 2016
  • hitachi/hmcs400
    ! Part !! ROM !! RAM !! Line !! Notes
    9 KB (1,127 words) - 20:43, 8 February 2016
  • rca/epic
    | {{\|GP201}} || [[RAM]] (1024x4-bit)
    3 KB (297 words) - 22:54, 24 April 2016
  • atmel/marc4
    ! Part !! ROM<br>(Prog) !! ROM<br>(Data) !! RAM !! I/O Ports !! Package !! Mem Type !! Notes ! Part !! ROM !! RAM !! I/O !! Package !! Notes
    6 KB (787 words) - 21:05, 7 February 2016
  • oki/olms-64
    ! Part !! ROM !! RAM !! I/O !! Stack !! Package !! Notes
    3 KB (275 words) - 23:03, 7 February 2016
  • oki/olms-65
    ! Part !! ROM !! RAM !! I/O !! Stack !! Package !! Notes
    2 KB (224 words) - 22:21, 7 February 2016
  • oki/olms-60
    ! Part !! ROM !! RAM !! I/O !! Stack !! Inst. !! Frequency !! Package !! Notes
    2 KB (200 words) - 22:58, 7 February 2016
  • oki/olms-50
    ! Part !! ROM !! RAM !! I/O !! Stack !! Inst. !! Frequency !! Package !! Notes
    2 KB (235 words) - 22:56, 7 February 2016
  • oki/olms-40
    ! Part !! ROM !! RAM !! I/O !! Stack !! Inst. !! Frequency !! Package !! Notes
    2 KB (225 words) - 22:47, 7 February 2016
  • sharp corporation/sm
    ! Part !! Tech !! ROM !! RAM !! Description ...4}} || CMOS || 2 kB || 96x4 b || built-in LCD driver, optional external 1K RAM
    2 KB (260 words) - 19:14, 8 February 2016
  • amd/am29100
    ...considerably more complex circuitry on a single chip such as [[scratchpad RAM]], a [[barrel shifter]], and [[bit manipulation]] capabilities.
    3 KB (323 words) - 11:26, 15 August 2017
  • fairchild/f8
    ! Part !! I/O Lines !! Regs !! RAM !! ROM !! Description
    2 KB (172 words) - 17:18, 12 December 2016
  • intel/mcs-80
    | {{\|8222}} || || Dynamic RAM Refresh Controller | {{intel|8316A}} || 2048x8 bit || MOS RAM
    4 KB (406 words) - 16:10, 26 January 2019
  • intel/microarchitectures/bonnell
    ** RAM
    38 KB (5,468 words) - 20:29, 23 May 2019
  • intel/microarchitectures/saltwell
    ** RAM
    7 KB (872 words) - 19:42, 30 November 2017
  • intel/microarchitectures/silvermont
    ** RAM
    9 KB (1,160 words) - 09:35, 25 September 2019
  • intel/microarchitectures/airmont
    ** RAM
    5 KB (568 words) - 19:40, 30 November 2017
  • intel/microarchitectures/goldmont
    ** RAM
    7 KB (956 words) - 23:05, 23 March 2020
  • amd/am386
    ...AMD's chip a few other advantages, such as not requiring a separate static RAM chip to store machine state (e.g. [[register file]]) when in maximum saving
    8 KB (1,077 words) - 14:50, 2 April 2020
  • amd/am186ex
    * Pseudo static RAM (PSRAM) controller ...]]s supported all the features of the Am186ES as well as 32K of integrated RAM on-die.
    9 KB (1,276 words) - 16:07, 28 June 2016
  • amd/am186ex/am186es–20vc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (387 words) - 17:00, 30 June 2017
  • amd/am186ex/am186es–25vc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (387 words) - 17:01, 30 June 2017
  • amd/am186ex/am186es–33vc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (387 words) - 17:01, 30 June 2017
  • amd/am186ex/am186es–40vc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (387 words) - 17:01, 30 June 2017
  • amd/am186ex/am186eslv–20vc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (402 words) - 16:59, 30 June 2017
  • amd/am186ex/am186eslv–25vc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (402 words) - 17:00, 30 June 2017
  • amd/am186ex/am186es–20kc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (387 words) - 17:00, 30 June 2017
  • amd/am186ex/am186es–25kc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (387 words) - 17:00, 30 June 2017
  • amd/am186ex/am186es–33kc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (387 words) - 17:01, 30 June 2017
  • amd/am186ex/am186es–40kc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (387 words) - 17:01, 30 June 2017
  • amd/am186ex/am186es–20ki\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (397 words) - 17:00, 30 June 2017
  • amd/am186ex/am186es–25ki\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (397 words) - 17:01, 30 June 2017
  • amd/am186ex/am186eslv–20kc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (400 words) - 16:59, 30 June 2017
  • amd/am186ex/am186eslv–25kc\w
    * Pseudo static RAM (PSRAM) controller
    4 KB (400 words) - 17:00, 30 June 2017
  • ambric/am2000
    * 2x '''RAM Units''' (RU) ::Each RAM Unit contains 4 2 kB RAM banks, each independently accessed via a dynamically programmed channel ope
    11 KB (1,421 words) - 14:45, 9 December 2018
  • ambric/am2000/am2045
    ...43 homogeneous 'Brics' laid out in a 5 by 9 grid to form 344 cores and 344 RAM units. ** 2x [[RAM]] Unit (RU)
    3 KB (367 words) - 15:16, 13 December 2017
  • ambric/am2000/am2035
    ...ade of 35 homogeneous 'Brics' laid out in a grid to form 280 cores and 280 RAM units. ** 2x [[RAM]] Unit (RU)
    3 KB (280 words) - 15:16, 13 December 2017
  • ambric/am2000/am2024
    ...ade of 24 homogeneous 'Brics' laid out in a grid to form 192 cores and 192 RAM units. ** 2x [[RAM]] Unit (RU)
    3 KB (280 words) - 15:16, 13 December 2017
  • ambric/am2000/am2012
    ...made of 12 homogeneous 'Brics' laid out in a grid to form 96 cores and 96 RAM units. ** 2x [[RAM]] Unit (RU)
    3 KB (280 words) - 15:16, 13 December 2017
  • ambric/am2000/am2045b
    ** 2x [[RAM]] Unit (RU)
    3 KB (344 words) - 15:16, 13 December 2017
  • ambric/am2000/am2029
    ** 2x [[RAM]] Unit (RU)
    3 KB (256 words) - 15:16, 13 December 2017
  • ambric/am2000/am2016
    ** 2x [[RAM]] Unit (RU)
    3 KB (256 words) - 15:16, 13 December 2017
  • ambric/am2000/am2070
    ** 2x [[RAM]] Unit (RU)
    3 KB (256 words) - 15:16, 13 December 2017
  • mathstar/builder
    *** Dual-ported RAM, single-cycle access * Internal Block [[RAM]]
    5 KB (596 words) - 21:23, 19 November 2017
  • mathstar/arrix
    ** 128 Byte, dualport RAM or FIFO * 12x Internal [[RAM]] banks
    4 KB (492 words) - 00:37, 28 June 2016
  • amd/microarchitectures/zen 2
    ...ed number of microcode entry addresses and redirect execution to the patch RAM.
    57 KB (8,701 words) - 22:11, 9 October 2022
  • mos technology
    *{{mos|6530}} ROM/RAM I/O Timer (RRIOT) *{{mos|6532}} RAM I/O Timer (RIOT)
    2 KB (269 words) - 18:40, 31 August 2021
  • acorn/microarchitectures/arm3
    ...f negligible performance. Each CAM entry refers to one line of data in the RAM. Each line consists of four 32-bit words (i.e., 128 bit lines) with the low ...On a hit the appropriate line address are generated to be retrieved by the RAM.
    7 KB (1,035 words) - 06:24, 21 November 2023
  • intel/microarchitectures/goldmont plus
    ** RAM
    9 KB (1,128 words) - 13:28, 17 July 2023
  • amd/microarchitectures/zen+
    ...condary storage devices can actually extend to main memory. Up to 2 GiB of RAM may be configured and reserved as another level of cache for the HDD on top
    11 KB (1,613 words) - 08:39, 3 March 2024
  • ti/tms1000/tms1099
    ...9JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 64x4 bits of RAM, 8 bits of "O" parallel latched data outputs and 13 "R" individually addres
    824 bytes (121 words) - 14:56, 13 December 2017
  • ti/tms1000/tms1098
    ...JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 128x4 bits of RAM, 8 bits of "O" parallel latched data outputs and 16 "R" individually addres
    900 bytes (128 words) - 14:56, 13 December 2017
  • intel/documents
    ...ete offerings of their products including [[microprocessors]], [[ROM]]s, [[RAM]]s, [[memory]] peripherals, and various other [[ICs]].
    4 KB (448 words) - 15:02, 3 October 2019
  • greenwaves/gap8
    The chip supports up to 16 MiB of SDRAM or additional RAM through the HyperBus interface. * HyperBus (External Flash and RAM)
    6 KB (981 words) - 14:11, 28 February 2018
  • verilog/example modules
    | {{\|Single-port RAM}} || | {{\|Dual-port RAM}} ||
    617 bytes (85 words) - 06:39, 21 April 2018
  • nvidia/microarchitectures/nvdla
    ...To aid with the buffer is a memory interface which supports both internal RAM and SDRAM support. With a smaller convolutional buffer size, the second lev | 1 RAM Interface || 2 RAM Interface
    5 KB (713 words) - 18:16, 1 September 2022
  • nanotube-ram
    {{title|Nanotube-RAM (NRAM)}} ...nge]] [[memory-class storage|memory-class storage]] [[random access memory|RAM]]. NRAM is proprietary technology developed by [[Nantero]] licenseable to m
    6 KB (1,010 words) - 02:42, 31 January 2019
  • NRAM
    #REDIRECT [[nanotube-ram]]
    26 bytes (2 words) - 23:43, 5 May 2019
  • nram
    #REDIRECT [[nanotube-ram]]
    26 bytes (2 words) - 02:42, 31 January 2019
  • static random-access memory
    ...memory]]-based storage that holds data in a static form. That is, static [[RAM]] retains its data for as long as the memory device has power. SRAM is the ...bit state. This is in contrast to other forms of memory, such as [[Dynamic RAM]], where the stored state of the bit is kept in the form of a charge that l
    6 KB (920 words) - 03:14, 30 December 2019
  • MCST/elbrus
    *Supported type of RAM - DDR2
    1 KB (161 words) - 14:51, 14 November 2019
  • centaur/microarchitectures/cha
    *** 2x8 MiB banks (D-RAM and W-RAM) ...ECC-protected. The caches are not coherent with the L3 or DRAM. Since the RAM is available even when the NCORE is not used, it may be used as a scratch p
    24 KB (3,792 words) - 04:37, 30 September 2022
  • amd/packages/socket am3
    |MA/MB_RESET_L||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
    12 KB (1,960 words) - 12:23, 18 July 2020
  • amd/packages/ft1
    |M_RESET_L||O-IO-S||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
    14 KB (2,611 words) - 00:31, 4 April 2022
  • amd/packages/socket fm1
    |MA/MB_RESET_L||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
    7 KB (1,063 words) - 15:50, 4 September 2020
  • amd/packages/socket f
    |MA/MB_RESET_L||DRAM Reset pin for Suspend-to-RAM power management mode
    11 KB (1,717 words) - 17:25, 5 February 2021
  • amd/packages/socket s1g4
    |H16||RSVD||RSVD_M1||MA_RESET_L||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
    10 KB (1,781 words) - 19:23, 12 January 2021
  • arm holdings/microarchitectures/cortex-a510
    **** Slice includes: data RAMs, L2 tags, L2 replacement RAM, and L1 duplicate tag RAMs
    15 KB (2,282 words) - 11:20, 10 January 2023
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