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Page title matches

  • Property:has intel identity protection technology support
    ...'' property holding whether the microprocessors has Intel {{intel|Identity Protection Technology}} support.
    142 bytes (20 words) - 20:16, 6 January 2017
  • Property:has intel supervisor mode execution protection
    ...ng whether the microprocessors has Intel {{intel|Supervisor Mode Execution Protection}} (SMEP) support also known as ''OS Guard''.
    182 bytes (27 words) - 21:44, 3 June 2017
  • Property:x86/has memory protection extensions
    ...rty holding whether the microprocessors has support for x86's {{x86|Memory Protection Extensions}}.
    142 bytes (22 words) - 21:09, 6 April 2018
  • x86/thermal protection
    {{x86 title|Thermal protection}} ...es motherboard logic with the THERMTRIP signal, active low, if the thermal protection circuit has tripped. The motherboard is supposed to power off the processor
    536 bytes (81 words) - 18:52, 12 January 2021

Page text matches

  • mirc/commands/flood
    * '''[on|off|clear]''' - turns flood protection on/off or clear the settings
    1 KB (156 words) - 12:03, 14 July 2020
  • intel/core i7
    ...{{intel|Fast Memory Access|FMA}}, {{intel|Flex Memory}}, {{intel|Identity Protection}}, and {{intel|My WiFi}} ...Protection}}, {{intel|Secure Key}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}
    43 KB (5,739 words) - 21:30, 22 April 2024
  • fairchild/f9450
    | F9451 || [[Block Protection Unit]] | F9452 || [[Block Protection Unit]]
    2 KB (253 words) - 16:27, 20 December 2015
  • mirc/sendmessage
    ** 4 = Use flood protection if turned on, can be or'd with 1 or 2, and 8
    6 KB (1,044 words) - 21:49, 25 April 2024
  • intel/microarchitectures/goldmont
    * {{x86|MPX|<code>MPX</code>}} -Memory Protection Extensions
    7 KB (956 words) - 23:05, 23 March 2020
  • intel/pentium (2009)
    ...e as well as introduced a number of new security features including Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}}. Kaby Lake-based Pentiums utilize th ...el|IPT}}, {{intel|Secure Key}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}}), and {{intel|OS Guard}}.
    20 KB (2,661 words) - 00:45, 11 October 2017
  • intel/celeron
    ...tep}} (EIST), Software Guard ({{intel|SGX}}), {{intel|Secure Key}}, Memory Protection ({{intel|MPX}}), {{intel|OS Guard}} ...|TSX}}, {{intel|SpeedStep}} (EIST), Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|Secure Key}}, {{intel|Speed Sh
    25 KB (3,201 words) - 03:13, 22 September 2018
  • intel/microarchitectures/skylake (client)
    * {{x86|MPX|<code>MPX</code>}} -Memory Protection Extensions * New Security technology - Better protection against hardware and software attacks
    79 KB (11,922 words) - 06:46, 11 November 2022
  • intel/microarchitectures/kaby lake
    ...intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support
    38 KB (5,431 words) - 10:41, 8 April 2024
  • x86/umip
    ...while the Current Privilege Level (CPL) is greater than 0 causes a general-protection exception.
    2 KB (338 words) - 01:25, 30 December 2019
  • intel/core i3
    ...{{intel|Fast Memory Access|FMA}}, {{intel|Flex Memory}}, {{intel|Identity Protection}}, and {{intel|My WiFi}} * '''Tech:''' Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|VT-x}}, and {{intel|Hyper-Thre
    25 KB (3,397 words) - 03:12, 3 October 2022
  • intel/core i5
    ...{{intel|Fast Memory Access|FMA}}, {{intel|Flex Memory}}, {{intel|Identity Protection}}, and {{intel|My WiFi}} ...Protection}}, {{intel|Secure Key}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}
    34 KB (4,663 words) - 20:38, 20 February 2023
  • amd/microarchitectures/zen
    <tr><th>Protection Per</th><td>Whole Machine</td><td>Individual VMs</td></tr> <tr><th>Type of Protection</th><td>Physical Memory Attack</td><td>Physical Memory Attack<br>Vulnerable
    79 KB (12,095 words) - 15:27, 9 June 2023
  • x86/extensions
    | [[2015]] || {{x86|MPX}} || {{intel|Skylake|l=arch}} || Memory Protection Extensions
    6 KB (764 words) - 08:53, 7 June 2020
  • amd/packages/socket am4
    |THERMTRIP_L||{{x86|Thermal protection|Temperature Trip}} Input/Output
    30 KB (6,098 words) - 01:58, 12 January 2024
  • Property:has intel identity protection technology support
    ...'' property holding whether the microprocessors has Intel {{intel|Identity Protection Technology}} support.
    142 bytes (20 words) - 20:16, 6 January 2017
  • intel/cores/kaby lake x
    ...el|VT-d}}, {{intel|SpeedStep}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}})
    3 KB (443 words) - 10:07, 24 October 2018
  • phytium/microarchitectures/xiaomi
    ** ECC and parity protection on all caches, tags, and TLBs
    7 KB (940 words) - 00:12, 8 March 2021
  • amd/microarchitectures/zen 3
    * {{x86|PKU}} - Memory Protection Keys for Users ** <code>RDPKRU</code> - Read Protection Key Rights
    15 KB (1,978 words) - 22:13, 6 April 2023
  • loongson
    | headquarters = Building No. 2, Zhongguancun Environmental protection park, Haidian, Beijing, China
    2 KB (181 words) - 23:20, 20 March 2017
  • intel/cores/kaby lake dt
    ...Protection}}, {{intel|Secure Key}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|TXT}}
    5 KB (660 words) - 08:08, 17 July 2018
  • intel/xeon bronze
    ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
    7 KB (973 words) - 14:08, 2 June 2019
  • intel/xeon silver
    ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
    7 KB (993 words) - 02:57, 2 March 2020
  • intel/xeon gold
    ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
    9 KB (1,195 words) - 05:38, 8 June 2021
  • intel/xeon platinum
    ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
    11 KB (1,476 words) - 17:13, 30 December 2022
  • intel/cores/skylake sp
    ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
    7 KB (934 words) - 14:21, 10 June 2018
  • intel/core i9
    ...el|VT-d}}, {{intel|SpeedStep}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}})
    9 KB (1,197 words) - 02:30, 6 April 2024
  • intel/cores/skylake dt
    ...Protection}}, {{intel|Secure Key}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|TXT}}
    4 KB (561 words) - 08:11, 17 July 2018
  • intel/cores/skylake y
    |?has intel supervisor mode execution protection
    4 KB (571 words) - 06:30, 6 April 2019
  • Property:has intel supervisor mode execution protection
    ...ng whether the microprocessors has Intel {{intel|Supervisor Mode Execution Protection}} (SMEP) support also known as ''OS Guard''.
    182 bytes (27 words) - 21:44, 3 June 2017
  • intel/microarchitectures/skylake (server)
    * {{x86|MPX|<code>MPX</code>}} - Memory Protection Extensions * {{x86|PKU|<code>PKU</code>}} - Memory Protection Keys for Userspace
    52 KB (7,651 words) - 00:59, 6 July 2022
  • intel/cores/kaby lake r
    ...{{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
    5 KB (751 words) - 09:52, 11 February 2019
  • intel/cores/skylake w
    ...2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Vol
    4 KB (613 words) - 12:46, 3 June 2019
  • intel/xeon w
    ...2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Vol ...2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Vol
    10 KB (1,442 words) - 15:17, 11 September 2021
  • microsoft/scorpio engine
    | THERMTRIP_N || {{x86|thermal protection|Temperature Trip}} Output
    15 KB (2,390 words) - 02:54, 17 May 2023
  • intel/pentium gold
    ...e as well as introduced a number of new security features including Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}}. Kaby Lake-based Pentiums utilize th ...el|IPT}}, {{intel|Secure Key}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}}), and {{intel|OS Guard}}.
    10 KB (1,338 words) - 11:10, 8 April 2018
  • voltage regulator module
    ...ure protection|OTP]], [[undervoltage protection|UVP]], and [[short circuit protection|SCP]]), advanced controllers can actually control how many phases are turne
    18 KB (3,026 words) - 16:55, 19 January 2020
  • page table entry
    ...rame number]] (PFN) and various [[control bits]] such as [[valid bit]] and protection bits (e.g. read-only or execute).
    353 bytes (57 words) - 01:22, 6 November 2017
  • intel/management engine
    * "Storage Protection with Intel® Anti-Theft Technology - Data Protection (Intel® AT-d)", Ned Smith. Intel Technology Journal, Volume 12, Issue 4, 2
    7 KB (949 words) - 15:55, 15 November 2019
  • intel/xeon e
    ...intel|vPro}}, Software Guard ({{intel|SGX}}), {{intel|Secure Key}}, Memory Protection ({{intel|MPX}}), and {{intel|OS Guard}} ...ure Key}}, Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, Identity Protection ({{intel|IPT}}), {{intel|SIPP}}
    11 KB (1,554 words) - 11:14, 2 June 2019
  • greenwaves/gap8
    * Secured execution support with Memory Protection Unit (MPU)
    6 KB (981 words) - 14:11, 28 February 2018
  • Property:x86/has memory protection extensions
    ...rty holding whether the microprocessors has support for x86's {{x86|Memory Protection Extensions}}.
    142 bytes (22 words) - 21:09, 6 April 2018
  • intel/cores/cascade lake sp
    ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
    9 KB (1,291 words) - 13:48, 27 February 2020
  • amd/sb-tsi
    * {{x86|Thermal protection}}
    2 KB (275 words) - 01:17, 2 April 2023
  • intel/cores/ice lake y
    ...{{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
    5 KB (731 words) - 19:08, 26 February 2020
  • intel/cores/whiskey lake u
    ...{{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
    4 KB (508 words) - 23:23, 2 August 2020
  • intel/cores/ice lake u
    ...{{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
    6 KB (810 words) - 23:19, 12 May 2020
  • intel/cores/comet lake u
    ...{{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
    4 KB (529 words) - 23:19, 12 May 2020
  • intel/cores/coffee lake e
    ...{intel|TSX}}, {{intel|Secure Key}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|TXT}}
    5 KB (748 words) - 12:14, 2 June 2019
  • amd/packages/socket tr4
    |THERMTRIP_L||B-IO33-OD||{{x86|Thermal protection|Temperature Trip}} Input/Output
    86 KB (17,313 words) - 02:48, 13 March 2023
  • amd/packages/socket sp3
    |THERMTRIP_L||B-IO33-OD||{{x86|Thermal protection|Temperature Trip}} Input/Output
    110 KB (21,122 words) - 02:46, 13 March 2023
  • arm holdings/microarchitectures/neoverse n1
    *** ECC protection per 64 bits
    7 KB (980 words) - 13:46, 18 February 2023
  • arm holdings/microarchitectures/cortex-a76
    *** Optional parity protection *** Optional ECC protection per 32 bits
    14 KB (2,183 words) - 17:15, 17 October 2020
  • arm holdings/microarchitectures/cortex-a77
    *** Optional parity protection *** Optional ECC protection per 32 bits
    17 KB (2,555 words) - 06:08, 16 June 2023
  • arm holdings/microarchitectures/cortex-a78
    *** Optional parity protection *** Optional ECC protection per 32 bits
    21 KB (3,067 words) - 09:25, 31 March 2022
  • apm/microarchitectures/storm
    *** ECC and Parity protection *** ECC and Parity protection
    2 KB (231 words) - 04:17, 26 September 2018
  • arm holdings/microarchitectures/arm9/pr1
    .... During debug, the ARM940T provides full debug access to the state of the protection unit registers and to the contents of the caches. ...ction + 4KB data caches, write buffer, AMBA bus interface, flexible memory protection unit, external coprocessor support.
    8 KB (1,261 words) - 22:05, 29 December 2018
  • phytium/microarchitectures/mars i
    ...des two 16-lane PCIe 3.0 interfaces. The chips incorporates ECC and parity protection on all caches, tags, and TLBs.
    6 KB (809 words) - 16:49, 15 October 2019
  • intel/cores/coffee lake er
    ...{intel|TSX}}, {{intel|Secure Key}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|TXT}}
    5 KB (721 words) - 12:41, 12 June 2023
  • intel/cores/cascade lake w
    ...2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Vol
    4 KB (610 words) - 11:34, 7 October 2019
  • MCST
    ...d in computing systems with high requirements for information security and protection against hacking. Computers with Elbrus processors are used in the armed for
    3 KB (423 words) - 16:42, 14 November 2019
  • amd/packages/socket 754
    * Thermal diode, overtemperature protection
    5 KB (662 words) - 09:51, 29 January 2020
  • amd/packages/socket 940
    * Thermal diode, overtemperature protection
    4 KB (576 words) - 15:27, 30 January 2020
  • amd/packages/socket 939
    * Thermal diode, overtemperature protection
    4 KB (490 words) - 22:47, 9 February 2020
  • amd/List of AMD publications
    ...re.pdf White Paper: AMD SEV-SNP: Strengthening VM Isolation with Integrity Protection and More]||2020-01||Family 19h
    181 KB (24,861 words) - 16:02, 17 April 2022
  • amd/packages/socket am2
    * Thermal diode, overtemperature protection
    7 KB (1,029 words) - 18:40, 22 February 2020
  • amd/packages/socket am2+
    * Thermal diode, overtemperature protection
    8 KB (1,212 words) - 19:01, 22 February 2020
  • intel/cores/cascade lake r
    ...nt Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
    8 KB (1,098 words) - 11:25, 28 February 2020
  • cea-leti/microarchitectures/tsarlet
    ...ry scan]]). The μ-buffers std cell integrates a bidirectional driver, ESD protection, pull-up, and a level-shifter to bridge between the two different domains b
    12 KB (1,895 words) - 10:17, 27 March 2020
  • amd/packages/socket am3
    * Thermal diode, overtemperature protection
    12 KB (1,960 words) - 12:23, 18 July 2020
  • amd/packages/socket am3+
    * Thermal diode, overtemperature protection
    6 KB (822 words) - 15:01, 9 December 2022
  • amd/packages/asb1
    * Thermal diode, overtemperature protection
    3 KB (481 words) - 16:24, 16 March 2023
  • amd/packages/asb2
    * Thermal diode, overtemperature protection
    4 KB (527 words) - 16:25, 16 March 2023
  • amd/packages/ft1
    |THERMTRIP_L||O-IO33-OD||{{x86|Thermal protection|Thermal Sensor Trip}} Output
    14 KB (2,611 words) - 00:31, 4 April 2022
  • amd/packages/socket fm1
    ** DRAM thermal protection
    7 KB (1,063 words) - 15:50, 4 September 2020
  • amd/packages/socket fm2+
    ** DRAM thermal protection
    5 KB (770 words) - 15:12, 4 September 2020
  • amd/packages/socket fm2
    ** DRAM thermal protection
    5 KB (727 words) - 15:34, 4 September 2020
  • amd/packages/ft3
    ** DRAM thermal protection
    5 KB (645 words) - 16:31, 16 March 2023
  • amd/packages/ft3b
    ** DRAM thermal protection
    4 KB (610 words) - 16:33, 16 March 2023
  • amd/packages/socket fs1r2
    ** DRAM thermal protection
    5 KB (755 words) - 13:50, 7 September 2020
  • amd/packages/socket am1
    ** DRAM thermal protection
    5 KB (642 words) - 14:08, 7 September 2020
  • amd/packages/fp2
    ** DRAM thermal protection
    4 KB (641 words) - 23:21, 25 March 2023
  • amd/packages/fp3
    ** DRAM thermal protection
    5 KB (630 words) - 23:22, 25 March 2023
  • amd/packages/fp6
    |THERMTRIP_L||{{x86|thermal protection|Temperature Trip}} Output
    20 KB (3,273 words) - 17:47, 10 May 2023
  • amd/packages/socket f
    |THERMTRIP_L||{{x86|Thermal protection|Thermal Sensor Trip}} output, open drain
    11 KB (1,717 words) - 17:25, 5 February 2021
  • x86/thermal protection
    {{x86 title|Thermal protection}} ...es motherboard logic with the THERMTRIP signal, active low, if the thermal protection circuit has tripped. The motherboard is supposed to power off the processor
    536 bytes (81 words) - 18:52, 12 January 2021
  • amd/packages/socket s1g1
    ** {{x86|Thermal protection}} |THERMTRIP_L||{{x86|Thermal protection|Thermal Sensor Trip}} output
    8 KB (1,126 words) - 18:53, 12 January 2021
  • amd/packages/socket s1g2
    ** {{x86|Thermal protection}} ** DRAM thermal protection
    8 KB (1,211 words) - 19:08, 12 January 2021
  • amd/packages/socket s1g3
    ** {{x86|Thermal protection}}
    5 KB (767 words) - 19:14, 12 January 2021
  • amd/packages/socket s1g4
    ** {{x86|Thermal protection}} |AA8||RSVD||MEMHOT_L||MEMHOT_L||DRAM Thermal Protection input
    10 KB (1,781 words) - 19:23, 12 January 2021
  • amd/packages/socket g34
    |THERMTRIP_L||{{x86|Thermal protection|Temperature Trip}}
    36 KB (7,214 words) - 15:50, 23 April 2022
  • arm holdings/microarchitectures/neoverse v1
    *** ECC protection per 64 bits
    5 KB (748 words) - 16:20, 4 July 2022
  • arm holdings/microarchitectures/cortex-a510
    *** Single Error Detect (SED) parity cache protection *** Error Correcting Code (ECC) cache protection
    15 KB (2,282 words) - 11:20, 10 January 2023
  • amd/packages/socket sp5
    |THERMTRIP_L||O-IO18S5-OD||{{x86|Thermal protection|Temperature Trip}} Output
    105 KB (21,123 words) - 02:59, 13 March 2023
  • amd/packages/socket am5
    |THERMTRIP_L||{{x86|thermal protection|Temperature Trip}} Output
    19 KB (3,162 words) - 17:35, 11 May 2023
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