Semiconductor & Computer Engineering
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Difference between revisions of "intel"
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In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | ||
| + | |||
| + | == Subsidiaries == | ||
| + | * [[Barefoot Networks]] | ||
| + | * [[Movidius]] | ||
| + | * [[Nervana]] | ||
| + | * [[Mobileye]] | ||
== Find Chip == | == Find Chip == | ||
| Line 55: | Line 61: | ||
* {{intel|Core M}} | * {{intel|Core M}} | ||
* {{intel|Core Solo}} | * {{intel|Core Solo}} | ||
| + | * {{intel|Core Ultra}} | ||
* {{intel|EP80579}} | * {{intel|EP80579}} | ||
* {{intel|i860}} | * {{intel|i860}} | ||
| Line 105: | Line 112: | ||
}} | }} | ||
| − | == List of | + | == List of architectures == |
{{collist | {{collist | ||
| count = 1 | | count = 1 | ||
| | | | ||
| − | * {{ | + | * {{\\|MCS-8/ISA|MCS-8 (8008)}} |
| + | * [[x86]] | ||
| + | * {{\\|Configurable Spatial Accelerator}} (CSA) | ||
| + | * {{\\|Programmable Unified Memory Architecture}} (PUMA) | ||
}} | }} | ||
| Line 126: | Line 136: | ||
* {{intel|Enhanced NetBurst|l=arch}} | * {{intel|Enhanced NetBurst|l=arch}} | ||
}} | }} | ||
| + | |||
{{collist | {{collist | ||
| Line 131: | Line 142: | ||
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| − | '''Client:''' | + | '''Client SoC:''' |
* {{intel|Core (client)|l=arch}} | * {{intel|Core (client)|l=arch}} | ||
* {{intel|Penryn (client)|l=arch}} | * {{intel|Penryn (client)|l=arch}} | ||
| Line 143: | Line 154: | ||
* {{intel|Kaby Lake|l=arch}} | * {{intel|Kaby Lake|l=arch}} | ||
* {{intel|Coffee Lake|l=arch}} | * {{intel|Coffee Lake|l=arch}} | ||
| + | * {{intel|Whiskey Lake|l=arch}} | ||
* {{intel|Amber Lake|l=arch}} | * {{intel|Amber Lake|l=arch}} | ||
| − | * {{intel| | + | * {{intel|Comet Lake|l=arch}} |
| + | * {{intel|Keystone Lake|l=arch}} | ||
| + | * {{intel|Rocket Lake|l=arch}} | ||
* {{intel|Cannon Lake|l=arch}} ("Skymont") | * {{intel|Cannon Lake|l=arch}} ("Skymont") | ||
* {{intel|Ice Lake (client)|l=arch}} | * {{intel|Ice Lake (client)|l=arch}} | ||
* {{intel|Tiger Lake|l=arch}} | * {{intel|Tiger Lake|l=arch}} | ||
* {{intel|Alder Lake|l=arch}} | * {{intel|Alder Lake|l=arch}} | ||
| + | * {{intel|Raptor Lake|l=arch}} | ||
* {{intel|Meteor Lake|l=arch}} | * {{intel|Meteor Lake|l=arch}} | ||
| + | * {{intel|Arrow Lake|l=arch}} | ||
| + | * {{intel|Lunar Lake|l=arch}} | ||
| + | |||
}} | }} | ||
| + | |||
{{collist | {{collist | ||
| Line 156: | Line 175: | ||
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| − | '''Server:''' | + | '''Server SoC:''' |
* {{intel|Core (server)|l=arch}} | * {{intel|Core (server)|l=arch}} | ||
* {{intel|Penryn (server)|l=arch}} | * {{intel|Penryn (server)|l=arch}} | ||
| Line 167: | Line 186: | ||
* {{intel|Skylake (server)|l=arch}} | * {{intel|Skylake (server)|l=arch}} | ||
* {{intel|Cascade Lake|l=arch}} | * {{intel|Cascade Lake|l=arch}} | ||
| + | * {{intel|Cooper Lake|l=arch}} | ||
* {{intel|Ice Lake (server)|l=arch}} | * {{intel|Ice Lake (server)|l=arch}} | ||
* {{intel|Sapphire Rapids|l=arch}} | * {{intel|Sapphire Rapids|l=arch}} | ||
| + | * {{intel|Emerald Rapids|l=arch}} | ||
* {{intel|Granite Rapids|l=arch}} | * {{intel|Granite Rapids|l=arch}} | ||
| + | * {{intel|Diamond Rapids|l=arch}} | ||
}} | }} | ||
| − | + | ||
{{collist | {{collist | ||
| − | | count = | + | | count = 4 |
| + | | style= margin-left: 20px; | ||
| + | | | ||
| + | '''Networking SoC:''' | ||
| + | * {{intel|Snow Ridge|l=arch}} | ||
| + | * {{intel|Tanner Ridge|l=arch}} | ||
| + | }} | ||
| + | |||
| + | |||
| + | {{collist | ||
| + | | count = 4 | ||
| + | | style= margin-left: 20px; | ||
| + | | | ||
| + | '''High-Perf (Big Cores):''' | ||
| + | * {{intel|Palm Cove|l=arch}} | ||
| + | * {{intel|Sunny Cove|l=arch}} | ||
| + | * {{intel|Willow Cove|l=arch}} | ||
| + | * {{intel|Golden Cove|l=arch}} | ||
| + | * {{intel|Ocean Cove|l=arch}} | ||
| + | }} | ||
| + | |||
| + | |||
| + | {{collist | ||
| + | | count = 4 | ||
| + | | style= margin-left: 20px; | ||
| | | | ||
| + | '''High-Efficiency (Small Cores)''' | ||
* {{intel|Bonnell|l=arch}} | * {{intel|Bonnell|l=arch}} | ||
* {{intel|Saltwell|l=arch}} | * {{intel|Saltwell|l=arch}} | ||
| Line 184: | Line 231: | ||
* {{intel|Tremont|l=arch}} | * {{intel|Tremont|l=arch}} | ||
}} | }} | ||
| + | |||
'''MCU:''' | '''MCU:''' | ||
{{collist | {{collist | ||
| Line 190: | Line 238: | ||
* {{intel|Lakemont|l=arch}} | * {{intel|Lakemont|l=arch}} | ||
}} | }} | ||
| + | |||
'''ULP ([[ARM]]):''' | '''ULP ([[ARM]]):''' | ||
{{collist | {{collist | ||
| Line 201: | Line 250: | ||
* Continued by [[Marvell]] .. | * Continued by [[Marvell]] .. | ||
}} | }} | ||
| + | |||
| + | |||
'''Server (EPIC) ([[Itanium]]):''' | '''Server (EPIC) ([[Itanium]]):''' | ||
{{collist | {{collist | ||
| Line 249: | Line 300: | ||
| | | | ||
* {{intel|Lakefield|l=arch}} | * {{intel|Lakefield|l=arch}} | ||
| + | * {{intel|Ryefield|l=arch}} | ||
}} | }} | ||
| Line 283: | Line 335: | ||
* {{intel|Arctic Sound|l=arch}} | * {{intel|Arctic Sound|l=arch}} | ||
* {{intel|Jupiter Sound|l=arch}} | * {{intel|Jupiter Sound|l=arch}} | ||
| + | }} | ||
| + | |||
| + | '''Artificial Intelligence:''' | ||
| + | {{collist | ||
| + | | count = 3 | ||
| + | | style= margin-left: 20px; | ||
| + | | | ||
| + | '''Training:''' | ||
| + | * {{intel|Lake Crest|l=arch}} | ||
| + | * {{intel|Spring Crest|l=arch}} | ||
| + | }} | ||
| + | {{clear}} | ||
| + | {{collist | ||
| + | | count = 3 | ||
| + | | style= margin-left: 20px; | ||
| + | | | ||
| + | '''Inference:''' | ||
| + | * {{intel|Spring Hill|l=arch}} | ||
}} | }} | ||
| Line 291: | Line 361: | ||
'''Neuromorphic:''' | '''Neuromorphic:''' | ||
* {{intel|Loihi}} | * {{intel|Loihi}} | ||
| + | * {{intel|Loihi 2}} | ||
'''Artificial Intelligence''' | '''Artificial Intelligence''' | ||
* {{intel|ETANN}} | * {{intel|ETANN}} | ||
| Line 341: | Line 412: | ||
* {{\\|Dynamic Tuning}} | * {{\\|Dynamic Tuning}} | ||
* {{\\|Hyper Scaling}} | * {{\\|Hyper Scaling}} | ||
| + | * {{\\|Speed Select Technology}} (SST) | ||
* {{\\|Turbo Boost Technology}} (TBT) | * {{\\|Turbo Boost Technology}} (TBT) | ||
* {{\\|Thermal Velocity Boost}} (TVB) | * {{\\|Thermal Velocity Boost}} (TVB) | ||
| + | * {{\\|DL Boost}} | ||
| + | }} | ||
| + | |||
| + | == Packaging Technologies == | ||
| + | {{collist | ||
| + | | count = 2 | ||
| + | | | ||
| + | * {{\\|Foveros}} | ||
| + | * {{\\|EMIB}} | ||
}} | }} | ||
Latest revision as of 04:45, 6 November 2024
| Intel | |||||||||
.svg){kind=logo}
| |||||||||
| Type | Public | ||||||||
| Founded | July 18, 1968 Mountain View, California | ||||||||
| Founder | Gordon Moore Robert Noyce Andrew Grove | ||||||||
| Headquarters | Santa Clara, California | ||||||||
| Website | http://www.intel.com | ||||||||
| |||||||||
.svg){kind=logo}
.svg)
Intel Corporation is an American semiconductor company. While most notably known for their development of microprocessors and x86, Intel also designs and manufactures other integrated circuits including flash memory, network interface controllers, GPUs, chipsets, motherboards, and computers.
In addition to x86, Intel used to also design and manufacture ARM-based chips as well as embed ARC-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
Contents
Subsidiaries[edit]
Find Chip[edit]
- By S-Spec
List of processor families[edit]
- 3000
- 80186
- 80188
- 80286
- 80376
- 80386
- 80486
- Atom
- Atom x3
- Atom x5
- Atom x7
- Celeron
- Celeron D
- Celeron M
- Core 2 Duo
- Core 2 Extreme
- Core 2 Quad
- Core 2 Quad Extreme
- Core 2 Solo
- Core Duo
- Core i3
- Core i5
- Core i7
- Core i7 EE
- Core i9
- Core M
- Core Solo
- Core Ultra
- EP80579
- i860
- i960
- iAPX432
- Itanium
- Itanium 2
- MCS-4
- MCS-40
- MCS-48
- MCS-51
- MCS-8
- MCS-80
- MCS-85
- MCS-86
- MCS-88
- MCS-96
- Mobile Pentium II
- Pentium
- Pentium (2009)
- Pentium 4
- Pentium 4 EE
- Pentium 4-M
- Pentium D
- Pentium EE
- Pentium Gold
- Pentium II
- Pentium III
- Pentium III Mobile
- Pentium III Xeon
- Pentium II Mobile
- Pentium II Xeon
- Pentium M
- Pentium MMX
- Pentium Pro
- Pentium Silver
- PXA
- Quark
- Xeon
- Xeon Bronze
- Xeon D
- Xeon E
- Xeon E3
- Xeon E5
- Xeon E7
- Xeon Gold
- Xeon Platinum
- Xeon Silver
- Xeon W
List of architectures[edit]
List of microarchitectures[edit]
Mainstream (x86):
Client SoC:
- Core (client)
- Penryn (client)
- Nehalem (client)
- Westmere (client)
- Sandy Bridge (client)
- Ivy Bridge (client)
- Haswell (client)
- Broadwell (client)
- Skylake (client)
- Kaby Lake
- Coffee Lake
- Whiskey Lake
- Amber Lake
- Comet Lake
- Keystone Lake
- Rocket Lake
- Cannon Lake ("Skymont")
- Ice Lake (client)
- Tiger Lake
- Alder Lake
- Raptor Lake
- Meteor Lake
- Arrow Lake
- Lunar Lake
Server SoC:
Networking SoC:
High-Perf (Big Cores):
High-Efficiency (Small Cores)
MCU:
ULP (ARM):
Server (EPIC) (Itanium):
Early Research:
- Knights Ferry (Aubrey Isle)
- Knights Corner (Angel Isle)
- Knights Landing
- Knights Mill
- Knights Hill
- Knights Peak
Heterogeneous:
GPU:
Integrated:
Discrete:
Artificial Intelligence:
Training:
Inference:
Other Chips[edit]
Neuromorphic:
Artificial Intelligence
Quantum:
RAM:
Architectural Concepts[edit]
Other[edit]
Other topics[edit]
Technologies[edit]
Packaging Technologies[edit]
Documents[edit]
See Documents.
Facts about "Intel"
| company type | public + |
| founded | July 18, 1968 + |
| founded location | Mountain View, California + |
| founder | Gordon Moore +, Robert Noyce + and Andrew Grove + |
| full page name | intel + |
| headquarters | Santa Clara, California + |
| instance of | semiconductor company + |
| name | Intel + |
| website | http://www.intel.com + |
| wikidata id | Q248 + |