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Snow Ridge - Microarchitectures - Intel
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Snow Ridge µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process10 nm
Instructions
ISAx86-64
Succession

Snow Ridge (SNR) is a 10 nm microarchitecture for servers and edge computing designed by Intel. SNR is planned to be introduced in late 2019.

Process Technology[edit]

Snow Ridge is planned for Intel's 10 nm process.

Architecture[edit]

Jacobsville platform[edit]

(Snow Ridge / Parker Ridge)

The Snow Ridge System-on-a-Chip (SoC) product family is Intel’s next generation of communication processors designed in Intel’s 10 nm process technology. The three major subsystems in this highly-integrated SoC are the Central Processing Unit (CPU) Complex, the Platform Control Hub (PCH), and the Network Accelerator Complex (NAC).

The CPU Complex contains up to 24 next-generation 64-bit Intel Atom processor cores (code name Tremont). The PCH is architected with a rich set of interconnect technologies. The NAC includes technologies for security and packet processing. The SoC architecture is highly scalable and efficient, providing a unified solution across an array of products.

Features[edit]

  • Up to 24 Intel Atom processor cores (code name Tremont) at up to 2.2 GHz
  • Mid-Level Cache (MLC) and Last Level Cache (LLC), including memory and cache
  • Quality of Service (QoS):
• 4.5 MB of MLC per four-core cluster, for a total of 27 MB for 6 clusters
• 2.5 MB of LLC per tile, for a total of 15 MB for 6 tiles
  • Integrated Memory Controller (IMC) that provides up to two 72-bit DDR4 interfaces (64-bit data + 8-bit Error Correcting Code (ECC)) and operating up to 2933 MT/s
  • Network Accelerator Complex (NAC) with high performance, programmable, packet-processing acceleration technology, including:
• Network Interface and Scheduler (NIS, code name Columbia Park), with nine levels of hierarchical scheduling
• Flexible Packet Processor and Switch (FPPS, code name Highland Park (SKU dependent)), leveraging high-performance cut-through architecture
• Intel QuickAssist Technology (Intel QAT) v1.8 (SKU dependent), which performs security and compression acceleration

Intel Atom Lines[edit]

See also: Intel Atom, Intel, Core, and intel/cpuid
Intel AtomRoadmap
Fabri-
cation
process
Micro-
archi-
tecture
Release
date
Processors / SoCs
Mobile Tablet Netbook Nettop Embedded Server CE
10 nm Tremont 2020 Lakefield
(hybrid)
Lakefield (hybrid)
Elkhart Lake
Jasper Lake
Jacobsville platform:
Parker Ridge
Snow Ridge
Intel 7 nm Gracemont 2021 Alder Lake (hybrid)
Alder Lake S (N/P/M)
Raptor Lake (S) (hybrid)
Tanner Ridge
Intel 7 nm Crestmont 2023 Meteor Lake (hybrid) Grand Ridge
TSMC N6
6 nm
Intel 3 nm 2024 Sierra Forest
TSMC
N3B
Skymont 2024 Lunar Lake (hybrid)
Arrow Lake (hybrid)
Twin Lake (E-cores, BGA)
Intel 18A Darkmont 2025 Clearwater Forest
codenameSnow Ridge +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/snow ridge +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameSnow Ridge +
process10 nm (0.01 μm, 1.0e-5 mm) +