Semiconductor & Computer Engineering
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Difference between revisions of "intel"
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| | | | ||
* {{intel|3000}} | * {{intel|3000}} | ||
| + | * {{intel|8086}} | ||
* {{intel|80186}} | * {{intel|80186}} | ||
* {{intel|80188}} | * {{intel|80188}} | ||
| Line 41: | Line 42: | ||
* {{intel|80386}} | * {{intel|80386}} | ||
* {{intel|80486}} | * {{intel|80486}} | ||
| − | * {{intel|Atom}} | + | |
| + | * {{intel|MCS-4}} | ||
| + | * {{intel|MCS-40}} | ||
| + | * {{intel|MCS-48}} | ||
| + | * {{intel|MCS-8}} | ||
| + | * {{intel|MCS-80}} | ||
| + | * {{intel|MCS-85}} | ||
| + | * {{intel|MCS-86}} | ||
| + | * {{intel|MCS-88}} | ||
| + | * {{intel|MCS-96}} | ||
| + | * {{intel|MCS-51}} | ||
| + | * {{intel|MCS-151}} | ||
| + | * {{intel|MCS-251}} | ||
| + | |||
| + | * {{intel|EP80579}} | ||
| + | * {{intel|iAPX432}} | ||
| + | * {{intel|i860}} | ||
| + | * {{intel|i960}} | ||
| + | |||
| + | * '''{{intel|Atom}}''' | ||
* {{intel|Atom x3}} | * {{intel|Atom x3}} | ||
* {{intel|Atom x5}} | * {{intel|Atom x5}} | ||
* {{intel|Atom x7}} | * {{intel|Atom x7}} | ||
| − | * {{intel|Celeron}} | + | |
| + | * '''{{intel|Celeron}}''' | ||
| + | * {{intel|Celeron Dual Core}} | ||
* {{intel|Celeron D}} | * {{intel|Celeron D}} | ||
* {{intel|Celeron M}} | * {{intel|Celeron M}} | ||
| + | |||
| + | * '''{{intel|Core}}''' | ||
| + | * {{intel|Core M}} • {{intel|Core X|X}} | ||
| + | * {{intel|Core Solo}} | ||
| + | * {{intel|Core Duo}} | ||
| + | * {{intel|Core 2 Solo}} | ||
* {{intel|Core 2 Duo}} | * {{intel|Core 2 Duo}} | ||
| + | * {{intel|Core 2 Quad}} <!--(Extreme)--> | ||
* {{intel|Core 2 Extreme}} | * {{intel|Core 2 Extreme}} | ||
| − | |||
| − | |||
| − | |||
| − | |||
* {{intel|Core i3}} | * {{intel|Core i3}} | ||
* {{intel|Core i5}} | * {{intel|Core i5}} | ||
| − | * {{intel|Core i7}} | + | * {{intel|Core i7}} ({{intel|Core i7 EE|EE}}) |
| − | |||
* {{intel|Core i9}} | * {{intel|Core i9}} | ||
| − | * {{intel|Core | + | * {{intel|Core Ultra}} |
| − | * {{intel|Core | + | * {{intel|Core Ultra 3}} |
| − | * {{intel| | + | * {{intel|Core Ultra 5}} |
| − | * {{intel| | + | * {{intel|Core Ultra 7}} |
| − | + | ||
| − | * {{intel| | + | * '''{{intel|Quark}}''' |
* {{intel|Itanium}} | * {{intel|Itanium}} | ||
* {{intel|Itanium 2}} | * {{intel|Itanium 2}} | ||
| − | * {{intel| | + | * {{intel|XScale}} (PXA) |
| − | + | ||
| − | + | * '''{{intel|Pentium}}''' | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | * {{intel|Pentium}} | ||
* {{intel|Pentium (2009)}} | * {{intel|Pentium (2009)}} | ||
| − | * {{intel|Pentium | + | * {{intel|Pentium Gold}} |
| − | * {{intel|Pentium | + | * {{intel|Pentium Silver}} |
| − | |||
* {{intel|Pentium D}} | * {{intel|Pentium D}} | ||
* {{intel|Pentium EE}} | * {{intel|Pentium EE}} | ||
| − | * {{intel|Pentium | + | * {{intel|Pentium M}} |
| + | * {{intel|Pentium MMX}} | ||
| + | * {{intel|Pentium Pro}} | ||
* {{intel|Pentium II}} | * {{intel|Pentium II}} | ||
| + | * {{intel|Mobile Pentium II|Pentium II Mobile}} | ||
| + | * {{intel|Pentium II Xeon}} | ||
* {{intel|Pentium III}} | * {{intel|Pentium III}} | ||
* {{intel|Pentium III Mobile}} | * {{intel|Pentium III Mobile}} | ||
* {{intel|Pentium III Xeon}} | * {{intel|Pentium III Xeon}} | ||
| − | * {{intel|Pentium | + | * {{intel|Pentium 4}} (-M/EE) <!-- |
| − | * {{intel|Pentium | + | * {{intel|Pentium 4 EE}} |
| − | * {{intel|Pentium M}} | + | * {{intel|Pentium 4-M}} --> |
| − | + | ||
| − | + | * '''{{intel|Xeon}}''' | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | * {{intel|Xeon | ||
* {{intel|Xeon D}} | * {{intel|Xeon D}} | ||
* {{intel|Xeon E}} | * {{intel|Xeon E}} | ||
| Line 105: | Line 118: | ||
* {{intel|Xeon E5}} | * {{intel|Xeon E5}} | ||
* {{intel|Xeon E7}} | * {{intel|Xeon E7}} | ||
| + | * {{intel|Xeon Bronze}} | ||
| + | * {{intel|Xeon Silver}} | ||
* {{intel|Xeon Gold}} | * {{intel|Xeon Gold}} | ||
* {{intel|Xeon Platinum}} | * {{intel|Xeon Platinum}} | ||
| − | * {{intel|Xeon | + | * {{intel|Xeon Scalable}} |
| − | * {{intel|Xeon W}} | + | * {{intel|Xeon W}} • {{intel|Xeon Phi}} |
}} | }} | ||
| + | <!-- | ||
| + | :• Intel • 3000 • 8088 • 80186 • 80188 • 80286 • 80386 • 80486 • 80860 • 80960 | ||
| + | :• MCS-4 • MCS-40 • MCS-8 • MCS-48 • MCS-80 • MCS-85 • MCS-86 • MCS-88 • MCS-96 • MCS-51 • MCS-151 • MCS-251 | ||
| + | :• iAPX 432 • iFX730 • iFX740 • iFX780 • iFX8160 • iPLD22 • iPLD610 • iPLD910 • H-EPLD | ||
| + | :• Atom • Atom x3 • Atom x5 • Atom x7 | ||
| + | :• Celeron • Celeron D • Celeron M | ||
| + | :• Core M • Core Solo • Core Duo • Core 2 Duo • Core i3 • Core i5 • Core i7 | ||
| + | :• Itanium • Itanium 2 • Quark • Timna • XScale | ||
| + | :• Pentium • Pentium D • Pentium M • Pentium EE • Pentium II • Pentium III • Pentium 4 | ||
| + | :• Xeon • Xeon D • Xeon E3 • Xeon E5 • Xeon E7 • Xeon Phi | ||
| + | --> | ||
== List of architectures == | == List of architectures == | ||
| Line 130: | Line 156: | ||
* {{intel|80386|l=arch}} | * {{intel|80386|l=arch}} | ||
* {{intel|80486|l=arch}} | * {{intel|80486|l=arch}} | ||
| + | |||
* {{intel|P5|l=arch}} | * {{intel|P5|l=arch}} | ||
* {{intel|P6|l=arch}} | * {{intel|P6|l=arch}} | ||
| Line 135: | Line 162: | ||
* {{intel|Enhanced NetBurst|l=arch}} | * {{intel|Enhanced NetBurst|l=arch}} | ||
}} | }} | ||
| − | |||
{{collist | {{collist | ||
| Line 146: | Line 172: | ||
* {{intel|Nehalem (client)|l=arch}} | * {{intel|Nehalem (client)|l=arch}} | ||
* {{intel|Westmere (client)|l=arch}} | * {{intel|Westmere (client)|l=arch}} | ||
| + | |||
* {{intel|Sandy Bridge (client)|l=arch}} | * {{intel|Sandy Bridge (client)|l=arch}} | ||
* {{intel|Ivy Bridge (client)|l=arch}} | * {{intel|Ivy Bridge (client)|l=arch}} | ||
* {{intel|Haswell (client)|l=arch}} | * {{intel|Haswell (client)|l=arch}} | ||
* {{intel|Broadwell (client)|l=arch}} | * {{intel|Broadwell (client)|l=arch}} | ||
| + | |||
* {{intel|Skylake (client)|l=arch}} | * {{intel|Skylake (client)|l=arch}} | ||
* {{intel|Kaby Lake|l=arch}} | * {{intel|Kaby Lake|l=arch}} | ||
* {{intel|Coffee Lake|l=arch}} | * {{intel|Coffee Lake|l=arch}} | ||
* {{intel|Whiskey Lake|l=arch}} | * {{intel|Whiskey Lake|l=arch}} | ||
| + | |||
* {{intel|Amber Lake|l=arch}} | * {{intel|Amber Lake|l=arch}} | ||
* {{intel|Comet Lake|l=arch}} | * {{intel|Comet Lake|l=arch}} | ||
* {{intel|Keystone Lake|l=arch}} | * {{intel|Keystone Lake|l=arch}} | ||
* {{intel|Rocket Lake|l=arch}} | * {{intel|Rocket Lake|l=arch}} | ||
| + | |||
* {{intel|Cannon Lake|l=arch}} ("Skymont") | * {{intel|Cannon Lake|l=arch}} ("Skymont") | ||
* {{intel|Ice Lake (client)|l=arch}} | * {{intel|Ice Lake (client)|l=arch}} | ||
* {{intel|Tiger Lake|l=arch}} | * {{intel|Tiger Lake|l=arch}} | ||
* {{intel|Alder Lake|l=arch}} | * {{intel|Alder Lake|l=arch}} | ||
| + | |||
| + | * {{intel|Raptor Lake|l=arch}} | ||
* {{intel|Meteor Lake|l=arch}} | * {{intel|Meteor Lake|l=arch}} | ||
| + | |||
| + | * {{intel|Lunar Lake|l=arch}} | ||
| + | * {{intel|Arrow Lake|l=arch}} | ||
| + | * {{intel|Panther Lake|l=arch}} | ||
| + | * {{intel|Nova Lake|l=arch}} | ||
}} | }} | ||
| − | |||
{{collist | {{collist | ||
| Line 171: | Line 207: | ||
| | | | ||
'''Server SoC:''' | '''Server SoC:''' | ||
| − | * {{intel|Core (server)|l=arch}} | + | * {{intel|Core|Core (server)|l=arch}} |
| − | * {{intel|Penryn (server)|l=arch}} | + | * {{intel|Penryn|Penryn (server)|l=arch}} |
| − | * {{intel|Nehalem (server)|l=arch}} | + | * {{intel|Nehalem|Nehalem (server)|l=arch}} |
| − | * {{intel|Westmere (server)|l=arch}} | + | * {{intel|Westmere|Westmere (server)|l=arch}} |
| − | * {{intel|Sandy Bridge (server)|l=arch}} | + | |
| − | * {{intel|Ivy Bridge (server)|l=arch}} | + | * {{intel|Sandy Bridge|Sandy Bridge (server)|l=arch}} |
| − | * {{intel|Haswell (server)|l=arch}} | + | * {{intel|Ivy Bridge|Ivy Bridge (server)|l=arch}} |
| − | * {{intel|Broadwell (server)|l=arch}} | + | * {{intel|Haswell|Haswell (server)|l=arch}} |
| + | * {{intel|Broadwell|Broadwell (server)|l=arch}} | ||
| + | |||
* {{intel|Skylake (server)|l=arch}} | * {{intel|Skylake (server)|l=arch}} | ||
* {{intel|Cascade Lake|l=arch}} | * {{intel|Cascade Lake|l=arch}} | ||
* {{intel|Cooper Lake|l=arch}} | * {{intel|Cooper Lake|l=arch}} | ||
* {{intel|Ice Lake (server)|l=arch}} | * {{intel|Ice Lake (server)|l=arch}} | ||
| + | |||
* {{intel|Sapphire Rapids|l=arch}} | * {{intel|Sapphire Rapids|l=arch}} | ||
| + | * {{intel|Emerald Rapids|l=arch}} | ||
* {{intel|Granite Rapids|l=arch}} | * {{intel|Granite Rapids|l=arch}} | ||
* {{intel|Diamond Rapids|l=arch}} | * {{intel|Diamond Rapids|l=arch}} | ||
| + | }} | ||
| + | |||
| + | {{collist | ||
| + | | count = 2 | ||
| + | | style= margin-left: 20px; | ||
| + | | | ||
| + | '''High-Efficiency (Small Cores) Server SoC:''' | ||
| + | * {{intel|Sierra Forest|Sierra Forest (server)|l=arch}} | ||
| + | * {{intel|Clearwater Forest|Clearwater Forest (server)|l=arch}} | ||
}} | }} | ||
{{collist | {{collist | ||
| − | | count = | + | | count = 2 |
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| Line 207: | Line 256: | ||
* {{intel|Sunny Cove|l=arch}} | * {{intel|Sunny Cove|l=arch}} | ||
* {{intel|Willow Cove|l=arch}} | * {{intel|Willow Cove|l=arch}} | ||
| + | * {{intel|Cypress Cove|l=arch}} | ||
| + | |||
* {{intel|Golden Cove|l=arch}} | * {{intel|Golden Cove|l=arch}} | ||
| + | * {{intel|Raptor Cove|l=arch}} | ||
| + | * {{intel|Redwood Cove|l=arch}} | ||
| + | * {{intel|Lion Cove|l=arch}} | ||
| + | |||
| + | * {{intel|Cougar Cove|l=arch}} | ||
| + | * {{intel|Coyote Cove|l=arch}} | ||
* {{intel|Ocean Cove|l=arch}} | * {{intel|Ocean Cove|l=arch}} | ||
}} | }} | ||
| Line 217: | Line 274: | ||
| | | | ||
'''High-Efficiency (Small Cores)''' | '''High-Efficiency (Small Cores)''' | ||
| − | * {{intel|Bonnell|l=arch}} | + | * {{intel|Bonnell|l=arch}} ([[Bonnell]]) |
| − | * {{intel|Saltwell|l=arch}} | + | * {{intel|Saltwell|l=arch}} ([[Saltwell]]) |
| − | * {{intel|Silvermont|l=arch}} | + | * {{intel|Silvermont|l=arch}} ([[Silvermont]]) |
| − | * {{intel|Airmont|l=arch}} | + | * {{intel|Airmont|l=arch}} ([[Airmont]]) |
| − | * {{intel|Goldmont|l=arch}} | + | |
| + | * {{intel|Goldmont|l=arch}} ([[Goldmont]]) | ||
* {{intel|Goldmont Plus|l=arch}} | * {{intel|Goldmont Plus|l=arch}} | ||
| − | * {{intel|Tremont|l=arch}} | + | * {{intel|Tremont|l=arch}} ([[Tremont]]) |
| + | * {{intel|Gracemont|l=arch}} ([[Gracemont]]) | ||
| + | |||
| + | * {{intel|Crestmont|l=arch}} ([[Crestmont]]) | ||
| + | * {{intel|Skymont|l=arch}} ([[Skymont]]) | ||
| + | * {{intel|Darkmont|l=arch}} ([[Darkmont]]) | ||
}} | }} | ||
| Line 230: | Line 293: | ||
| count = 1 | | count = 1 | ||
| | | | ||
| − | * {{intel|Lakemont|l=arch}} | + | * {{intel|Lakemont|l=arch}} ([[Lakemont]]) |
}} | }} | ||
| + | |||
| + | |||
'''ULP ([[ARM]]):''' | '''ULP ([[ARM]]):''' | ||
| Line 244: | Line 309: | ||
* Continued by [[Marvell]] .. | * Continued by [[Marvell]] .. | ||
}} | }} | ||
| − | |||
'''Server (EPIC) ([[Itanium]]):''' | '''Server (EPIC) ([[Itanium]]):''' | ||
| Line 254: | Line 318: | ||
* {{intel|Madison|l=arch}} | * {{intel|Madison|l=arch}} | ||
* {{intel|Deerfield|l=arch}} | * {{intel|Deerfield|l=arch}} | ||
| + | |||
* {{intel|Hondo|l=arch}} | * {{intel|Hondo|l=arch}} | ||
* {{intel|Madison 9M|l=arch}} | * {{intel|Madison 9M|l=arch}} | ||
* {{intel|Fanwood|l=arch}} | * {{intel|Fanwood|l=arch}} | ||
* {{intel|Montecito|l=arch}} | * {{intel|Montecito|l=arch}} | ||
| + | |||
* {{intel|Chivano|l=arch}} | * {{intel|Chivano|l=arch}} | ||
* {{intel|Millington|l=arch}} | * {{intel|Millington|l=arch}} | ||
* {{intel|Montvale|l=arch}} | * {{intel|Montvale|l=arch}} | ||
* {{intel|Tukwila|l=arch}} | * {{intel|Tukwila|l=arch}} | ||
| + | |||
* {{intel|Dimona|l=arch}} | * {{intel|Dimona|l=arch}} | ||
* {{intel|Poulson|l=arch}} | * {{intel|Poulson|l=arch}} | ||
* {{intel|Kittson|l=arch}} | * {{intel|Kittson|l=arch}} | ||
}} | }} | ||
| + | |||
'''[[Many-core]]:''' | '''[[Many-core]]:''' | ||
{{collist | {{collist | ||
| − | | count = | + | | count = 3 |
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| Line 277: | Line 345: | ||
}} | }} | ||
{{clear}} | {{clear}} | ||
| + | |||
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
| Line 285: | Line 354: | ||
* {{intel|Knights Corner|l=arch}} (Angel Isle) | * {{intel|Knights Corner|l=arch}} (Angel Isle) | ||
* {{intel|Knights Landing|l=arch}} | * {{intel|Knights Landing|l=arch}} | ||
| + | |||
* {{intel|Knights Mill|l=arch}} | * {{intel|Knights Mill|l=arch}} | ||
* {{intel|Knights Hill|l=arch}} | * {{intel|Knights Hill|l=arch}} | ||
* {{intel|Knights Peak|l=arch}} | * {{intel|Knights Peak|l=arch}} | ||
}} | }} | ||
| + | |||
'''Heterogeneous:''' | '''Heterogeneous:''' | ||
{{collist | {{collist | ||
| − | | count = | + | | count = 2 |
| | | | ||
* {{intel|Lakefield|l=arch}} | * {{intel|Lakefield|l=arch}} | ||
* {{intel|Ryefield|l=arch}} | * {{intel|Ryefield|l=arch}} | ||
}} | }} | ||
| − | |||
'''GPU:''' | '''GPU:''' | ||
{{collist | {{collist | ||
| − | | count = | + | | count = 4 |
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| Line 308: | Line 378: | ||
* {{intel|Gen3|l=arch}} | * {{intel|Gen3|l=arch}} | ||
* {{intel|Gen3.5|l=arch}} | * {{intel|Gen3.5|l=arch}} | ||
| + | |||
* {{intel|Gen4|l=arch}} | * {{intel|Gen4|l=arch}} | ||
* {{intel|Gen5|l=arch}} | * {{intel|Gen5|l=arch}} | ||
* {{intel|Gen5.75|l=arch}} ("Ironlake") | * {{intel|Gen5.75|l=arch}} ("Ironlake") | ||
* {{intel|Gen6|l=arch}} | * {{intel|Gen6|l=arch}} | ||
| + | |||
* {{intel|Gen7|l=arch}} | * {{intel|Gen7|l=arch}} | ||
* {{intel|Gen7.5|l=arch}} | * {{intel|Gen7.5|l=arch}} | ||
* {{intel|Gen8|l=arch}} | * {{intel|Gen8|l=arch}} | ||
* {{intel|Gen9|l=arch}} | * {{intel|Gen9|l=arch}} | ||
| + | |||
* {{intel|Gen9.5|l=arch}} | * {{intel|Gen9.5|l=arch}} | ||
* {{intel|Gen10|l=arch}} | * {{intel|Gen10|l=arch}} | ||
| Line 322: | Line 395: | ||
}} | }} | ||
{{clear}} | {{clear}} | ||
| + | |||
{{collist | {{collist | ||
| − | | count = | + | | count = 2 |
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| Line 333: | Line 407: | ||
'''Artificial Intelligence:''' | '''Artificial Intelligence:''' | ||
{{collist | {{collist | ||
| − | | count = | + | | count = 2 |
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| Line 342: | Line 416: | ||
{{clear}} | {{clear}} | ||
{{collist | {{collist | ||
| − | | count = | + | | count = 1 |
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| Line 348: | Line 422: | ||
* {{intel|Spring Hill|l=arch}} | * {{intel|Spring Hill|l=arch}} | ||
}} | }} | ||
| + | |||
| + | == [[Integrated Graphics Processor]]s == | ||
| + | |||
| + | === Family === | ||
| + | {| border="0" cellpadding="5" width="100%" | ||
| + | |- | ||
| + | |width="50%" valign="top" align="left"| | ||
| + | *'''{{intel|HD Graphics (Ironlake)|HD Graphics}}''' - Intel + (integrated graphics processor family) | ||
| + | *{{intel|HD Graphics 510}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|HD Graphics 515}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|HD Graphics 520}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|HD Graphics 530}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|HD Graphics P530}} - Intel + (integrated graphics processor) | ||
| + | |||
| + | *{{intel|HD Graphics 610}} - Intel + (integrated graphics processor family) | ||
| + | *{{intel|HD Graphics 615}} - Intel + (integrated graphics processor family) | ||
| + | *{{intel|HD Graphics 620}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|HD Graphics 630}} - Intel + (integrated graphics processor family) | ||
| + | *{{intel|HD Graphics P630}} - Intel + (integrated graphics processor family) | ||
| + | |||
| + | *{{intel|UHD Graphics 600}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|UHD Graphics 605}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|UHD Graphics 620}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|UHD Graphics 630}} - Intel + (integrated graphics processor) | ||
| + | |||
| + | |width="50%" valign="top" align="left"| | ||
| + | *'''{{intel|Iris Graphics}}''' - Intel + (integrated graphics processor extended family) | ||
| + | *{{intel|Iris Graphics 540}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|Iris Graphics 550}} - Intel + (integrated graphics processor) | ||
| + | |||
| + | *'''{{intel|Iris Pro Graphics}}''' - Intel + (integrated graphics processor extended family) | ||
| + | *{{intel|Iris Pro Graphics P555}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|Iris Pro Graphics P580}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|Iris Pro Graphics 580}} - Intel + (integrated graphics processor) | ||
| + | *{{intel|Iris Pro Graphics 5200}} - Intel + (integrated graphics processor family) | ||
| + | *{{intel|Iris Pro Graphics 6200}} - Intel + (integrated graphics processor family) | ||
| + | |||
| + | *{{intel|Iris Plus Graphics 640}} - Intel + (integrated graphics processor family) | ||
| + | *{{intel|Iris Plus Graphics 650}} - Intel + (integrated graphics processor family) | ||
| + | |} | ||
== Other Chips == | == Other Chips == | ||
| Line 355: | Line 469: | ||
'''Neuromorphic:''' | '''Neuromorphic:''' | ||
* {{intel|Loihi}} | * {{intel|Loihi}} | ||
| + | * {{intel|Loihi 2}} | ||
'''Artificial Intelligence''' | '''Artificial Intelligence''' | ||
* {{intel|ETANN}} | * {{intel|ETANN}} | ||
Latest revision as of 19:05, 2 July 2025
| Intel | |||||||||
.svg){kind=logo}
| |||||||||
| Type | Public | ||||||||
| Founded | July 18, 1968 Mountain View, California | ||||||||
| Founder | Gordon Moore Robert Noyce Andrew Grove | ||||||||
| Headquarters | Santa Clara, California | ||||||||
| Website | http://www.intel.com | ||||||||
| |||||||||
.svg){kind=logo}
.svg)
Intel Corporation is an American semiconductor company. While most notably known for their development of microprocessors and x86, Intel also designs and manufactures other integrated circuits including flash memory, network interface controllers, GPUs, chipsets, motherboards, and computers.
In addition to x86, Intel used to also design and manufacture ARM-based chips as well as embed ARC-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
Contents
[hide]Subsidiaries[edit]
Find Chip[edit]
- By S-Spec
List of processor families[edit]
- Core
- Core M • X
- Core Solo
- Core Duo
- Core 2 Solo
- Core 2 Duo
- Core 2 Quad
- Core 2 Extreme
- Core i3
- Core i5
- Core i7 (EE)
- Core i9
- Core Ultra
- Core Ultra 3
- Core Ultra 5
- Core Ultra 7
List of architectures[edit]
List of microarchitectures[edit]
Mainstream (x86):
Client SoC:
- Cannon Lake ("Skymont")
- Ice Lake (client)
- Tiger Lake
- Alder Lake
Server SoC:
High-Efficiency (Small Cores) Server SoC:
Networking SoC:
High-Perf (Big Cores):
High-Efficiency (Small Cores)
MCU:
ULP (ARM):
Server (EPIC) (Itanium):
Early Research:
- Knights Ferry (Aubrey Isle)
- Knights Corner (Angel Isle)
- Knights Landing
Heterogeneous:
GPU:
Integrated:
Discrete:
Artificial Intelligence:
Training:
Inference:
Integrated Graphics Processors[edit]
Family[edit]
|
|
Other Chips[edit]
Neuromorphic:
Artificial Intelligence
Quantum:
RAM:
Architectural Concepts[edit]
Other[edit]
Other topics[edit]
Technologies[edit]
Packaging Technologies[edit]
Documents[edit]
See Documents.
Facts about "Intel"
| company type | public + |
| founded | July 18, 1968 + |
| founded location | Mountain View, California + |
| founder | Gordon Moore +, Robert Noyce + and Andrew Grove + |
| full page name | intel + |
| headquarters | Santa Clara, California + |
| instance of | semiconductor company + |
| name | Intel + |
| website | http://www.intel.com + |
| wikidata id | Q248 + |