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Intel actual large effort research into the area of [[many-core]] started after the February 2004 [[Intel Developer Forum]] following Pradeep Dubey famous keynote titled "The Era of Tera." Around the [[2004]]-[[2005]] Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the {{intel|Tera-scale Computing Research Program}} which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum. | Intel actual large effort research into the area of [[many-core]] started after the February 2004 [[Intel Developer Forum]] following Pradeep Dubey famous keynote titled "The Era of Tera." Around the [[2004]]-[[2005]] Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the {{intel|Tera-scale Computing Research Program}} which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum. | ||
| − | The first product to come directly from that project was {{intel|Polaris|l=arch}}, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a [[mesh topology]]. Fabricated on a [[65 nm process]], the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the | + | The first product to come directly from that project was {{intel|Polaris|l=arch}}, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a [[mesh topology]]. Fabricated on a [[65 nm process]], the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. [[3D IC|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustained performance. |
=== Larrabee === | === Larrabee === | ||
{{empty section}} | {{empty section}} | ||
Latest revision as of 19:59, 8 February 2022
Below is a list of Intel microarchitectures:
Contents
CPU Microarchitectures[edit]
... further results| Intel CPU Microarchitectures | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| General | Details | ||||||||||
| µarch | Introduction | Phase-out | Process | Cores | Pipeline | ||||||
| 80386 | 1984-03-01 | 1989-01-01 | 1,500 nm 1.5 μm 0.0015 mm | ||||||||
| 80486 | 1989-04-10 | 1995-01-01 | 1,000 nm 1 μm , 800 nm0.001 mm 0.8 μm , 600 nm8.0e-4 mm 0.6 μm 6.0e-4 mm | ||||||||
| P5 | 1993-04-01 | 1995-10-01 | 600 nm 0.6 μm 6.0e-4 mm | ||||||||
| P6 | 1995-10-01 | 2000-12-01 | 350 nm 0.35 μm , 250 nm3.5e-4 mm 0.25 μm 2.5e-4 mm | ||||||||
| NetBurst | 2000-11-20 | 2006-04-01 | 180 nm 0.18 μm 1.8e-4 mm | ||||||||
| Merced | 2001-06-01 | 180 nm 0.18 μm 1.8e-4 mm | 1 | ||||||||
| McKinley | 2002-07-08 | 180 nm 0.18 μm 1.8e-4 mm | 1, 2 | ||||||||
| Pentium M | 2003-01-01 | 2005-01-01 | 130 nm 0.13 μm , 90 nm1.3e-4 mm 0.09 μm 9.0e-5 mm | ||||||||
| Madison | 2003-06-30 | 130 nm 0.13 μm 1.3e-4 mm | 1 | ||||||||
| Madison 9M | 2004-11-08 | 130 nm 0.13 μm 1.3e-4 mm | 1 | ||||||||
| Modified Pentium M | 2006-01-01 | 2008-01-01 | 65 nm 0.065 μm 6.5e-5 mm | ||||||||
| Core | 2006-04-01 | 2009-05-01 | 65 nm 0.065 μm 6.5e-5 mm | ||||||||
| Montecito | 2006-07-18 | 90 nm 0.09 μm 9.0e-5 mm | 1, 2 | ||||||||
| Polaris | 2007-02-01 | 65 nm 0.065 μm 6.5e-5 mm | 80 | 9 | |||||||
| Montvale | 2007-10-31 | 90 nm 0.09 μm 9.0e-5 mm | 1, 2 | ||||||||
| Penryn | 2007-11-01 | 2008-09-01 | 45 nm 0.045 μm 4.5e-5 mm | ||||||||
| Bonnell | 2008-03-02 | 2011-01-01 | 45 nm 0.045 μm 4.5e-5 mm | 1, 2 | 16 | 19 | |||||
| Nehalem | 2008-08-01 | 2010-03-01 | 45 nm 0.045 μm 4.5e-5 mm | ||||||||
| Rock Creek | 2009-12-01 | 45 nm 0.045 μm 4.5e-5 mm | 48 | ||||||||
| Westmere | 2010-01-01 | 2011-08-01 | 32 nm 0.032 μm 3.2e-5 mm | ||||||||
| Tukwila | 2010-02-08 | 65 nm 0.065 μm 6.5e-5 mm | 1, 2 | ||||||||
| Knights Ferry | 2010-05-31 | 2011-01-01 | 45 nm 0.045 μm 4.5e-5 mm | 32 | |||||||
| Sandy Bridge (client) | 2010-09-13 | 2012-11-01 | 32 nm 0.032 μm 3.2e-5 mm | 2, 4 | 14 | 19 | |||||
| Saltwell | 2011-01-01 | 2013-01-01 | 32 nm 0.032 μm 3.2e-5 mm | 1, 2 | 16 | ||||||
| Knights Corner | 2011-01-01 | 2013-01-01 | 22 nm 0.022 μm 2.2e-5 mm | 57, 60, 61 | |||||||
| Ivy Bridge | 2011-05-04 | 2013-04-01 | 22 nm 0.022 μm 2.2e-5 mm | ||||||||
| Poulson | 2012-11-08 | 32 nm 0.032 μm 3.2e-5 mm | 1, 2 | ||||||||
| Silvermont | 2013-01-01 | 2015-01-01 | 22 nm 0.022 μm 2.2e-5 mm | 1, 2, 4, 8 | 12 | 14 | |||||
| Haswell | 2013-06-04 | 2015-01-01 | 22 nm 0.022 μm 2.2e-5 mm | 2, 4, 6, 8, 16, 10, 12, 14, 18 | 14 | 19 | |||||
| Broadwell | 2014-10-01 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22 | 14 | 19 | ||||||
| Airmont | 2015-01-01 | 2017-01-01 | 14 nm 0.014 μm 1.4e-5 mm | 1, 2, 4, 8 | 12 | 14 | |||||
| Skylake (client) | 2015-08-05 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4 | 14 | 19 | ||||||
| Kaby Lake | 2016-08-30 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4 | 14 | 19 | ||||||
| Goldmont | 2016-08-30 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4, 8, 12, 16 | 12 | 14 | ||||||
| Kittson | 2017-01-01 | 22 nm 0.022 μm 2.2e-5 mm | 1, 2 | ||||||||
| Skylake (server) | 2017-05-04 | 14 nm 0.014 μm 1.4e-5 mm | 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28 | 14 | 19 | ||||||
| Coffee Lake | 2017-10-05 | 14 nm 0.014 μm 1.4e-5 mm | 14 | 19 | |||||||
| Goldmont Plus | 2017-12-11 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4 | ||||||||
| Knights Mill | 2017-12-18 | 2019-08-09 | 14 nm 0.014 μm 1.4e-5 mm | ||||||||
| Palm Cove | 2018-01-01 | 10 nm 0.01 μm 1.0e-5 mm | 2 | 14 | 19 | ||||||
| Whiskey Lake | 2018-04-01 | 4 | 14 | 19 | |||||||
| Amber Lake | 2018-04-01 | 14 nm 0.014 μm 1.4e-5 mm | 2 | 14 | 19 | ||||||
| Cannon Lake | 2018-05-15 | 10 nm 0.01 μm 1.0e-5 mm | 2 | 14 | 19 | ||||||
| Tremont | 2019-01-01 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
| Snow Ridge | 2019-01-01 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
| Sunny Cove | 2019-01-01 | 2021-01-01 | 10 nm 0.01 μm 1.0e-5 mm | 2, 4, 8, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 40 | 14 | 19 | |||||
| Lakefield | 2019-01-01 | 22 nm 0.022 μm , 10 nm2.2e-5 mm 0.01 μm 1.0e-5 mm | 5 | ||||||||
| Cascade Lake | 2019-01-01 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4, 6, 8, 10, 12, 16, 18, 20, 22, 24, 26, 28, 32, 48, 56 | 14 | 19 | ||||||
| Ice Lake (client) | 2019-05-27 | 10 nm 0.01 μm 1.0e-5 mm | 2, 4 | 14 | 19 | ||||||
| Willow Cove | 2020-01-01 | 10 nm 0.01 μm 1.0e-5 mm | 2, 4, 6, 8 | 14 | 19 | ||||||
GPU Microarchitectures[edit]
| Intel GPU Microarchitectures | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| General | Details | ||||||||||
| µarch | Introduction | Phase-out | Process | ||||||||
| Gen1 | 1998-01-01 | ||||||||||
| Gen2 | 2002-01-01 | ||||||||||
| Gen3 | 2004-01-01 | ||||||||||
| Gen3.5 | 2005-01-01 | 90 nm 0.09 μm 9.0e-5 mm | |||||||||
| Gen4 | 2006-01-01 | 65 nm 0.065 μm 6.5e-5 mm | |||||||||
| Gen5 | 2008-06-03 | 45 nm 0.045 μm 4.5e-5 mm | |||||||||
| Larrabee | 2008-08-12 | 2010-01-01 | 32 nm 0.032 μm , 45 nm3.2e-5 mm 0.045 μm 4.5e-5 mm | ||||||||
| Gen5.75 | 2010-01-01 | 45 nm 0.045 μm 4.5e-5 mm | |||||||||
| Gen6 | 2010-09-13 | 32 nm 0.032 μm 3.2e-5 mm | |||||||||
| Gen7 | 2011-05-04 | 22 nm 0.022 μm 2.2e-5 mm | |||||||||
| Gen7.5 | 2013-06-04 | 22 nm 0.022 μm 2.2e-5 mm | |||||||||
| Gen8 | 2014-10-01 | 14 nm 0.014 μm 1.4e-5 mm | |||||||||
| Gen9 | 2015-08-05 | 14 nm 0.014 μm 1.4e-5 mm | |||||||||
| Gen9.5 | 2016-08-30 | 14 nm 0.014 μm 1.4e-5 mm | |||||||||
| Gen10 | 2018-01-01 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
| Gen11 | 2018-01-01 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
| Gen12 | 2020-01-01 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
| Arctic Sound | 2020-01-01 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
| Jupiter Sound | 2022-01-01 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
Many-core[edit]
This article is a work in progress!Initial effort & Polaris[edit]
Intel actual large effort research into the area of many-core started after the February 2004 Intel Developer Forum following Pradeep Dubey famous keynote titled "The Era of Tera." Around the 2004-2005 Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the Tera-scale Computing Research Program which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.
The first product to come directly from that project was Polaris, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a mesh topology. Fabricated on a 65 nm process, the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. 3D stacked SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 teraFLOPS of sustained performance.
Larrabee[edit]
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