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Difference between revisions of "arm holdings/cortex"
< arm holdings

(→‎Comparison)
(→‎Comparison)
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==== Comparison ====
 
==== Comparison ====
 
:;"LITTLE" core
 
:;"LITTLE" core
−
{| class="wikitable" style="text-align: center;
+
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
 
|-
 
|-
 
! [[Microarchitecture|µArch]]
 
! [[Microarchitecture|µArch]]
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|-
 
|-
 
! Codename
 
! Codename
−
| ''Apollo''
+
| ''{{armh|Apollo|l=arch}}''
−
| ''Ananke''
+
| ''{{armh|Ananke|l=arch}}''
−
| ''Klein''
+
| ''{{armh|Klein|l=arch}}''
 
| ''{{armh|Hayes|l=arch}}''
 
| ''{{armh|Hayes|l=arch}}''
 
| ''Nevis''
 
| ''Nevis''
Line 281: Line 281:
 
| 2.0&nbsp;GHz
 
| 2.0&nbsp;GHz
 
| 2.0&nbsp;GHz
 
| 2.0&nbsp;GHz
−
|
+
| -
 
|-
 
|-
 
! Architecture
 
! Architecture
Line 288: Line 288:
 
| [[ARMv9]].0-A
 
| [[ARMv9]].0-A
 
| [[ARMv9]].2-A
 
| [[ARMv9]].2-A
−
| [[ARMv9]].2-A
+
| [[ARMv9]].4-A
 
|-
 
|-
 
! '''AArch'''
 
! '''AArch'''
 
| colspan="3" | 32-bit and 64-bit
 
| colspan="3" | 32-bit and 64-bit
−
| 64-bit
+
| colspan="2" | 64-bit
−
|
 
 
|-
 
|-
 
! '''L1 (I + D)''' (KiB)
 
! '''L1 (I + D)''' (KiB)
Line 299: Line 298:
 
| 16/64 + 16/64 KiB
 
| 16/64 + 16/64 KiB
 
| colspan="2" | 32/64 + 32/64 KiB
 
| colspan="2" | 32/64 + 32/64 KiB
−
|
+
| -
 
|-
 
|-
 
! L2 Cache (KiB)
 
! L2 Cache (KiB)
 
| colspan="2" | 0–256 KiB
 
| colspan="2" | 0–256 KiB
 
| colspan="2" | 0–512 KiB
 
| colspan="2" | 0–512 KiB
−
|
+
| -
 
|-
 
|-
 
! L3 Cache (MiB)
 
! L3 Cache (MiB)
Line 311: Line 310:
 
| 0–16 MiB
 
| 0–16 MiB
 
| 0–32 MiB
 
| 0–32 MiB
−
|
+
| -
 
|-
 
|-
−
! Decode Width
+
! Decode width
−
| colspan="2" | 2
+
| colspan="2" | 2-way
−
| 3
+
| 3-way
−
| 3 (2 ALU)
+
| 3-way (2 ALU)
 
| -
 
| -
 
|-
 
|-
 
! Dispatch
 
! Dispatch
−
| colspan="2" | 8
+
| colspan="2" | 8 Mops/cycle
−
|
+
| -
−
|
+
| -
−
|
+
| -
 
|-
 
|-
 
|}
 
|}
  
 
:;"big" core
 
:;"big" core
−
{| class="wikitable" style="text-align: center;
+
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
 
|-
 
|-
 
! [[Microarchitecture|µArch]]
 
! [[Microarchitecture|µArch]]
Line 340: Line 339:
 
|-
 
|-
 
! Codename
 
! Codename
−
| ''Deimos''
+
| ''{{armh|Deimos|l=arch}}''
−
| ''Hercules''
+
| ''{{armh|Hercules|l=arch}}''
−
| ''Matterhorn''
+
| ''{{armh|Matterhorn|l=arch}}''
−
| ''Makalu''
+
| ''{{armh|Makalu|l=arch}}''
 
| ''{{armh|Hunter|l=arch}}''
 
| ''{{armh|Hunter|l=arch}}''
 
| ''{{armh|Chaberton|l=arch}}''
 
| ''{{armh|Chaberton|l=arch}}''
Line 349: Line 348:
 
|-
 
|-
 
! Peak clock speed
 
! Peak clock speed
−
|  
+
| 2.6&nbsp;GHz
 
| colspan="4" | ~3.0&nbsp;GHz
 
| colspan="4" | ~3.0&nbsp;GHz
−
|  
+
| -
−
|  
+
| -
 
|-
 
|-
 
! Architecture
 
! Architecture
Line 358: Line 357:
 
| colspan="2" | [[ARMv9]].0-A
 
| colspan="2" | [[ARMv9]].0-A
 
| colspan="2" | [[ARMv9]].2-A
 
| colspan="2" | [[ARMv9]].2-A
−
| -
+
| [[ARMv9]].4-A
 
|-
 
|-
 
! AArch
 
! AArch
−
|  
+
| -
 
| colspan="2" | 32-bit and 64-bit
 
| colspan="2" | 32-bit and 64-bit
 
| colspan="2" | 64-bit
 
| colspan="2" | 64-bit
−
| -
+
| colspan="2" | 64-bit
−
| -
 
 
|-
 
|-
 
! Max In-flight
 
! Max In-flight
−
| 160
+
| 2x 160
−
| 160
+
| 2x 160
 
| ?
 
| ?
−
| 192+ <ref>{{cite book |title=Arm introduces Cortex-A715 |url=https://fuse.wikichip.org/news/6853/arm-introduces-the-cortex-a715/ |website=WikiChip Fuse |date=2022-06-28}}</ref>
+
| 2x 192+ <ref>{{cite book |title=Arm introduces Cortex-A715 |url=https://fuse.wikichip.org/news/6853/arm-introduces-the-cortex-a715/ |website=WikiChip Fuse |date=2022-06-28}}</ref>
 
| ?  
 
| ?  
 
| -
 
| -
Line 377: Line 375:
 
|-
 
|-
 
! L0 (Mops entries)
 
! L0 (Mops entries)
−
|  
+
| -
 
| colspan="2" | 1536  
 
| colspan="2" | 1536  
 
| colspan="2" | 0
 
| colspan="2" | 0
Line 392: Line 390:
 
| 256–512 KiB
 
| 256–512 KiB
 
| colspan="4" | 128–512 KiB
 
| colspan="4" | 128–512 KiB
−
| 1 MiB <ref>{{cite book |title=Arm launches next gen big core Cortex-A725 |website=WikiChip Fuse |url=https://fuse.wikichip.org/news/7829/arm-launches-next-gen-big-core-cortex-a725/ |date=2024-05-29}}</ref><!-- From 32K/512K/8M L1/2/3 on the Cortex-A720 to 64K/1M/16M L1/2/3 on the new Cortex-A725 ? -->
+
| 0.25–1 MiB <ref>{{cite book |title=Arm launches next gen big core Cortex-A725 |website=WikiChip Fuse |url=https://fuse.wikichip.org/news/7829/arm-launches-next-gen-big-core-cortex-a725/ |date=2024-05-29}}</ref><!-- From 32K/512K/8M L1/2/3 on the Cortex-A720 to 64K/1M/16M L1/2/3 on the new Cortex-A725 ? -->
−
|  
+
| -
 
|-
 
|-
 
! L3 Cache (MiB)
 
! L3 Cache (MiB)
Line 399: Line 397:
 
| 0–8 MiB
 
| 0–8 MiB
 
| colspan="2" | 0–16 MiB
 
| colspan="2" | 0–16 MiB
−
| 0–32 MiB <ref>{{cite book |title=Arm introduces a new big core Cortex-A720 |website=WikiChip Fuse |url=https://fuse.wikichip.org/news/7529/arm-introduces-a-new-big-core-the-cortex-a720/ |date=2023-05-28}}</ref>
+
| colspan="2" | 0–32 MiB <ref>{{cite book |title=Arm introduces a new big core Cortex-A720 |website=WikiChip Fuse |url=https://fuse.wikichip.org/news/7529/arm-introduces-a-new-big-core-the-cortex-a720/ |date=2023-05-28}}</ref>
−
| 0–32 MiB
+
| -
−
|
 
 
|-
 
|-
 
! Decode width
 
! Decode width
−
| colspan="3" | 4
+
| colspan="3" | 4-way
−
| colspan="3" | 5
+
| colspan="3" | 5-way
 
| -
 
| -
 
|-
 
|-
 
! Dispatch
 
! Dispatch
 +
| colspan="2" | 6 Mops/cycle
 +
| colspan="2" | 5 Mops/cycle
 +
| ?
 +
| -
 
| -
 
| -
−
| 6/cycle
+
|-
−
| colspan="2" | 5/cycle
+
|}
−
| ?
+
 
 +
=== Cortex-X ===
 +
:;"Prime" core
 +
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
 +
|-
 +
! [[Microarchitecture|µArch]]
 +
! {{armh|Cortex-X1|l=arch}}(C)
 +
! {{armh|Cortex-X2|l=arch}}
 +
! {{armh|Cortex-X3|l=arch}}
 +
! {{armh|Cortex-X4|l=arch}}
 +
! <s>{{armh|Cortex-X5|l=arch}}</s>
 +
! {{armh|Cortex-X925|l=arch}}
 +
! {{armh|Cortex-X930|l=arch}}
 +
|-
 +
! Codename
 +
| ''{{armh|Hera|l=arch}}(-C)''
 +
| ''{{armh|Matterhorn-ELP|l=arch}}''
 +
| ''{{armh|Makalu-ELP|l=arch}}''
 +
| ''{{armh|Hunter-ELP|l=arch}}''
 +
| <s>''{{armh|Chaberton-ELP|l=arch}}''</s>
 +
| ''{{armh|Blackhawk|l=arch}}''
 +
| ''Travis'' /''Alto''
 +
|-
 +
! Peak clock speed
 +
| 3.0&nbsp;GHz
 +
| 3.0&nbsp;GHz
 +
| 3.3&nbsp;GHz
 +
| 3.4&nbsp;GHz
 +
| - -
 +
| 3.8&nbsp;GHz
 +
| 4.2&nbsp;GHz
 +
|-
 +
! Architecture
 +
| [[ARMv8]].2-A
 +
| colspan="2" | [[ARMv9]].0-A
 +
| colspan="3" | [[ARMv9]].2-A
 +
| [[ARMv9]].4-A
 +
|-
 +
! AArch
 +
| 32/64-bit
 +
| colspan="2" | 64-bit
 +
| colspan="2" | 64-bit
 +
| colspan="2" | 64-bit
 +
|-
 +
! Max in-flight
 +
| 2x 224 <ref>{{cite book |last=Schor |first=David |date=2020-05-26 |title=Arm Cortex-X1: The First From The Cortex-X Custom Program |url=https://fuse.wikichip.org/news/3543/arm-cortex-x1-the-first-from-the-cortex-x-custom-program/ |website=WikiChip Fuse}}</ref>
 +
| 2x 288
 +
| 2x 320
 +
| 2x 384
 +
| - -
 +
| 2x 768 <ref>https://www.androidauthority.com/arm-cortex-x925-g925-explained-3445480/</ref>
 +
| -
 +
|-
 +
! L0 (Mops entries)
 +
| colspan="2" | 3072 <ref>{{cite book |title=Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence |url=https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging |website=www.anandtech.com}}</ref>
 +
| 1536
 +
| 0 <ref>{{cite book |title=Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive |url=https://www.androidauthority.com/arm-cortex-x4-explained-3328008/ |website=Android Authority}}</ref>
 +
| - -
 +
| -
 +
| -
 +
|-
 +
! '''L1 (I + D)''' (KiB)
 +
| colspan="2" | 64 + 64 KiB
 +
| colspan="2" | 64 + 64 KiB
 +
| - -
 +
| 64 + 64 KiB
 +
| -
 +
|-
 +
! L2 Cache (KiB)
 +
| colspan="3" | 0.25–1 MiB
 +
| 0.5–2 MiB
 +
| - -
 +
| 2–3 MiB
 +
| -
 +
|-
 +
! L3 Cache (MiB)
 +
| 0–8 MiB
 +
| colspan="2" |0–16 MiB
 +
| colspan="3" |0–32 MiB
 +
| -
 +
|-
 +
! Decode width
 +
| colspan="2" | 5-way
 +
| 6-way
 +
| colspan="3" | 10-way
 
| -
 
| -
 +
|-
 +
! Dispatch
 +
| colspan="3" | 8 Mops/cycle
 +
| colspan="3" | 10 Mops/cycle
 
| -
 
| -
 
|-
 
|-
 
|}
 
|}
−
<pre>
 
−
+
 
−
</pre>
 
  
 
=== References ===
 
=== References ===

Revision as of 19:00, 12 April 2025

Logo

Cortex is a family of specialized ARM microarchitectures designed by Arm for various edge market such as embedded and mobile. The Cortex family succeed Arm's classic cores with more specialized cores with highly targeted requirements

Overview

Cortex is a family of ARM cores that address a broad set of markets. First announced in 2004, Cortex cores have replaced Arm's classic cores with more market-specific variations. Cortex can be broadly categorized into three types of workloads: Applications, Real-time, Microcontroller (A.R.M).

  • Cortex-A - Application processors. Designed for fully capable computers, running typical operating systems (Android, Windows, Linux, iOS). Those processors are found in anything from smartphones to tablets and laptops.
  • Cortex-X - Application processors. Slightly enhanced version of the Cortex-A designs in order to to further optimize the Cortex-A design (in terms of PPA) for certain markets or workloads/
  • Cortex-R - Real-time processors. Designed for real-time operating systems with very deterministic behavior. Those cores are typically less powerful than the A series and are used for things such as controllers, factory equipment, medical devices, and other machines.
  • Cortex-M - Microcontrollers. Designed for ultra-low power, typically small factor and low-performance systems. Those are found in cost-sensitive devices and electronics, automated systems, and many other embedded devices.

Cores

See also: arm/versions, neoverse, and zen

Cortex-A

Year Low-power Performance
2005 Cortex-A8 (Tiger)
2006
2007 Cortex-A9 (Falcon)
2008
Ultra-low power Mainstream-performance High-efficiency High-performance
2009 Cortex-A5 (Sparrow)
2010 Cortex-A15 (Eagle)
2011 Cortex-A7 (Kingfisher)
2012 Cortex-A53 (Apollo) Cortex-A57 (Atlas)
2013 Cortex-A12 (Owl)
2014 Cortex-A17 (Owl)
2015 Cortex-A35 (Mercury) Cortex-A72 (Maia)
2016 Cortex-A32 (Minerva) Cortex-A73 (Artemis)
2017 Cortex-A55 (Ananke) Cortex-A75 (Prometheus)
2018 Cortex-A65 (Helios)
Cortex-A65AE (Helios-SL) 		Cortex-A76 (Enyo)
Cortex-A76AE (Enyo-SL)
2019 Cortex-A34 (Metis) Cortex-A77 (Deimos)
2020 Cortex-A78 (Hercules)
Cortex-A78AE (Hercules-AE)
Cortex-A78C (Hera Prime)
2021 Cortex-A510 (Klein) Cortex-A710 (Matterhorn)
2022 Cortex-A715 (Makalu)
2023 Cortex-A520 (Hayes) Cortex-A720 (Hunter)
2024 Cortex-A520AE (Hayes-AE) Cortex-A720AE (Hunter-AE)
Cortex-A725 (Chaberton)
2025 Cortex-A320 (IoT & AI ) Cortex-A530 (Nevis) Cortex-A730 (Gelas)

Cortex-M

Year Core
2004 Cortex-M3 (Sandcat)
2005
2006
2007 Cortex-M1 (Proteus)
2008
2009 Cortex-M0 (Swift)
2010 Cortex-M4 (Merlin)
2011
2012 Cortex-M0+ (Flycatcher)
2013
2014 Cortex-M7 (Pelican)
2015
2016 Cortex-M23 (Grebe)
Cortex-M33 (Teal)
2017
2018 Cortex-M35P (Tahan)
2019
2020 Cortex-M55 (Yamin)
2021
2022 Cortex-M85 (Helium)
2023 Cortex-M52
2024
2025

Cortex-R

Year Core
2005
2006
2007
2008
2009
2010 Cortex-R4(F)
(Serval-E)
2011 Cortex-R5(F)
Cortex-R7(F)
2012
2013
2014
2015
2016 Cortex-R8(F)
Cortex-R52(F)
2017
2018
2019
2020 Cortex-R82(F) (64-bit)
2021
2022 Cortex-R52+(F)
2023
2024 Cortex-R82AE (64-bit)
2025

Cortex-X

Year Core
2020 Cortex-X1 (Hera)
Cortex-X1C (Hera-C)
2021 Cortex-X2
(Matterhorn-ELP)
2022 Cortex-X3 (Makalu-ELP)
2023 Cortex-X4 (Hunter-ELP)
2024 Cortex-X5 (Chaberton-ELP)
Cortex-X925 (Blackhawk)
2025 Cortex-X930 (Travis)

Neoverse

Year Core
2019 Neoverse E1 (Helios)
Neoverse N1 (Ares)
2020 Neoverse V1 (Zeus)
2021 Neoverse E2 (Genesis)
Neoverse N2 (Perseus)
2022 Neoverse V2 (Demeter)
2023 Neoverse E3 (Aphrodite)
Neoverse N3 (Hermes)
Neoverse V3 (Poseidon)
2024 Neoverse V3AE
Neoverse VN
2025 Neoverse E4 (Lycius)
Neoverse N4 (Dionysus)
Neoverse V4 (Adonis)

Specifications

Cortex-A

Year µArch ISA Decoder Out-of-order
execution buffer 		ALU/FPU/LSU L1 Cache (KiB)
I (Instruction) + D (Data) 		Performance
(per clock)
Little Core target
2014 Cortex-A53 ARMv8.0-A 2-wide unsupported 2/1/1 8/64 + 8/64 82
2017 Cortex-A55 ARMv8.2-A 2-wide unsupported 2/2/2 16/64 + 16/64 89
2021 Cortex-A510 ARMv9.0-A 3-wide unsupported 3/2*/2 32/64 + 32/64 -
2023 Cortex-A520 ARMv9.2-A 3-wide unsupported 2/2*/2 32/64 + 32/64 -
2025 Cortex-A530 ARMv9.2-A 3-wide unsupported // + -
Big/Middle Core target
2014 Cortex-A57 ARMv8.0-A 3-wide 128 2/2/2 48 + 32 127
2015 Cortex-A72 ARMv8.0-A 3-wide 128 2/2/2 48 + 32 147
2016 Cortex-A73 ARMv8.0-A 2-wide 128 2/2/2 64 + 32 157
2017 Cortex-A75 ARMv8.2-A 3-wide 128 2/3/2 64 + 64 177
2018 Cortex-A76 ARMv8.2-A 4-wide 128 3/2/2 64 + 64 265
2019 Cortex-A77 ARMv8.2-A 4-wide 160 4/2/2 64 + 64 306
2020 Cortex-A78 ARMv8.2-A 4-wide 160 4/2/3 32/64 + 32/64 325
2021 Cortex-A710 ARMv9.0-A 4-wide - // 32/64 + 32/64 -
2022 Cortex-A715 ARMv9.0-A 5-wide 192 // 32/64 + 32/64 -
2023 Cortex-A720 ARMv9.2-A 5-wide - // 32/64 + 32/64 -
2024 Cortex-A725 ARMv9.2-A 5-wide - // 32/64 + 32/64 -
2025 Cortex-A730 ARMv9.2-A 5-wide - // + -

Comparison

"LITTLE" core
µArch Cortex-A53 Cortex-A55 Cortex-A510 Cortex-A520 Cortex-A530
Codename Apollo Ananke Klein Hayes Nevis
Peak clock speed 2.3 GHz 2.1 GHz 2.0 GHz 2.0 GHz -
Architecture ARMv8.0-A ARMv8.2-A ARMv9.0-A ARMv9.2-A ARMv9.4-A
AArch 32-bit and 64-bit 64-bit
L1 (I + D) (KiB) 8/64 + 8/64 KiB 16/64 + 16/64 KiB 32/64 + 32/64 KiB -
L2 Cache (KiB) 0–256 KiB 0–512 KiB -
L3 Cache (MiB) - 0–4 MiB 0–16 MiB 0–32 MiB -
Decode width 2-way 3-way 3-way (2 ALU) -
Dispatch 8 Mops/cycle - - -
"big" core
µArch Cortex-A77 Cortex-A78 Cortex-A710 Cortex-A715 Cortex-A720 Cortex-A725 Cortex-A730
Codename Deimos Hercules Matterhorn Makalu Hunter Chaberton Gelas
Peak clock speed 2.6 GHz ~3.0 GHz - -
Architecture ARMv8.2-A ARMv9.0-A ARMv9.2-A ARMv9.4-A
AArch - 32-bit and 64-bit 64-bit 64-bit
Max In-flight 2x 160 2x 160  ? 2x 192+ [1]  ? - -
L0 (Mops entries) - 1536 0 - -
L1 (I + D) (KiB) 64 + 64 KiB 32/64 + 32/64 KiB 64 + 64 KiB -
L2 Cache (KiB) 256–512 KiB 128–512 KiB 0.25–1 MiB [2] -
L3 Cache (MiB) 0–4 MiB 0–8 MiB 0–16 MiB 0–32 MiB [3] -
Decode width 4-way 5-way -
Dispatch 6 Mops/cycle 5 Mops/cycle  ? - -

Cortex-X

"Prime" core
µArch Cortex-X1(C) Cortex-X2 Cortex-X3 Cortex-X4 Cortex-X5 Cortex-X925 Cortex-X930
Codename Hera(-C) Matterhorn-ELP Makalu-ELP Hunter-ELP Chaberton-ELP Blackhawk Travis /Alto
Peak clock speed 3.0 GHz 3.0 GHz 3.3 GHz 3.4 GHz - - 3.8 GHz 4.2 GHz
Architecture ARMv8.2-A ARMv9.0-A ARMv9.2-A ARMv9.4-A
AArch 32/64-bit 64-bit 64-bit 64-bit
Max in-flight 2x 224 [4] 2x 288 2x 320 2x 384 - - 2x 768 [5] -
L0 (Mops entries) 3072 [6] 1536 0 [7] - - - -
L1 (I + D) (KiB) 64 + 64 KiB 64 + 64 KiB - - 64 + 64 KiB -
L2 Cache (KiB) 0.25–1 MiB 0.5–2 MiB - - 2–3 MiB -
L3 Cache (MiB) 0–8 MiB 0–16 MiB 0–32 MiB -
Decode width 5-way 6-way 10-way -
Dispatch 8 Mops/cycle 10 Mops/cycle -

References

See also

  • ↑ (2022-06-28) Arm introduces Cortex-A715.
  • ↑ (2024-05-29) Arm launches next gen big core Cortex-A725.
  • ↑ (2023-05-28) Arm introduces a new big core Cortex-A720.
  • ↑ Schor, David (2020-05-26). Arm Cortex-X1: The First From The Cortex-X Custom Program.
  • ↑ https://www.androidauthority.com/arm-cortex-x925-g925-explained-3445480/
  • ↑ Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence.
  • ↑ Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive.
    • Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/cortex&oldid=103206"