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== Cores ==
 
== Cores ==
 
{{see also|arm/versions|neoverse|zen}}
 
{{see also|arm/versions|neoverse|zen}}
−
 
 
=== Cortex-A ===
 
=== Cortex-A ===
 
{| class="wikitable" style="text-align: center;
 
{| class="wikitable" style="text-align: center;
Line 20: Line 19:
 
| [[2005]] || colspan="4" | {{armh|Cortex-A8|l=arch}} (''{{armh|Tiger|l=arch}}'')
 
| [[2005]] || colspan="4" | {{armh|Cortex-A8|l=arch}} (''{{armh|Tiger|l=arch}}'')
 
|-
 
|-
−
| [[2006]] ||  
+
| [[2006]] || colspan="4" |  
 
|-
 
|-
 
| [[2007]] || colspan="4" | {{armh|Cortex-A9|l=arch}} (''{{armh|Falcon|l=arch}}'')
 
| [[2007]] || colspan="4" | {{armh|Cortex-A9|l=arch}} (''{{armh|Falcon|l=arch}}'')
 
|-
 
|-
−
| [[2008]] ||  
+
| [[2008]] || colspan="4" |  
 
|-
 
|-
 
! !! Ultra-low power !! Mainstream-performance !! High-efficiency !! High-performance
 
! !! Ultra-low power !! Mainstream-performance !! High-efficiency !! High-performance
Line 60: Line 59:
 
| [[2024]] || || || {{armh|Cortex-A520AE|l=arch}} (''{{armh|Hayes-AE|l=arch}}'') || {{armh|Cortex-A720AE|l=arch}} (''{{armh|Hunter-AE|l=arch}}'') <br>{{armh|Cortex-A725|l=arch}} (''{{armh|Chaberton|l=arch}}'') <!-- big.Mid.LITTLE with Logan and Hayes or as big.LITTLE • https://fuse.wikichip.org/wp-content/uploads/2024/05/arm-client-cores-roadmap-2025.png -->
 
| [[2024]] || || || {{armh|Cortex-A520AE|l=arch}} (''{{armh|Hayes-AE|l=arch}}'') || {{armh|Cortex-A720AE|l=arch}} (''{{armh|Hunter-AE|l=arch}}'') <br>{{armh|Cortex-A725|l=arch}} (''{{armh|Chaberton|l=arch}}'') <!-- big.Mid.LITTLE with Logan and Hayes or as big.LITTLE • https://fuse.wikichip.org/wp-content/uploads/2024/05/arm-client-cores-roadmap-2025.png -->
 
|-
 
|-
−
| [[2025]] || {{armh|Cortex-A320|l=arch}} (''IoT & AI'') || || {{armh|Cortex-A530|l=arch}} (''{{armh|Nevis|l=arch}}'') || {{armh|Cortex-A730|l=arch}} (''{{armh|Gelas|l=arch}}'')
+
| [[2025]] || {{armh|Cortex-A320|l=arch}} (''IoT & AI'' ) || || {{armh|Cortex-A530|l=arch}} (''{{armh|Nevis|l=arch}}'') || {{armh|Cortex-A730|l=arch}} (''{{armh|Gelas|l=arch}}'')
 
|-
 
|-
 
|}
 
|}
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{| class="wikitable" style="text-align: center;
 
{| class="wikitable" style="text-align: center;
 
|-
 
|-
−
! Year !! Core
+
! Year !! Core  
 +
|-
 +
| [[2005]] ||
 +
|-
 +
| [[2006]] ||
 +
|-
 +
| [[2007]] ||
 +
|-
 +
| [[2008]] ||
 +
|-
 +
| [[2009]] ||
 +
|-
 +
| [[2010]] || {{armh|Cortex-R4|l=arch}}(F) <br>(''{{armh|Serval-E|l=arch}}'')
 
|-
 
|-
−
| [[2011]] || {{armh|Cortex-R4|l=arch}} (''{{armh|Serval-E|l=arch}}'') <br>{{armh|Cortex-R5|l=arch}} <br>{{armh|Cortex-R7|l=arch}}
+
| [[2011]] || {{armh|Cortex-R5|l=arch}}(F) <br>{{armh|Cortex-R7|l=arch}}(F)
 
|-
 
|-
 
| [[2012]] ||  
 
| [[2012]] ||  
Line 133: Line 144:
 
| [[2015]] ||  
 
| [[2015]] ||  
 
|-
 
|-
−
| [[2016]] || {{armh|Cortex-R8|l=arch}} <br>{{armh|Cortex-R52|l=arch}}
+
| [[2016]] || {{armh|Cortex-R8|l=arch}}(F) <br>{{armh|Cortex-R52|l=arch}}(F)
 
|-
 
|-
 
| [[2017]] ||  
 
| [[2017]] ||  
Line 141: Line 152:
 
| [[2019]] ||  
 
| [[2019]] ||  
 
|-
 
|-
−
| [[2020]] || {{armh|Cortex-R82|l=arch}}
+
| [[2020]] || {{armh|Cortex-R82|l=arch}}(F) (64-bit)
 
|-
 
|-
 
| [[2021]] ||  
 
| [[2021]] ||  
 
|-
 
|-
−
| [[2022]] || {{armh|Cortex-R52+|l=arch}}
+
| [[2022]] || {{armh|Cortex-R52+|l=arch}}(F)
 
|-
 
|-
 
| [[2023]] ||  
 
| [[2023]] ||  
 
|-
 
|-
−
| [[2024]] || {{armh|Cortex-R82AE|l=arch}}
+
| [[2024]] || {{armh|Cortex-R82AE|l=arch}} (64-bit)
 
|-
 
|-
 
| [[2025]] ||  
 
| [[2025]] ||  
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=== [[Neoverse]] ===
 
=== [[Neoverse]] ===
 
{| class="wikitable" style="text-align: center;
 
{| class="wikitable" style="text-align: center;
−
|-
+
|- <!--
 
| [[2015]] || {{armh|Cosmos|l=arch}} ([[Cortex]])  
 
| [[2015]] || {{armh|Cosmos|l=arch}} ([[Cortex]])  
−
|-
+
|- -->
 
! Year !! Core
 
! Year !! Core
 
|-
 
|-
Line 198: Line 209:
 
|}
 
|}
 
|}
 
|}
 +
 +
== Specifications ==
 +
*[https://en.namu.wiki/w/ARM%20Cortex-A%20시리즈#s-1 Spec.]
 +
 +
=== Cortex-A ===
 +
{| class="wikitable" style="text-align: center;
 +
|-
 +
! Year !! [[Microarchitecture|µArch]] !! {{arm|Versions|ISA}} !! Decoder !! Out-of-order <br>execution buffer !! ALU/FPU/LSU !! L1 Cache (KiB)<br>I (Instruction) + D (Data) || Performance<br>(per clock)
 +
|-
 +
! colspan="8" | Little Core target
 +
|-
 +
| [[2014]] || {{armh|Cortex-A53|l=arch}} || [[ARMv8]].0-A || 2-wide || unsupported || 2/1/1 || 8/64 + 8/64 || 82
 +
|-
 +
| [[2017]] || {{armh|Cortex-A55|l=arch}} || [[ARMv8]].2-A || 2-wide || unsupported || 2/2/2 || 16/64 + 16/64 || 89
 +
|-
 +
| [[2021]] || {{armh|Cortex-A510|l=arch}} || [[ARMv9]].0-A || 3-wide || unsupported || 3/2*/2 || 32/64 + 32/64 || -
 +
|-
 +
| [[2023]] || {{armh|Hayes|Cortex-A520|l=arch}} || [[ARMv9]].2-A || 3-wide || unsupported || 2/2*/2 || 32/64 + 32/64 || -
 +
|-
 +
| [[2025]] || {{armh|Cortex-A530|l=arch}} || [[ARMv9]].2-A || 3-wide || unsupported || // || + || -
 +
|-
 +
! colspan="8" | Big/Middle Core target
 +
|-
 +
| [[2014]] || {{armh|Cortex-A57|l=arch}} || [[ARMv8]].0-A || 3-wide || 128 || 2/2/2 || 48 + 32 || 127
 +
|-
 +
| [[2015]] || {{armh|Cortex-A72|l=arch}} || [[ARMv8]].0-A || 3-wide || 128 || 2/2/2 || 48 + 32 || 147
 +
|-
 +
| [[2016]] || {{armh|Cortex-A73|l=arch}} || [[ARMv8]].0-A || 2-wide || 128 || 2/2/2 || 64 + 32 || 157
 +
|-
 +
| [[2017]] || {{armh|Cortex-A75|l=arch}} || [[ARMv8]].2-A || 3-wide || 128 || 2/3/2 || 64 + 64 || 177
 +
|-
 +
| [[2018]] || {{armh|Cortex-A76|l=arch}} || [[ARMv8]].2-A || 4-wide || 128 || 3/2/2 || 64 + 64 || 265
 +
|-
 +
| [[2019]] || {{armh|Cortex-A77|l=arch}} || [[ARMv8]].2-A || 4-wide || 160 || 4/2/2 || 64 + 64 || 306
 +
|-
 +
| [[2020]] || {{armh|Cortex-A78|l=arch}} || [[ARMv8]].2-A || 4-wide || 160 || 4/2/3 || 32/64 + 32/64 || 325
 +
|-
 +
| [[2021]] || {{armh|Cortex-A710|l=arch}} || [[ARMv9]].0-A || 4-wide || - || // || 32/64 + 32/64 || -
 +
|-
 +
| [[2022]] || {{armh|Cortex-A715|l=arch}} || [[ARMv9]].0-A || 5-wide || 192 || // || 32/64 + 32/64 || -
 +
|-
 +
| [[2023]] || {{armh|Hunter|Cortex-A720|l=arch}} || [[ARMv9]].2-A || 5-wide || - || // || 32/64 + 32/64 || -
 +
|-
 +
| [[2024]] || {{armh|Chaberton|Cortex-A725|l=arch}} || [[ARMv9]].2-A || 5-wide || - || // || 32/64 + 32/64 || -
 +
|-
 +
| [[2025]] || {{armh|Cortex-A730|l=arch}} || [[ARMv9]].2-A || 5-wide || - || // || + || -
 +
|-
 +
|}
 +
 +
==== Comparison ====
 +
:;"LITTLE" core
 +
{| class="wikitable" style="text-align: center;
 +
|-
 +
! [[Microarchitecture|µArch]]
 +
! {{armh|Cortex-A53|l=arch}}
 +
! {{armh|Cortex-A55|l=arch}}
 +
! {{armh|Cortex-A510|l=arch}}
 +
! {{armh|Cortex-A520|l=arch}}
 +
! {{armh|Cortex-A530|l=arch}}
 +
|-
 +
! Codename
 +
| ''Apollo''
 +
| ''Ananke''
 +
| ''Klein''
 +
| ''{{armh|Hayes|l=arch}}''
 +
| ''Nevis''
 +
|-
 +
! Peak clock speed
 +
| 2.3&nbsp;GHz
 +
| 2.1&nbsp;GHz
 +
| 2.0&nbsp;GHz
 +
| 2.0&nbsp;GHz
 +
|
 +
|-
 +
! Architecture
 +
| [[ARMv8]].0-A
 +
| [[ARMv8]].2-A
 +
| [[ARMv9]].0-A
 +
| [[ARMv9]].2-A
 +
| [[ARMv9]].2-A
 +
|-
 +
! '''AArch'''
 +
| colspan="3" | 32-bit and 64-bit
 +
| 64-bit
 +
|
 +
|-
 +
! '''L1 (I + D)''' (KiB)
 +
| 8/64 + 8/64 KiB
 +
| 16/64 + 16/64 KiB
 +
| colspan="2" | 32/64 + 32/64 KiB
 +
|
 +
|-
 +
! L2 Cache (KiB)
 +
| colspan="2" | 0–256 KiB
 +
| colspan="2" | 0–512 KiB
 +
|
 +
|-
 +
! L3 Cache (MiB)
 +
| -
 +
| 0–4 MiB
 +
| 0–16 MiB
 +
| 0–32 MiB
 +
|
 +
|-
 +
! Decode Width
 +
| colspan="2" | 2
 +
| 3
 +
| 3 (2 ALU)
 +
| -
 +
|-
 +
! Dispatch
 +
| colspan="2" | 8
 +
|
 +
|
 +
|
 +
|-
 +
|}
 +
 +
:;"big" core
 +
{| class="wikitable" style="text-align: center;
 +
|-
 +
! [[Microarchitecture|µArch]]
 +
! {{armh|Cortex-A77|l=arch}}
 +
! {{armh|Cortex-A78|l=arch}}
 +
! {{armh|Cortex-A710|l=arch}}
 +
! {{armh|Cortex-A715|l=arch}}
 +
! {{armh|Cortex-A720|l=arch}}
 +
! {{armh|Cortex-A725|l=arch}}
 +
! {{armh|Cortex-A730|l=arch}}
 +
|-
 +
! Codename
 +
| ''Deimos''
 +
| ''Hercules''
 +
| ''Matterhorn''
 +
| ''Makalu''
 +
| ''{{armh|Hunter|l=arch}}''
 +
| ''{{armh|Chaberton|l=arch}}''
 +
| ''Gelas''
 +
|-
 +
! Peak clock speed
 +
|
 +
| colspan="4" | ~3.0&nbsp;GHz
 +
|
 +
|
 +
|-
 +
! Architecture
 +
| colspan="2" | [[ARMv8]].2-A
 +
| colspan="2" | [[ARMv9]].0-A
 +
| colspan="2" | [[ARMv9]].2-A
 +
| -
 +
|-
 +
! AArch
 +
|
 +
| colspan="2" | 32-bit and 64-bit
 +
| colspan="2" | 64-bit
 +
| -
 +
| -
 +
|-
 +
! Max In-flight
 +
| 160
 +
| 160
 +
| ?
 +
| 192+ <ref>{{cite book |title=Arm introduces Cortex-A715 |url=https://fuse.wikichip.org/news/6853/arm-introduces-the-cortex-a715/ |website=WikiChip Fuse |date=2022-06-28}}</ref>
 +
| ?
 +
| -
 +
| -
 +
|-
 +
! L0 (Mops entries)
 +
|
 +
| colspan="2" | 1536
 +
| colspan="2" | 0
 +
| -
 +
| -
 +
|-
 +
! '''L1 (I + D)''' (KiB)
 +
| 64 + 64 KiB
 +
| colspan="4" | 32/64 + 32/64 KiB
 +
| 64 + 64 KiB
 +
| -
 +
|-
 +
! L2 Cache (KiB)
 +
| 256–512 KiB
 +
| colspan="4" | 128–512 KiB
 +
| 1 MiB <ref>{{cite book |title=Arm launches next gen big core Cortex-A725 |website=WikiChip Fuse |url=https://fuse.wikichip.org/news/7829/arm-launches-next-gen-big-core-cortex-a725/ |date=2024-05-29}}</ref><!-- From 32K/512K/8M L1/2/3 on the Cortex-A720 to 64K/1M/16M L1/2/3 on the new Cortex-A725 ? -->
 +
|
 +
|-
 +
! L3 Cache (MiB)
 +
| 0–4 MiB
 +
| 0–8 MiB
 +
| colspan="2" | 0–16 MiB
 +
| 0–32 MiB <ref>{{cite book |title=Arm introduces a new big core Cortex-A720 |website=WikiChip Fuse |url=https://fuse.wikichip.org/news/7529/arm-introduces-a-new-big-core-the-cortex-a720/ |date=2023-05-28}}</ref>
 +
| 0–32 MiB
 +
|
 +
|-
 +
! Decode width
 +
| colspan="3" | 4
 +
| colspan="3" | 5
 +
| -
 +
|-
 +
! Dispatch
 +
| -
 +
| 6/cycle
 +
| colspan="2" | 5/cycle
 +
| ?
 +
| -
 +
| -
 +
|-
 +
|}
 +
<pre>
 +
+
 +
</pre>
 +
 +
=== References ===
  
 
== See also ==
 
== See also ==
−
* ARM {{arm|Versions}}
+
* [[ARM]] {{arm|Versions}}
 
* {{\\|Neoverse}}
 
* {{\\|Neoverse}}
 +
 
[[category:arm holdings]]
 
[[category:arm holdings]]

Latest revision as of 06:58, 23 March 2025

Logo

Cortex is a family of specialized ARM microarchitectures designed by Arm for various edge market such as embedded and mobile. The Cortex family succeed Arm's classic cores with more specialized cores with highly targeted requirements

Overview[edit]

Cortex is a family of ARM cores that address a broad set of markets. First announced in 2004, Cortex cores have replaced Arm's classic cores with more market-specific variations. Cortex can be broadly categorized into three types of workloads: Applications, Real-time, Microcontroller (A.R.M).

  • Cortex-A - Application processors. Designed for fully capable computers, running typical operating systems (Android, Windows, Linux, iOS). Those processors are found in anything from smartphones to tablets and laptops.
  • Cortex-X - Application processors. Slightly enhanced version of the Cortex-A designs in order to to further optimize the Cortex-A design (in terms of PPA) for certain markets or workloads/
  • Cortex-R - Real-time processors. Designed for real-time operating systems with very deterministic behavior. Those cores are typically less powerful than the A series and are used for things such as controllers, factory equipment, medical devices, and other machines.
  • Cortex-M - Microcontrollers. Designed for ultra-low power, typically small factor and low-performance systems. Those are found in cost-sensitive devices and electronics, automated systems, and many other embedded devices.

Cores[edit]

See also: arm/versions, neoverse, and zen

Cortex-A[edit]

Year Low-power Performance
2005 Cortex-A8 (Tiger)
2006
2007 Cortex-A9 (Falcon)
2008
Ultra-low power Mainstream-performance High-efficiency High-performance
2009 Cortex-A5 (Sparrow)
2010 Cortex-A15 (Eagle)
2011 Cortex-A7 (Kingfisher)
2012 Cortex-A53 (Apollo) Cortex-A57 (Atlas)
2013 Cortex-A12 (Owl)
2014 Cortex-A17 (Owl)
2015 Cortex-A35 (Mercury) Cortex-A72 (Maia)
2016 Cortex-A32 (Minerva) Cortex-A73 (Artemis)
2017 Cortex-A55 (Ananke) Cortex-A75 (Prometheus)
2018 Cortex-A65 (Helios)
Cortex-A65AE (Helios-SL) 		Cortex-A76 (Enyo)
Cortex-A76AE (Enyo-SL)
2019 Cortex-A34 (Metis) Cortex-A77 (Deimos)
2020 Cortex-A78 (Hercules)
Cortex-A78AE (Hercules-AE)
Cortex-A78C (Hera Prime)
2021 Cortex-A510 (Klein) Cortex-A710 (Matterhorn)
2022 Cortex-A715 (Makalu)
2023 Cortex-A520 (Hayes) Cortex-A720 (Hunter)
2024 Cortex-A520AE (Hayes-AE) Cortex-A720AE (Hunter-AE)
Cortex-A725 (Chaberton)
2025 Cortex-A320 (IoT & AI ) Cortex-A530 (Nevis) Cortex-A730 (Gelas)

Cortex-M[edit]

Year Core
2004 Cortex-M3 (Sandcat)
2005
2006
2007 Cortex-M1 (Proteus)
2008
2009 Cortex-M0 (Swift)
2010 Cortex-M4 (Merlin)
2011
2012 Cortex-M0+ (Flycatcher)
2013
2014 Cortex-M7 (Pelican)
2015
2016 Cortex-M23 (Grebe)
Cortex-M33 (Teal)
2017
2018 Cortex-M35P (Tahan)
2019
2020 Cortex-M55 (Yamin)
2021
2022 Cortex-M85 (Helium)
2023 Cortex-M52
2024
2025

Cortex-R[edit]

Year Core
2005
2006
2007
2008
2009
2010 Cortex-R4(F)
(Serval-E)
2011 Cortex-R5(F)
Cortex-R7(F)
2012
2013
2014
2015
2016 Cortex-R8(F)
Cortex-R52(F)
2017
2018
2019
2020 Cortex-R82(F) (64-bit)
2021
2022 Cortex-R52+(F)
2023
2024 Cortex-R82AE (64-bit)
2025

Cortex-X[edit]

Year Core
2020 Cortex-X1 (Hera)
Cortex-X1C (Hera-C)
2021 Cortex-X2
(Matterhorn-ELP)
2022 Cortex-X3 (Makalu-ELP)
2023 Cortex-X4 (Hunter-ELP)
2024 Cortex-X5 (Chaberton-ELP)
Cortex-X925 (Blackhawk)
2025 Cortex-X930 (Travis)

Neoverse[edit]

Year Core
2019 Neoverse E1 (Helios)
Neoverse N1 (Ares)
2020 Neoverse V1 (Zeus)
2021 Neoverse E2 (Genesis)
Neoverse N2 (Perseus)
2022 Neoverse V2 (Demeter)
2023 Neoverse E3 (Aphrodite)
Neoverse N3 (Hermes)
Neoverse V3 (Poseidon)
2024 Neoverse V3AE
Neoverse VN
2025 Neoverse E4 (Lycius)
Neoverse N4 (Dionysus)
Neoverse V4 (Adonis)

Specifications[edit]

Cortex-A[edit]

Year µArch ISA Decoder Out-of-order
execution buffer 		ALU/FPU/LSU L1 Cache (KiB)
I (Instruction) + D (Data) 		Performance
(per clock)
Little Core target
2014 Cortex-A53 ARMv8.0-A 2-wide unsupported 2/1/1 8/64 + 8/64 82
2017 Cortex-A55 ARMv8.2-A 2-wide unsupported 2/2/2 16/64 + 16/64 89
2021 Cortex-A510 ARMv9.0-A 3-wide unsupported 3/2*/2 32/64 + 32/64 -
2023 Cortex-A520 ARMv9.2-A 3-wide unsupported 2/2*/2 32/64 + 32/64 -
2025 Cortex-A530 ARMv9.2-A 3-wide unsupported // + -
Big/Middle Core target
2014 Cortex-A57 ARMv8.0-A 3-wide 128 2/2/2 48 + 32 127
2015 Cortex-A72 ARMv8.0-A 3-wide 128 2/2/2 48 + 32 147
2016 Cortex-A73 ARMv8.0-A 2-wide 128 2/2/2 64 + 32 157
2017 Cortex-A75 ARMv8.2-A 3-wide 128 2/3/2 64 + 64 177
2018 Cortex-A76 ARMv8.2-A 4-wide 128 3/2/2 64 + 64 265
2019 Cortex-A77 ARMv8.2-A 4-wide 160 4/2/2 64 + 64 306
2020 Cortex-A78 ARMv8.2-A 4-wide 160 4/2/3 32/64 + 32/64 325
2021 Cortex-A710 ARMv9.0-A 4-wide - // 32/64 + 32/64 -
2022 Cortex-A715 ARMv9.0-A 5-wide 192 // 32/64 + 32/64 -
2023 Cortex-A720 ARMv9.2-A 5-wide - // 32/64 + 32/64 -
2024 Cortex-A725 ARMv9.2-A 5-wide - // 32/64 + 32/64 -
2025 Cortex-A730 ARMv9.2-A 5-wide - // + -

Comparison[edit]

"LITTLE" core
µArch Cortex-A53 Cortex-A55 Cortex-A510 Cortex-A520 Cortex-A530
Codename Apollo Ananke Klein Hayes Nevis
Peak clock speed 2.3 GHz 2.1 GHz 2.0 GHz 2.0 GHz
Architecture ARMv8.0-A ARMv8.2-A ARMv9.0-A ARMv9.2-A ARMv9.2-A
AArch 32-bit and 64-bit 64-bit
L1 (I + D) (KiB) 8/64 + 8/64 KiB 16/64 + 16/64 KiB 32/64 + 32/64 KiB
L2 Cache (KiB) 0–256 KiB 0–512 KiB
L3 Cache (MiB) - 0–4 MiB 0–16 MiB 0–32 MiB
Decode Width 2 3 3 (2 ALU) -
Dispatch 8
"big" core
µArch Cortex-A77 Cortex-A78 Cortex-A710 Cortex-A715 Cortex-A720 Cortex-A725 Cortex-A730
Codename Deimos Hercules Matterhorn Makalu Hunter Chaberton Gelas
Peak clock speed ~3.0 GHz
Architecture ARMv8.2-A ARMv9.0-A ARMv9.2-A -
AArch 32-bit and 64-bit 64-bit - -
Max In-flight 160 160  ? 192+ [1]  ? - -
L0 (Mops entries) 1536 0 - -
L1 (I + D) (KiB) 64 + 64 KiB 32/64 + 32/64 KiB 64 + 64 KiB -
L2 Cache (KiB) 256–512 KiB 128–512 KiB 1 MiB [2]
L3 Cache (MiB) 0–4 MiB 0–8 MiB 0–16 MiB 0–32 MiB [3] 0–32 MiB
Decode width 4 5 -
Dispatch - 6/cycle 5/cycle  ? - - 
+

References[edit]

See also[edit]

  • ↑ (2022-06-28) Arm introduces Cortex-A715.
  • ↑ (2024-05-29) Arm launches next gen big core Cortex-A725.
  • ↑ (2023-05-28) Arm introduces a new big core Cortex-A720.
    • Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/cortex&oldid=103043"