From WikiChip
Difference between revisions of "intel"

 
(31 intermediate revisions by 8 users not shown)
Line 20: Line 20:
  
 
In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
 
In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
 +
 +
== Subsidiaries ==
 +
* [[Barefoot Networks]]
 +
* [[Movidius]]
 +
* [[Nervana]]
 +
* [[Mobileye]]
  
 
== Find Chip ==
 
== Find Chip ==
Line 55: Line 61:
 
* {{intel|Core M}}
 
* {{intel|Core M}}
 
* {{intel|Core Solo}}
 
* {{intel|Core Solo}}
 +
* {{intel|Core Ultra}}
 
* {{intel|EP80579}}
 
* {{intel|EP80579}}
 
* {{intel|i860}}
 
* {{intel|i860}}
Line 105: Line 112:
 
}}
 
}}
  
−
== List of instruction set architectures ==
+
== List of architectures ==
 
{{collist
 
{{collist
 
| count = 1
 
| count = 1
 
|
 
|
−
* {{intel|MCS-8/ISA|MCS-8 (8008)}}
+
* {{\\|MCS-8/ISA|MCS-8 (8008)}}
 +
* [[x86]]
 +
* {{\\|Configurable Spatial Accelerator}} (CSA)
 +
* {{\\|Programmable Unified Memory Architecture}} (PUMA)
 
}}
 
}}
  
Line 126: Line 136:
 
* {{intel|Enhanced NetBurst|l=arch}}
 
* {{intel|Enhanced NetBurst|l=arch}}
 
}}
 
}}
 +
  
 
{{collist
 
{{collist
Line 131: Line 142:
 
| style= margin-left: 20px;
 
| style= margin-left: 20px;
 
|
 
|
−
'''Client:'''
+
'''Client SoC:'''
 
* {{intel|Core (client)|l=arch}}
 
* {{intel|Core (client)|l=arch}}
 
* {{intel|Penryn (client)|l=arch}}
 
* {{intel|Penryn (client)|l=arch}}
Line 144: Line 155:
 
* {{intel|Coffee Lake|l=arch}}
 
* {{intel|Coffee Lake|l=arch}}
 
* {{intel|Whiskey Lake|l=arch}}
 
* {{intel|Whiskey Lake|l=arch}}
 +
* {{intel|Amber Lake|l=arch}}
 +
* {{intel|Comet Lake|l=arch}}
 +
* {{intel|Keystone Lake|l=arch}}
 +
* {{intel|Rocket Lake|l=arch}}
 
* {{intel|Cannon Lake|l=arch}} ("Skymont")
 
* {{intel|Cannon Lake|l=arch}} ("Skymont")
 
* {{intel|Ice Lake (client)|l=arch}}
 
* {{intel|Ice Lake (client)|l=arch}}
 
* {{intel|Tiger Lake|l=arch}}
 
* {{intel|Tiger Lake|l=arch}}
 
* {{intel|Alder Lake|l=arch}}
 
* {{intel|Alder Lake|l=arch}}
 +
* {{intel|Raptor Lake|l=arch}}
 
* {{intel|Meteor Lake|l=arch}}
 
* {{intel|Meteor Lake|l=arch}}
 +
* {{intel|Arrow Lake|l=arch}}
 +
* {{intel|Lunar Lake|l=arch}}
 +
 
}}
 
}}
 +
  
 
{{collist
 
{{collist
Line 155: Line 175:
 
| style= margin-left: 20px;
 
| style= margin-left: 20px;
 
|
 
|
−
'''Server:'''
+
'''Server SoC:'''
 
* {{intel|Core (server)|l=arch}}
 
* {{intel|Core (server)|l=arch}}
 
* {{intel|Penryn (server)|l=arch}}
 
* {{intel|Penryn (server)|l=arch}}
Line 166: Line 186:
 
* {{intel|Skylake (server)|l=arch}}
 
* {{intel|Skylake (server)|l=arch}}
 
* {{intel|Cascade Lake|l=arch}}
 
* {{intel|Cascade Lake|l=arch}}
 +
* {{intel|Cooper Lake|l=arch}}
 
* {{intel|Ice Lake (server)|l=arch}}
 
* {{intel|Ice Lake (server)|l=arch}}
 
* {{intel|Sapphire Rapids|l=arch}}
 
* {{intel|Sapphire Rapids|l=arch}}
 +
* {{intel|Emerald Rapids|l=arch}}
 
* {{intel|Granite Rapids|l=arch}}
 
* {{intel|Granite Rapids|l=arch}}
 +
* {{intel|Diamond Rapids|l=arch}}
 +
}}
 +
 +
 +
{{collist
 +
| count = 4
 +
| style= margin-left: 20px;
 +
|
 +
'''Networking SoC:'''
 +
* {{intel|Snow Ridge|l=arch}}
 +
* {{intel|Tanner Ridge|l=arch}}
 
}}
 
}}
  
−
'''ULP ([[x86]]):'''
+
 
 
{{collist
 
{{collist
−
| count = 2
+
| count = 4
 +
| style= margin-left: 20px;
 +
|
 +
'''High-Perf (Big Cores):'''
 +
* {{intel|Palm Cove|l=arch}}
 +
* {{intel|Sunny Cove|l=arch}}
 +
* {{intel|Willow Cove|l=arch}}
 +
* {{intel|Golden Cove|l=arch}}
 +
* {{intel|Ocean Cove|l=arch}}
 +
}}
 +
 
 +
 
 +
{{collist
 +
| count = 4
 +
| style= margin-left: 20px;
 
|
 
|
 +
'''High-Efficiency (Small Cores)'''
 
* {{intel|Bonnell|l=arch}}
 
* {{intel|Bonnell|l=arch}}
 
* {{intel|Saltwell|l=arch}}
 
* {{intel|Saltwell|l=arch}}
Line 183: Line 231:
 
* {{intel|Tremont|l=arch}}
 
* {{intel|Tremont|l=arch}}
 
}}
 
}}
 +
 
'''MCU:'''
 
'''MCU:'''
 
{{collist
 
{{collist
Line 189: Line 238:
 
* {{intel|Lakemont|l=arch}}
 
* {{intel|Lakemont|l=arch}}
 
}}
 
}}
 +
 
'''ULP ([[ARM]]):'''
 
'''ULP ([[ARM]]):'''
 
{{collist
 
{{collist
Line 200: Line 250:
 
* Continued by [[Marvell]] ..
 
* Continued by [[Marvell]] ..
 
}}
 
}}
 +
 +
 
'''Server (EPIC) ([[Itanium]]):'''
 
'''Server (EPIC) ([[Itanium]]):'''
 
{{collist
 
{{collist
Line 237: Line 289:
 
'''{{intel|MIC Architectures}}:'''
 
'''{{intel|MIC Architectures}}:'''
 
* {{intel|Knights Ferry|l=arch}} (Aubrey Isle)
 
* {{intel|Knights Ferry|l=arch}} (Aubrey Isle)
−
* {{intel|Knights Corner|l=arch}}
+
* {{intel|Knights Corner|l=arch}} (Angel Isle)
 
* {{intel|Knights Landing|l=arch}}
 
* {{intel|Knights Landing|l=arch}}
 
* {{intel|Knights Mill|l=arch}}
 
* {{intel|Knights Mill|l=arch}}
Line 248: Line 300:
 
|
 
|
 
* {{intel|Lakefield|l=arch}}
 
* {{intel|Lakefield|l=arch}}
 +
* {{intel|Ryefield|l=arch}}
 
}}
 
}}
  
Line 280: Line 333:
 
|
 
|
 
'''Discrete:'''
 
'''Discrete:'''
−
* {{intel|Artic Sound|l=arch}}
+
* {{intel|Arctic Sound|l=arch}}
 
* {{intel|Jupiter Sound|l=arch}}
 
* {{intel|Jupiter Sound|l=arch}}
 +
}}
 +
 +
'''Artificial Intelligence:'''
 +
{{collist
 +
| count = 3
 +
| style= margin-left: 20px;
 +
|
 +
'''Training:'''
 +
* {{intel|Lake Crest|l=arch}}
 +
* {{intel|Spring Crest|l=arch}}
 +
}}
 +
{{clear}}
 +
{{collist
 +
| count = 3
 +
| style= margin-left: 20px;
 +
|
 +
'''Inference:'''
 +
* {{intel|Spring Hill|l=arch}}
 
}}
 
}}
  
Line 290: Line 361:
 
'''Neuromorphic:'''
 
'''Neuromorphic:'''
 
* {{intel|Loihi}}
 
* {{intel|Loihi}}
 +
* {{intel|Loihi 2}}
 
'''Artificial Intelligence'''
 
'''Artificial Intelligence'''
 
* {{intel|ETANN}}
 
* {{intel|ETANN}}
 
'''Quantum:'''
 
'''Quantum:'''
 
* {{intel|Surface-17}}
 
* {{intel|Surface-17}}
 +
* {{intel|Tangle Lake}}
 
'''RAM:'''
 
'''RAM:'''
 
* {{intel|3101}}
 
* {{intel|3101}}
Line 338: Line 411:
 
|
 
|
 
* {{\\|Dynamic Tuning}}
 
* {{\\|Dynamic Tuning}}
 +
* {{\\|Hyper Scaling}}
 +
* {{\\|Speed Select Technology}} (SST)
 
* {{\\|Turbo Boost Technology}} (TBT)
 
* {{\\|Turbo Boost Technology}} (TBT)
 
* {{\\|Thermal Velocity Boost}} (TVB)
 
* {{\\|Thermal Velocity Boost}} (TVB)
 +
* {{\\|DL Boost}}
 +
}}
 +
 +
== Packaging Technologies ==
 +
{{collist
 +
| count = 2
 +
|
 +
* {{\\|Foveros}}
 +
* {{\\|EMIB}}
 
}}
 
}}
  

Latest revision as of 04:45, 6 November 2024

Intel
Intel logo (2006-2020).svg
Type Public
Founded July 18, 1968
Mountain View, California
Founder Gordon Moore
Robert Noyce
Andrew Grove
Headquarters Santa Clara, California
Website http://www.intel.com
IC Identification
Logo Example Package
ic logo (intel).svg ic example (intel).svg
By Prefix • By Logo

Intel Corporation is an American semiconductor company. While most notably known for their development of microprocessors and x86, Intel also designs and manufactures other integrated circuits including flash memory, network interface controllers, GPUs, chipsets, motherboards, and computers.

In addition to x86, Intel used to also design and manufacture ARM-based chips as well as embed ARC-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.

Subsidiaries[edit]

Find Chip[edit]

List of processor families[edit]

List of architectures[edit]

List of microarchitectures[edit]

Mainstream (x86):


Client SoC:



Server SoC:


Networking SoC:


High-Perf (Big Cores):


High-Efficiency (Small Cores)

MCU:

ULP (ARM):


Server (EPIC) (Itanium):

Many-core:

Early Research:

MIC Architectures:

Heterogeneous:


GPU:

Integrated:

Discrete:

Artificial Intelligence:

Training:

Inference:

Other Chips[edit]

Neuromorphic:

Artificial Intelligence

Quantum:

RAM:

Architectural Concepts[edit]

Other[edit]

Other topics[edit]

Technologies[edit]

Packaging Technologies[edit]

Documents[edit]

See Documents.

Retrieved from "https://en.wikichip.org/w/index.php?title=intel&oldid=102592"
Facts about "Intel"
RDF feed
company typepublic +
foundedJuly 18, 1968 +
founded locationMountain View, California +
founderGordon Moore +, Robert Noyce + and Andrew Grove +
full page nameintel +
headquartersSanta Clara, California +
instance ofsemiconductor company +
nameIntel +
websitehttp://www.intel.com +
wikidata idQ248 +