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In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
 
In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
 +
 +
== Subsidiaries ==
 +
* [[Barefoot Networks]]
 +
* [[Movidius]]
 +
* [[Nervana]]
 +
* [[Mobileye]]
  
 
== Find Chip ==
 
== Find Chip ==
Line 95: Line 101:
 
* {{intel|Xeon Bronze}}
 
* {{intel|Xeon Bronze}}
 
* {{intel|Xeon D}}
 
* {{intel|Xeon D}}
 +
* {{intel|Xeon E}}
 
* {{intel|Xeon E3}}
 
* {{intel|Xeon E3}}
 
* {{intel|Xeon E5}}
 
* {{intel|Xeon E5}}
Line 104: Line 111:
 
}}
 
}}
  
−
== List of instruction set architectures ==
+
== List of architectures ==
 
{{collist
 
{{collist
 
| count = 1
 
| count = 1
 
|
 
|
−
* {{intel|MCS-8/ISA|MCS-8 (8008)}}
+
* {{\\|MCS-8/ISA|MCS-8 (8008)}}
 +
* [[x86]]
 +
* {{\\|Configurable Spatial Accelerator}} (CSA)
 +
* {{\\|Programmable Unified Memory Architecture}} (PUMA)
 
}}
 
}}
  
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* {{intel|NetBurst|l=arch}}
 
* {{intel|NetBurst|l=arch}}
 
* {{intel|Enhanced NetBurst|l=arch}}
 
* {{intel|Enhanced NetBurst|l=arch}}
−
* {{intel|Core|l=arch}}
+
}}
−
* {{intel|Penryn|l=arch}}
+
 
−
* {{intel|Nehalem|l=arch}}
+
 
−
* {{intel|Westmere|l=arch}}
+
{{collist
−
* {{intel|Sandy Bridge|l=arch}}
+
| count = 4
−
* {{intel|Ivy Bridge|l=arch}}
+
| style= margin-left: 20px;
−
* {{intel|Haswell|l=arch}}
+
|
−
* {{intel|Broadwell|l=arch}}
+
'''Client SoC:'''
−
* Skylake ({{intel|Skylake|client}}, {{intel|Skylake (server)|server}})
+
* {{intel|Core (client)|l=arch}}
 +
* {{intel|Penryn (client)|l=arch}}
 +
* {{intel|Nehalem (client)|l=arch}}
 +
* {{intel|Westmere (client)|l=arch}}
 +
* {{intel|Sandy Bridge (client)|l=arch}}
 +
* {{intel|Ivy Bridge (client)|l=arch}}
 +
* {{intel|Haswell (client)|l=arch}}
 +
* {{intel|Broadwell (client)|l=arch}}
 +
* {{intel|Skylake (client)|l=arch}}
 
* {{intel|Kaby Lake|l=arch}}
 
* {{intel|Kaby Lake|l=arch}}
 
* {{intel|Coffee Lake|l=arch}}
 
* {{intel|Coffee Lake|l=arch}}
 
* {{intel|Whiskey Lake|l=arch}}
 
* {{intel|Whiskey Lake|l=arch}}
 +
* {{intel|Amber Lake|l=arch}}
 +
* {{intel|Comet Lake|l=arch}}
 +
* {{intel|Keystone Lake|l=arch}}
 +
* {{intel|Rocket Lake|l=arch}}
 +
* {{intel|Cannon Lake|l=arch}} ("Skymont")
 +
* {{intel|Ice Lake (client)|l=arch}}
 +
* {{intel|Tiger Lake|l=arch}}
 +
* {{intel|Alder Lake|l=arch}}
 +
* {{intel|Raptor Lake|l=arch}}
 +
* {{intel|Meteor Lake|l=arch}}
 +
* {{intel|Arrow Lake|l=arch}}
 +
* {{intel|Lunar Lake|l=arch}}
 +
 +
}}
 +
 +
 +
{{collist
 +
| count = 4
 +
| style= margin-left: 20px;
 +
|
 +
'''Server SoC:'''
 +
* {{intel|Core (server)|l=arch}}
 +
* {{intel|Penryn (server)|l=arch}}
 +
* {{intel|Nehalem (server)|l=arch}}
 +
* {{intel|Westmere (server)|l=arch}}
 +
* {{intel|Sandy Bridge (server)|l=arch}}
 +
* {{intel|Ivy Bridge (server)|l=arch}}
 +
* {{intel|Haswell (server)|l=arch}}
 +
* {{intel|Broadwell (server)|l=arch}}
 +
* {{intel|Skylake (server)|l=arch}}
 
* {{intel|Cascade Lake|l=arch}}
 
* {{intel|Cascade Lake|l=arch}}
−
* {{intel|Cannon Lake|l=arch}} ("Skymont")
+
* {{intel|Cooper Lake|l=arch}}
−
* {{intel|Ice Lake|l=arch}}
+
* {{intel|Ice Lake (server)|l=arch}}
−
* {{intel|Tigerlake|l=arch}}
 
 
* {{intel|Sapphire Rapids|l=arch}}
 
* {{intel|Sapphire Rapids|l=arch}}
−
* {{intel|Alder Lake|l=arch}}
+
* {{intel|Emerald Rapids|l=arch}}
−
* {{intel|Anderson Lake|l=arch}}
+
* {{intel|Granite Rapids|l=arch}}
 +
* {{intel|Diamond Rapids|l=arch}}
 +
}}
 +
 
 +
 
 +
{{collist
 +
| count = 4
 +
| style= margin-left: 20px;
 +
|
 +
'''Networking SoC:'''
 +
* {{intel|Snow Ridge|l=arch}}
 +
* {{intel|Tanner Ridge|l=arch}}
 +
}}
 +
 
 +
 
 +
{{collist
 +
| count = 4
 +
| style= margin-left: 20px;
 +
|
 +
'''High-Perf (Big Cores):'''
 +
* {{intel|Palm Cove|l=arch}}
 +
* {{intel|Sunny Cove|l=arch}}
 +
* {{intel|Willow Cove|l=arch}}
 +
* {{intel|Golden Cove|l=arch}}
 +
* {{intel|Ocean Cove|l=arch}}
 
}}
 
}}
−
'''ULP ([[x86]]):'''
+
 
 +
 
 
{{collist
 
{{collist
−
| count = 2
+
| count = 4
 +
| style= margin-left: 20px;
 
|
 
|
 +
'''High-Efficiency (Small Cores)'''
 
* {{intel|Bonnell|l=arch}}
 
* {{intel|Bonnell|l=arch}}
 
* {{intel|Saltwell|l=arch}}
 
* {{intel|Saltwell|l=arch}}
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* {{intel|Goldmont|l=arch}}
 
* {{intel|Goldmont|l=arch}}
 
* {{intel|Goldmont Plus|l=arch}}
 
* {{intel|Goldmont Plus|l=arch}}
 +
* {{intel|Tremont|l=arch}}
 
}}
 
}}
 +
 
'''MCU:'''
 
'''MCU:'''
 
{{collist
 
{{collist
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* {{intel|Lakemont|l=arch}}
 
* {{intel|Lakemont|l=arch}}
 
}}
 
}}
 +
 
'''ULP ([[ARM]]):'''
 
'''ULP ([[ARM]]):'''
 
{{collist
 
{{collist
 
| count = 3
 
| count = 3
 
|
 
|
 +
* .. From [[DEC]]
 
* {{intel|XScale|l=arch}}
 
* {{intel|XScale|l=arch}}
 
* {{intel|XScale 2|l=arch}}
 
* {{intel|XScale 2|l=arch}}
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* Continued by [[Marvell]] ..
 
* Continued by [[Marvell]] ..
 
}}
 
}}
 +
 +
 
'''Server (EPIC) ([[Itanium]]):'''
 
'''Server (EPIC) ([[Itanium]]):'''
 
{{collist
 
{{collist
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* {{intel|Kittson|l=arch}}
 
* {{intel|Kittson|l=arch}}
 
}}
 
}}
−
'''{{intel|MIC Architectures}}:'''
+
'''[[Many-core]]:'''
 +
{{collist
 +
| count = 2
 +
| style= margin-left: 20px;
 +
|
 +
'''Early Research:'''
 +
* {{intel|Polaris|l=arch}}
 +
* {{intel|Larrabee|l=arch}}
 +
* {{intel|Rock Creek|l=arch}}
 +
}}
 +
{{clear}}
 
{{collist
 
{{collist
 
| count = 3
 
| count = 3
 +
| style= margin-left: 20px;
 
|
 
|
−
* {{intel|Larrabee|l=arch}}
+
'''{{intel|MIC Architectures}}:'''
−
* {{intel|Knights Ferry|l=arch}}
+
* {{intel|Knights Ferry|l=arch}} (Aubrey Isle)
−
* {{intel|Knights Corner|l=arch}}
+
* {{intel|Knights Corner|l=arch}} (Angel Isle)
 
* {{intel|Knights Landing|l=arch}}
 
* {{intel|Knights Landing|l=arch}}
 
* {{intel|Knights Mill|l=arch}}
 
* {{intel|Knights Mill|l=arch}}
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* {{intel|Knights Peak|l=arch}}
 
* {{intel|Knights Peak|l=arch}}
 
}}
 
}}
 +
'''Heterogeneous:'''
 +
{{collist
 +
| count = 1
 +
|
 +
* {{intel|Lakefield|l=arch}}
 +
* {{intel|Ryefield|l=arch}}
 +
}}
 +
 +
 
'''GPU:'''
 
'''GPU:'''
 
{{collist
 
{{collist
 
| count = 3
 
| count = 3
−
| width = 500px
+
| style= margin-left: 20px;
 
|
 
|
 +
'''Integrated:'''
 
* {{intel|Gen1|l=arch}}
 
* {{intel|Gen1|l=arch}}
 
* {{intel|Gen2|l=arch}}
 
* {{intel|Gen2|l=arch}}
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* {{intel|Gen11|l=arch}}
 
* {{intel|Gen11|l=arch}}
 
* {{intel|Gen12|l=arch}}
 
* {{intel|Gen12|l=arch}}
 +
}}
 +
{{clear}}
 +
{{collist
 +
| count = 1
 +
| style= margin-left: 20px;
 +
|
 +
'''Discrete:'''
 +
* {{intel|Arctic Sound|l=arch}}
 +
* {{intel|Jupiter Sound|l=arch}}
 +
}}
 +
 +
'''Artificial Intelligence:'''
 +
{{collist
 +
| count = 3
 +
| style= margin-left: 20px;
 +
|
 +
'''Training:'''
 +
* {{intel|Lake Crest|l=arch}}
 +
* {{intel|Spring Crest|l=arch}}
 +
}}
 +
{{clear}}
 +
{{collist
 +
| count = 3
 +
| style= margin-left: 20px;
 +
|
 +
'''Inference:'''
 +
* {{intel|Spring Hill|l=arch}}
 
}}
 
}}
  
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'''Neuromorphic:'''
 
'''Neuromorphic:'''
 
* {{intel|Loihi}}
 
* {{intel|Loihi}}
 +
* {{intel|Loihi 2}}
 
'''Artificial Intelligence'''
 
'''Artificial Intelligence'''
 
* {{intel|ETANN}}
 
* {{intel|ETANN}}
 
'''Quantum:'''
 
'''Quantum:'''
 
* {{intel|Surface-17}}
 
* {{intel|Surface-17}}
 +
* {{intel|Tangle Lake}}
 
'''RAM:'''
 
'''RAM:'''
 
* {{intel|3101}}
 
* {{intel|3101}}
 
* {{intel|1103}}
 
* {{intel|1103}}
 +
}}
 +
 +
== Architectural Concepts ==
 +
{{collist
 +
| count = 1
 +
|
 +
* {{\\|Mesh Interconnect Architecture}}
 +
* {{\\|Ring Interconnect Architecture}}
 
}}
 
}}
  
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| count = 2
 
| count = 2
 
|
 
|
−
* {{intel|CNVi}}
+
* {{\\|CPUID}}
−
* {{intel|Frequency Behavior}}
+
* {{\\|CNVi}}
−
* {{intel|Process-Architecture-Optimization}} (PAO)
+
* {{\\|Flexpoint}}
−
* {{intel|Process Technology}}
+
* {{\\|Frequency Behavior}}
−
* {{intel|Tick-Tock}}
+
* {{\\|Innovation Engine}} (IE)
−
* {{intel|Turbo Boost Technology}} (TBT)
+
* {{\\|Management Engine}} (ME)
 +
* {{\\|Process-Architecture-Optimization}} (PAO)
 +
* {{\\|Process Technology}}
 +
* {{\\|Tick-Tock}}
 +
}}
 +
 
 +
== Technologies ==
 +
{{collist
 +
| count = 2
 +
|
 +
* {{\\|Dynamic Tuning}}
 +
* {{\\|Hyper Scaling}}
 +
* {{\\|Speed Select Technology}} (SST)
 +
* {{\\|Turbo Boost Technology}} (TBT)
 +
* {{\\|Thermal Velocity Boost}} (TVB)
 +
* {{\\|DL Boost}}
 +
}}
 +
 
 +
== Packaging Technologies ==
 +
{{collist
 +
| count = 2
 +
|
 +
* {{\\|Foveros}}
 +
* {{\\|EMIB}}
 
}}
 
}}
  
 
== Documents ==
 
== Documents ==
−
* [[:File:1975 Intel Data Catalog.pdf|Intel Data Catalog]], 1975
+
See {{\\|Documents}}.
  
 
[[Category:intel]]
 
[[Category:intel]]

Latest revision as of 23:03, 1 October 2022

Intel
Intel logo (2006-2020).svg
Type Public
Founded July 18, 1968
Mountain View, California
Founder Gordon Moore
Robert Noyce
Andrew Grove
Headquarters Santa Clara, California
Website http://www.intel.com
IC Identification
Logo Example Package
ic logo (intel).svg ic example (intel).svg
By Prefix • By Logo

Intel Corporation is an American semiconductor company. While most notably known for their development of microprocessors and x86, Intel also designs and manufactures other integrated circuits including flash memory, network interface controllers, GPUs, chipsets, motherboards, and computers.

In addition to x86, Intel used to also design and manufacture ARM-based chips as well as embed ARC-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.

Subsidiaries[edit]

Find Chip[edit]

List of processor families[edit]

List of architectures[edit]

List of microarchitectures[edit]

Mainstream (x86):


Client SoC:



Server SoC:


Networking SoC:


High-Perf (Big Cores):


High-Efficiency (Small Cores)

MCU:

ULP (ARM):


Server (EPIC) (Itanium):

Many-core:

Early Research:

MIC Architectures:

Heterogeneous:


GPU:

Integrated:

Discrete:

Artificial Intelligence:

Training:

Inference:

Other Chips[edit]

Neuromorphic:

Artificial Intelligence

Quantum:

RAM:

Architectural Concepts[edit]

Other[edit]

Other topics[edit]

Technologies[edit]

Packaging Technologies[edit]

Documents[edit]

See Documents.

Retrieved from "https://en.wikichip.org/w/index.php?title=intel&oldid=100568"
Facts about "Intel"
RDF feed
company typepublic +
foundedJuly 18, 1968 +
founded locationMountain View, California +
founderGordon Moore +, Robert Noyce + and Andrew Grove +
full page nameintel +
headquartersSanta Clara, California +
instance ofsemiconductor company +
nameIntel +
websitehttp://www.intel.com +
wikidata idQ248 +