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{{intel title|Microarchitectures}}
 +
Below is a list of [[Intel]] [[microarchitectures]]:
 +
== CPU Microarchitectures ==
 +
{{see also|Intel|Lake|Core|intel/core}}
 +
 
 +
<table class="wikitable sortable">
 +
<tr><th colspan="12" style="background:#D6D6FF;">Intel CPU Microarchitectures</th></tr>
 +
<tr><th colspan="6">General</th><th colspan="5">Details</th></tr>
 +
<tr><th>µarch</th><th>Type</th><th>[[ISA]]</th><th>Manuf</th><th>Introduction</th><th>Phase-out</th><th>[[technology node|Process]]</th><th>Cores</th><th colspan="3">Pipeline<br>Num•Min•Max</th></tr>
 +
{{#ask:
 +
[[Category:cpu microarchitectures by intel]]
 +
[[instance of::microarchitecture]]
 +
[[designer::Intel]]
 +
|?full page name
 +
|?name
 +
|?microarchitecture_type
 +
|?instruction_set_architecture
 +
|?manufacturer
 +
|?first launched#ISO
 +
|?phase-out#ISO
 +
|?process
 +
|?core count
 +
|?pipeline stages
 +
|?pipeline stages (min)
 +
|?pipeline stages (max)
 +
|limit=100
 +
|sort=first launched
 +
|order=ascending
 +
|format=template
 +
|template=proc table 2
 +
|userparam=12
 +
|valuesep=,
 +
|mainlabel=-
 +
}}
 +
</table>
 +
 
 +
=== Newest models ===
 +
:;TSMC N3B ([[3 nm]])
 +
* {{intel|Lunar Lake|l=arch}} (hybrid) • ''Lion Cove'' (P)/''Skymont'' (E) • Ultra 200V • 2024-09
 +
* {{intel|Arrow Lake|l=arch}} (hybrid) • ''Ultra'' Series 2 • 2024-10 (desktop)/2025-01 (mobile)
 +
:;[[Intel]] 18A
 +
* {{intel|Panther Lake|l=arch}} (hybrid) • ''Cougar Cove'' (P)/''Darkmont'' (E) • ''Ultra'' 300 • 2025
 +
* {{intel|Diamond Rapids|l=arch}} • ''Panther Cove X'' (''Mountain Stream'') • 2025
 +
:;[[Intel]] 18A (or [[TSMC]] [[2 nm]])
 +
* {{intel|Nova Lake|l=arch}} (hybrid) • ''Coyote Cove'' • 2026
 +
* {{intel|Razer Lake|l=arch}} (hybrid) • (TBA) • 2027
 +
 
 +
== GPU Microarchitectures ==
 +
<table class="wikitable sortable">
 +
<tr><th colspan="12" style="background:#D6D6FF;">Intel GPU Microarchitectures</th></tr>
 +
<tr><th colspan="3">General</th><th colspan="5">Details</th></tr>
 +
<tr><th>µarch</th><th>Introduction</th><th>Phase-out</th><th>[[technology node|Process]]</th></tr>
 +
{{#ask:
 +
[[Category:gpu microarchitectures by intel]]
 +
[[instance of::microarchitecture]]
 +
[[designer::Intel]]
 +
|?full page name
 +
|?name
 +
|?first launched#ISO
 +
|?phase-out#ISO
 +
|?process
 +
|sort=first launched
 +
|order=ascending
 +
|format=template
 +
|template=proc table 2
 +
|userparam=5
 +
|valuesep=,
 +
|mainlabel=-
 +
}}
 +
</table>
 +
 
 +
== Intel Core Lines ==
 +
;{{see also|Intel|Core|Intel Atom|Lake|intel/roadmap}}
 +
{| class="wikitable mw-datatable" style="margin:0.2em auto; text-align:center; min-width:72em;"
 +
|+Intel Core Roadmap
 +
|-
 +
! rowspan="2" | Fab<br>process
 +
! rowspan="2" | Micro-<br>architecture
 +
! rowspan="2" | Code<br>names
 +
! rowspan="2" | Core<br>{{abbr|Gen|generation}}
 +
! rowspan="2" | Scalable<br>(Xeon)<br>{{abbr|Gen|generation}}
 +
! rowspan="2" | Release<br>date
 +
! colspan="5" | Processors
 +
|-
 +
! Mobile
 +
! Desktop
 +
! Enthusiast/<br>Workstation
 +
! 1P/2P<br>Server
 +
! 4P/8P<br>Server
 +
|-
 +
| [[180 nm]]
 +
! rowspan="2" | [[NetBurst]]
 +
| {{intel|Willamette|l=core}}
 +
| colspan="2" rowspan="3" | &mdash;
 +
| 2000-11
 +
| &mdash;
 +
| {{intel|Willamette|l=core}}
 +
| &mdash;
 +
| Foster
 +
| Foster MP
 +
|-
 +
| [[130 nm]]<hr>[[90 nm]]
 +
| {{intel|Northwood|l=core}}<hr>{{intel|Prescott|l=arch}}
 +
| 2002-01
 +
| Northwood <br>Mobile
 +
| Northwood <hr>Prescott
 +
| Northwood-XE <hr>Prescott 2M-XE
 +
| Prestonia<br>Gallatin
 +
| Gallatin
 +
|- <!-- Pentium M (arch): Core: Banias, Dothan, Stealey, Canmore, Tolapai; Core: (Atom) Diamondville, Silverthorne -->
 +
| [[130 nm]]<hr>[[90 nm]]<hr>[[90 nm]]<hr>[[65 nm]]
 +
! {{intel|Pentium M|l=arch}}<br>.<hr>.<br>{{intel|Pentium D|l=arch}}<!-- Pentium D: 90 nm Smithfield, 65 nm Presler -->
 +
| {{intel|Banias|l=core}}<hr>{{intel|Dothan|l=core}}<hr>{{intel|Smithfield|l=core}}<hr>{{intel|Presler|l=core}}
 +
| 2004-02
 +
| {{intel|Banias|l=core}}<hr>{{intel|Dothan|l=core}}
 +
| {{intel|Smithfield|l=core}}<hr>{{intel|Presler|l=core}}
 +
| Smithfield-XE<hr>Presler-XE
 +
| Nocona<br>Irwindale<br>Paxville
 +
| Potomac<br>Cranford<br>Paxville
 +
|-
 +
| rowspan="2" | [[65 nm]]
 +
! {{intel|Modified Pentium M|Modified <br>Pentium M|l=arch}}
 +
| {{intel|Yonah|l=core}}<br>{{intel|Cedar Mill|l=core}}
 +
| 1<br><small>(Yonah)</small>
 +
| rowspan="10" | &mdash;
 +
| 2006-01
 +
| Yonah
 +
| Cedar Mill
 +
| -
 +
| Dempsey<br>Sossaman
 +
| Tulsa <br>('''Xeon''')
 +
|-
 +
! rowspan="2" | '''{{intel|core|Intel Core|l=arch}}'''
 +
| {{intel|Merom|l=core}}
 +
| rowspan="2" | 2
 +
| 2006-07
 +
| {{intel|Merom|l=core}}<br>Merom-L
 +
| {{intel|Conroe|l=core}}
 +
| {{intel|Kentsfield|l=core}}
 +
| {{intel|Woodcrest|l=core}}<br>{{intel|Clovertown|l=core}}
 +
| {{intel|Tigerton|l=core}}
 +
|-
 +
| rowspan="2" | [[45 nm]]
 +
| [[Penryn]]
 +
| 2007-11
 +
| {{intel|Penryn|l=arch}}
 +
| {{intel|Wolfdale|l=core}}
 +
| {{intel|Yorkfield|l=core}}
 +
| {{intel|Harpertown|l=core}}
 +
| {{intel|Dunnington|l=core}}
 +
|-
 +
! rowspan="2" | {{intel|Nehalem|l=arch}}
 +
| {{intel|Nehalem|l=arch}}
 +
| rowspan="2" | 1 <br>(Core i)
 +
| 2008-11
 +
| {{intel|Clarksfield|l=core}}
 +
| {{intel|Lynnfield|l=core}}
 +
| {{intel|Bloomfield|l=core}}
 +
| {{intel|Gainestown|l=core}}
 +
| {{intel|Beckton|l=core}}
 +
|-
 +
| rowspan="2" | [[32 nm]]
 +
| {{intel|Westmere|l=arch}}
 +
| 2010-01
 +
| {{intel|Arrandale|l=core}}
 +
| {{intel|Clarkdale|l=core}}
 +
| {{intel|Gulftown|l=core}}
 +
| {{intel|Westmere EP|l=core}}
 +
| {{intel|Westmere EX|l=core}}
 +
|-
 +
! rowspan="2" | {{intel|Sandy Bridge|l=arch}}
 +
| {{intel|Sandy Bridge|l=arch}}
 +
| 2
 +
| 2011-01
 +
| {{intel|Sandy Bridge M|l=core}}
 +
| {{intel|Sandy Bridge|l=arch}}
 +
| {{intel|Sandy Bridge E|l=core}}
 +
| {{intel|Sandy Bridge EP|l=core}}
 +
| &mdash;
 +
|-
 +
| rowspan="3" | [[22 nm]]
 +
| {{intel|Ivy Bridge|l=arch}}
 +
| 3
 +
| 2012-04
 +
| {{intel|Ivy Bridge M|l=core}}
 +
| {{intel|Ivy Bridge|l=arch}}
 +
| {{intel|Ivy Bridge E|l=core}}
 +
| {{intel|Ivy Bridge EP|l=core}}
 +
| {{intel|Ivy Bridge EX|l=core}}
 +
|-
 +
! rowspan="2" | {{intel|Haswell|l=arch}}
 +
| [[Haswell]]
 +
| rowspan="2" | 4
 +
| 2013-06
 +
| {{intel|Haswell H|l=core}}<br>{{intel|Haswell MB|l=core}}<br>{{intel|Haswell ULP|l=core}}<br>{{intel|Haswell ULX|l=core}}
 +
| {{intel|Haswell DT|l=core}}
 +
| {{intel|Haswell E|l=core}}
 +
| {{intel|Haswell EP|l=core}}
 +
| {{intel|Haswell EX|l=core}}
 +
|-
 +
| ''Devil's Canyon''
 +
| 2014-06
 +
| &mdash;
 +
| Haswell DT
 +
| colspan=3 | &mdash;
 +
|-
 +
| rowspan="10" | [[14 nm]]
 +
! {{intel|Broadwell|l=arch}}
 +
| [[Broadwell]]
 +
| 5
 +
| 2014-09
 +
| {{intel|Broadwell H|l=core}}<br>{{intel|Broadwell U|l=core}}<br>{{intel|Broadwell Y|l=core}}
 +
| {{intel|Broadwell DT|l=core}}<br>''{{intel|Broadwell DE|l=core}}''
 +
| {{intel|Broadwell E|l=core}}
 +
| {{intel|Broadwell EP|l=core}}<br>('''{{intel|Xeon E5}}''' v4)
 +
| {{intel|Broadwell EX|l=core}}<br>('''{{intel|Xeon E7}}''' v4)
 +
|-
 +
! {{intel|Skylake|l=arch}}
 +
| [[Skylake]]
 +
| 6
 +
| Xeon 1
 +
| 2015-08
 +
| {{intel|Skylake H|l=core}}<br>{{intel|Skylake U|l=core}}<br>{{intel|Skylake Y|l=core}}
 +
| ''{{intel|Skylake DT|l=core}}''<br>{{intel|Skylake S|l=core}}
 +
| {{intel|Skylake W|l=core}}<br>{{intel|Skylake X|l=core}}
 +
| colspan="2" | {{intel|Skylake SP|l=core}}<br><small>(formerly Skylake-EP/EX)</small> <br>('''Xeon''' Gold, Platinum)
 +
|-
 +
! {{intel|Kaby Lake|l=arch}}
 +
| [[Kaby Lake]]
 +
| 7 / 8
 +
| rowspan="4" | &mdash;
 +
| 2016-10
 +
| {{intel|Kaby Lake G|l=core}}<br>{{intel|Kaby Lake H|l=core}}<br>{{intel|Kaby Lake U|l=core}}<br>{{intel|Kaby Lake Y|l=core}}
 +
| {{intel|Kaby Lake S|l=core}}
 +
| {{intel|Kaby Lake X|l=core}}
 +
| colspan="2" | &mdash;
 +
|-
 +
! {{intel|Coffee Lake|l=arch}}
 +
| [[Coffee Lake]]
 +
| 8 / 9
 +
| 2017-10
 +
| {{intel|Coffee Lake B|l=core}}<br>{{intel|Coffee Lake H|l=core}}<br>{{intel|Coffee Lake U|l=core}}
 +
| {{intel|Coffee Lake S|l=core}}
 +
| {{intel|Coffee Lake W|l=core}}
 +
| [[Coffee Lake]]<br>('''{{intel|Xeon}}''' E)
 +
| &mdash;
 +
|-
 +
! {{intel|Whiskey Lake|l=arch}}
 +
| [[Whiskey Lake]]
 +
| 8
 +
| rowspan="2" | 2018-08
 +
| {{intel|Whiskey Lake U|l=core}}
 +
| colspan="2" rowspan="2" | &mdash;
 +
| colspan="2" rowspan="2" | &mdash;
 +
|-
 +
! {{intel|Amber Lake|l=arch}}
 +
| [[Amber Lake]]
 +
| 8 / 10
 +
| {{intel|Amber Lake Y|l=core}}
 +
|-
 +
! {{intel|Cascade Lake|l=arch}}
 +
| [[Cascade Lake]]
 +
| &mdash;
 +
| Xeon 2
 +
| 2019-04
 +
| colspan="2" | &mdash;
 +
| {{intel|Cascade Lake W|l=core}}<br>{{intel|Cascade Lake X|l=core}}
 +
| colspan="2" | {{intel|Cascade Lake AP|l=core}}<br>{{intel|Cascade Lake SP|l=core}} ('''Xeon''')
 +
|-
 +
! {{intel|Comet Lake|l=arch}}
 +
| [[Comet Lake]]
 +
| 10
 +
| &mdash;
 +
| 2019-09
 +
| {{intel|Comet Lake H|l=core}}<br>{{intel|Comet Lake Y|l=core}}<br>{{intel|Comet Lake U|l=core}}
 +
| {{intel|Comet Lake S|l=core}}
 +
| {{intel|Comet Lake W|l=core}}
 +
| colspan="2" | &mdash;
 +
|-
 +
! {{intel|Cooper Lake|l=arch}}
 +
| [[Cooper Lake]]
 +
| &mdash;
 +
| Xeon 3
 +
| 2020-06
 +
| colspan="4" | &mdash;
 +
| {{intel|Cooper Lake SP|l=core}}
 +
|-
 +
! {{intel|Rocket Lake|l=arch}}
 +
| {{intel|Cypress Cove|l=core}}
 +
| 11
 +
| rowspan=2 | &mdash;
 +
| 2021-03
 +
| &mdash;
 +
| {{intel|Rocket Lake SP|l=core}}
 +
| {{intel|Rocket Lake W|l=core}}
 +
| {{intel|Rocket Lake|l=arch}}<br>('''{{intel|Xeon}}''' E)
 +
| &mdash;
 +
|-
 +
| rowspan=4 | [[10 nm]]
 +
! [[Cannon Lake]]
 +
| [[Palm Cove]]
 +
| 8
 +
| 2018-05
 +
| {{intel|Cannon Lake U|l=core}}
 +
| colspan=2 | &mdash;
 +
| colspan=2 | &mdash;
 +
|-
 +
! [[Ice Lake]]<br><small>(client)</small><br><small>(server)</small>
 +
| rowspan=2 | [[Sunny Cove]]<br>.<hr>.<br>+ 4x {{intel|Tremont|l=arch}}
 +
| 10
 +
| Xeon 3
 +
| 2019-09<br><small>(client)</small><br>2021-04<br><small>(server)</small>
 +
| {{intel|Ice Lake U|l=core}}<br>{{intel|Ice Lake Y|l=core}}
 +
| &mdash;
 +
| {{intel|Ice Lake W|l=core}}
 +
| {{intel|Ice Lake SP|l=core}} <!-- + Cooper Lake -->
 +
| &mdash;
 +
|-
 +
! {{intel|Lakefield|l=arch}}<br><small>(hybrid)</small><br>({{intel|Foveros}})
 +
| &mdash;
 +
| rowspan="3" | &mdash;
 +
| 2020-06
 +
| {{intel|Lakefield|l=arch}}
 +
|
 +
|
 +
|
 +
| &mdash;
 +
|-
 +
! {{intel|Tiger Lake|l=arch}}
 +
| {{intel|Willow Cove|l=arch}}
 +
| 11
 +
| 2020-09
 +
| Tiger Lake-H<br>Tiger Lake-H35<br>Tiger Lake-UP3<br>Tiger Lake-UP4
 +
|
 +
|
 +
|
 +
| &mdash;
 +
|-
 +
| rowspan="4" | [[Intel]] [[7 nm]]
 +
! {{intel|Alder Lake|l=arch}}<br><small>(hybrid)</small>
 +
| rowspan="2" | {{intel|Golden Cove|l=arch}} (P)<br>{{intel|Gracemont|l=arch}} (E)
 +
| 12
 +
| 2021-11 <!-- ? "Sunny Cove" -->
 +
| Alder Lake-H<br>Alder Lake-HX<br>Alder Lake-U<br>{{intel|Alder Lake M|l=core}}
 +
| {{intel|Alder Lake S|l=core}}
 +
| {{intel|Alder Lake P|l=core}}
 +
| colspan=2 | &mdash;
 +
|-
 +
! [[Sapphire Rapids]]
 +
| &mdash;
 +
| Xeon 4
 +
| 2023-01
 +
| colspan=2 | &mdash;
 +
| Sapphire <br>Rapids-WS
 +
| Sapphire <br>Rapids-SP/HBM<br>('''{{intel|Xeon}}''' Max)
 +
| Sapphire <br>Rapids-SP
 +
|-
 +
! {{intel|Raptor Lake|l=arch}}<br><small>(hybrid)</small>
 +
| rowspan="2" | {{intel|Raptor Cove|l=arch}} (P)<br>{{intel|Gracemont|l=arch}} (E)
 +
| 13 / 14 /<br>Series<br> 1 / 2
 +
| &mdash;
 +
| 2022-10
 +
| Raptor Lake-HX<br>Raptor Lake-PX<br>Raptor Lake U
 +
| Raptor Lake S
 +
| Raptor Lake H<br>Raptor Lake P
 +
| Raptor Lake<br>('''{{intel|Xeon}}''' E)
 +
| rowspan=2 | &mdash;
 +
|-
 +
! {{intel|Emerald Rapids|l=arch}}
 +
| &mdash;
 +
| Xeon 5
 +
| 2023-12
 +
| colspan="3" | &mdash;
 +
| Emerald <br>Rapids-SP
 +
|-
 +
| [[Intel]] [[4 nm]]
 +
! {{intel|Meteor Lake|l=arch}}<br><small>(hybrid)</small>
 +
| rowspan="2" | {{intel|Redwood Cove|l=arch}} (P)<br>{{intel|Crestmont|l=arch}} (E)
 +
| Ultra <br>Series 1
 +
| &mdash;
 +
| 2023-12
 +
| Meteor Lake-H<br>Meteor Lake-U
 +
| colspan="2" | &mdash;
 +
| colspan="2" | &mdash;
 +
|-
 +
| [[Intel]] [[3 nm]]
 +
! {{intel|Granite Rapids|l=arch}}
 +
| &mdash;
 +
| '''{{intel|Sierra Forest|Xeon 6|l=arch}}'''
 +
| 2024-09
 +
| colspan="3" | &mdash;
 +
| Granite Rapids-AP<br>Granite Rapids-SP
 +
| &mdash;
 +
|-
 +
| rowspan="2" | [[TSMC]] N3B
 +
! {{intel|Lunar Lake|l=arch}}<br><small>(hybrid)</small>
 +
| rowspan="2" | {{intel|Lion Cove|l=arch}} (P)<br>{{intel|Skymont|l=arch}} (E)
 +
| Ultra<br>200V <!-- Core Ultra 200V -->
 +
| rowspan="3" | &mdash;
 +
| 2024-09
 +
| Lunar Lake-V
 +
| colspan=2 | &mdash;
 +
| colspan=2 | &mdash;
 +
|-
 +
! {{intel|Arrow Lake|l=arch}}<br><small>(hybrid)</small>
 +
| Ultra <br>200 <br>Series 2
 +
| 2024-10<br><small>(desktop)</small><br>2025-01<br><small>(mobile)</small>
 +
| Arrow Lake-H<br>Arrow Lake-HX<br>Arrow Lake-U
 +
| Arrow Lake-S
 +
|
 +
| &mdash;
 +
| &mdash;
 +
|-
 +
| rowspan="2" | [[Intel]] 18A
 +
! {{intel|Panther Lake|l=arch}}<br><small>(hybrid)</small>
 +
| {{intel|Cougar Cove|l=arch}} (P)<br>{{intel|Darkmont|l=arch}} (E) <!-- Cougar Cove (P-cores), Darkmont (E-cores) -->
 +
| Ultra <br>300 <!-- Core Ultra 300 -->
 +
| 2025
 +
| Panther Lake-H<br>Panther Lake-HL<br>Panther Lake-U<br>Panther Lake-UL
 +
| ?
 +
|
 +
| &mdash;
 +
| &mdash;
 +
|-
 +
! {{intel|Diamond Rapids|l=arch}}
 +
| {{intel|Panther Cove X|l=arch}}<br>(''Mountain Stream'') <!-- Panther Cove X, Mountain Stream -->
 +
| &mdash;
 +
| ?
 +
| 2025
 +
| &mdash;
 +
|
 +
|
 +
| &mdash;
 +
| &mdash;
 +
|-
 +
| rowspan="3" | TBA<br>([[TSMC]] <br>[[2 nm]] or<br>[[Intel]] 18A<br>[[Intel]] 14A)
 +
! {{intel|Wildcat Lake|l=arch}}<br><small>(hybrid)</small>
 +
| {{intel|Cougar Cove|l=arch}} (P)<br>{{intel|Darkmont|l=arch}} (LPE)<!--Cougar Cove (P),Darkmont (LPE) WCL,2P+4LPE -->
 +
|
 +
| &mdash;
 +
| 2025
 +
| &mdash;
 +
| TBA
 +
| TBA
 +
| &mdash;
 +
| &mdash;
 +
|-
 +
! {{intel|Nova Lake|l=arch}}<br><small>(hybrid)</small>
 +
| {{intel|Coyote Cove|l=arch}} (P)<br>Arctic Wolf (E) <!-- Coyote Cove (P), Arctic Wolf (E) -->
 +
|
 +
| &mdash;
 +
| 2026
 +
| &mdash;
 +
| TBA
 +
| TBA
 +
| &mdash;
 +
| &mdash;
 +
|-
 +
! {{intel|Razer Lake|l=arch}}<br><small>(hybrid)</small>
 +
|
 +
|
 +
| &mdash;
 +
| 2027
 +
| &mdash;
 +
| TBA
 +
| TBA
 +
| &mdash;
 +
| &mdash;
 +
|-
 +
|}
 +
 
 +
===Intel Mainstream CPU Generations comparison===
 +
 
 +
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;"
 +
|-
 +
! [[Intel]] CPU <br>family !! Processor <br>[[Technology Node|process]] !! Processor <br>architecture !! Graphics <br>architecture !! Processors <br>cores/threads !! Platform !! Memory support !! PCIe support !! Launch
 +
|-
 +
! {{intel|Alder Lake|l=arch}}<br><small>(12th Gen)</small>
 +
| [[Intel 7]] || {{intel|Golden Cove|l=arch}} (P-Core) <br>{{intel|Gracemont|l=arch}} (E-Core) || HD 700 Series || 16/24 || LGA 1700/1800 || DDR5 / DDR4 || PCIe Gen 5.0 || [[2021]]
 +
|-
 +
! {{intel|Raptor Lake|l=arch}}<br><small>(13th Gen)</small>
 +
| [[Intel 7]] || Raptor Cove (P-Core) <br>{{intel|Gracemont|l=arch}} (E-Core) || HD 700 Series || 24/32 || LGA 1700/1800 || DDR5 / DDR4 || PCIe Gen 5.0 || [[2022]]
 +
|-
 +
! {{intel|Raptor Lake|l=arch}}<br><small>Refresh (14th Gen)</small>
 +
| [[Intel 7]] || Raptor Cove (P-Core) <br>{{intel|Gracemont|l=arch}} (E-Core) || HD 700 Series || 24/32 || LGA 1700/1800 || DDR5 / DDR4 || PCIe Gen 5.0 || [[2023]]
 +
|-
 +
! {{intel|Meteor Lake|l=arch}}<br><small>([[Core]] Ultra 100)</small>
 +
| [[5 nm|Intel 4]] || Redwood Cove (P-Core) <br>Crestmont (E-Core) || Xe1 (Alchemist) || 22/28 || LGA 1851 || DDR5 || PCIe Gen 5.0 || [[2024]]
 +
|-
 +
! {{intel|Arrow Lake|l=arch}}<br><small>([[Core]] Ultra 200)</small>
 +
| [[TSMC]] N3B || Lion Cove (P-Core) <br>Skymont (E-Core) || Xe1 (Alchemist) || 24/24 || LGA 1851 || DDR5 || PCIe Gen 5.0 || [[2024]]
 +
|-
 +
! {{intel|Arrow Lake|l=arch}}<br><small>Refresh (TBD)</small>
 +
| [[TSMC]] N3B ? || Lion Cove (P-Core) <br>Skymont (E-Core) || Xe1 (Alchemist) || 24/24 || LGA 1851 || DDR5 || PCIe Gen 5.0 || [[2025]]
 +
|-
 +
! {{intel|Lunar Lake|l=arch}}<br><small>([[Core]] Ultra 200V)</small>
 +
| [[Intel]] 18A || Lion Cove (P-Core) <br>Skymont (E-Core) || Xe2 (Battlemage) || 8/8 ? || LGA 1851 ? || DDR5 || PCIe Gen 5.0 ? || [[2024]]
 +
|-
 +
! {{intel|Panther Lake|l=arch}}<br><small>([[Core]] Ultra 300)</small> <!-- Panther Lake-H/HX -->
 +
| [[Intel]] 18A || Cougar Cove (P-Core) <br>Skymont (E-Core) || Xe3 (Celestial) || 16/16 || LGA 1851 ? || DDR5 || PCIe Gen 5.0 ? || [[2025]]
 +
|-
 +
! {{intel|Wildcat Lake|l=arch}}<br><small>([[Core]] Ultra 300?)</small>
 +
| [[Intel]] 18A || Cougar Cove (P-Core) <br>Darkmont (E-Core) || Xe3 (Celestial) || 16/32 || LGA 1851 ? || DDR5 || PCIe Gen 6.0 ? || [[2025]]
 +
|-
 +
! {{intel|Nova Lake|l=arch}}<br><small>([[Core]] Ultra 400?)</small> <!--
 +
:NVL-SK: 2x 8P + 16E, NVL-HX: 1x 8P + 16E, NVL-S/NVL-H: 4P + 8E, NVL-U: 4P + 0E • 16 (P) + 32 (E)-->
 +
| TBA || Coyote Cove (P-Core) <br>Arctic Wolf (E-Core) || Xe4 ("Druid") ? || 16(P)/32(E) ? || TBA || DDR5 ? || PCIe Gen 6.0 ? || [[2026]]
 +
|-
 +
! {{intel|Razer Lake|l=arch}}<br><small>([[Core]] Ultra 500?)</small>
 +
| TBA || TBA || TBA || TBA || TBA || TBA || TBA || [[2027]] ?
 +
|-
 +
|}
 +
 
 +
== Many-core ==
 +
{{work-in-progress}}
 +
 
 +
=== Initial effort & Polaris ===
 +
Intel actual large effort research into the area of [[many-core]] started after the February 2004 [[Intel Developer Forum]] following Pradeep Dubey famous keynote titled "The Era of Tera." Around the [[2004]]-[[2005]] Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the {{intel|Tera-scale Computing Research Program}} which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.
 +
 
 +
The first product to come directly from that project was {{intel|Polaris|l=arch}}, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a [[mesh topology]]. Fabricated on a [[65 nm process]], the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. [[3D IC|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustained performance.
 +
 
 +
=== Larrabee ===
 +
{{empty section}}
 +
 
 +
[[Category:intel]]

Latest revision as of 02:30, 31 March 2025

Below is a list of Intel microarchitectures:

CPU Microarchitectures[edit]

See also: Intel, Lake, Core, and intel/core


Intel CPU Microarchitectures
GeneralDetails
µarchTypeISAManufIntroductionPhase-outProcessCoresPipeline
Num•Min•Max
80386CPUx86-32Intel1984-03-011989-01-011,500 nm
1.5 μm
0.0015 mm
80486CPUx86-32Intel, AMD1989-04-101995-01-011,000 nm
1 μm
0.001 mm
, 800 nm
0.8 μm
8.0e-4 mm
, 600 nm
0.6 μm
6.0e-4 mm
P5CPUx86-32Intel1993-04-011995-10-01600 nm
0.6 μm
6.0e-4 mm
P6CPUx86-32Intel1995-10-012000-12-01350 nm
0.35 μm
3.5e-4 mm
, 250 nm
0.25 μm
2.5e-4 mm
NetBurstCPUx86-32, x86-64Intel2000-11-202006-04-01180 nm
0.18 μm
1.8e-4 mm
MercedCPUIA-64Intel2001-06-01180 nm
0.18 μm
1.8e-4 mm
1
McKinleyCPUIA-64Intel2002-07-08180 nm
0.18 μm
1.8e-4 mm
1, 2
Pentium MCPUx86-16, x86-32Intel2003-01-012005-01-01130 nm
0.13 μm
1.3e-4 mm
, 90 nm
0.09 μm
9.0e-5 mm
MadisonCPUIA-64Intel2003-06-30130 nm
0.13 μm
1.3e-4 mm
1
Madison 9MCPUIA-64Intel2004-11-08130 nm
0.13 μm
1.3e-4 mm
1
Modified Pentium MCPUx86-16, x86-32Intel2006-01-012008-01-0165 nm
0.065 μm
6.5e-5 mm
CoreCPUx86-64Intel2006-04-012009-05-0165 nm
0.065 μm
6.5e-5 mm
MontecitoCPUIA-64Intel2006-07-1890 nm
0.09 μm
9.0e-5 mm
1, 2
PolarisCPUIntel2007-02-0165 nm
0.065 μm
6.5e-5 mm
809
MontvaleCPUIA-64Intel2007-10-3190 nm
0.09 μm
9.0e-5 mm
1, 2
PenrynCPUx86-64Intel2007-11-012008-09-0145 nm
0.045 μm
4.5e-5 mm
BonnellCPUx86-64Intel2008-03-022011-01-0145 nm
0.045 μm
4.5e-5 mm
1, 21619
NehalemCPUx86-64Intel2008-08-012010-03-0145 nm
0.045 μm
4.5e-5 mm
Rock CreekCPUx86Intel2009-12-0145 nm
0.045 μm
4.5e-5 mm
48
WestmereCPUx86-64Intel2010-01-012011-08-0132 nm
0.032 μm
3.2e-5 mm
TukwilaCPUIA-64Intel2010-02-0865 nm
0.065 μm
6.5e-5 mm
1, 2
Knights FerryCPUx86Intel2010-05-312011-01-0145 nm
0.045 μm
4.5e-5 mm
32
Sandy Bridge (client)CPUx86-64Intel2010-09-132012-11-0132 nm
0.032 μm
3.2e-5 mm
2, 41419
SaltwellCPUx86-64Intel2011-01-012013-01-0132 nm
0.032 μm
3.2e-5 mm
1, 216
Knights CornerCPUx86Intel2011-01-012013-01-0122 nm
0.022 μm
2.2e-5 mm
57, 60, 61
Ivy BridgeCPUx86-64Intel2011-05-042013-04-0122 nm
0.022 μm
2.2e-5 mm
PoulsonCPUIA-64Intel2012-11-0832 nm
0.032 μm
3.2e-5 mm
1, 2
SilvermontCPUx86-64Intel2013-01-012015-01-0122 nm
0.022 μm
2.2e-5 mm
1, 2, 4, 81214
HaswellCPUx86-64Intel2013-06-042015-01-0122 nm
0.022 μm
2.2e-5 mm
2, 4, 6, 8, 16, 10, 12, 14, 181419
BroadwellCPUx86-64Intel2014-10-0114 nm
0.014 μm
1.4e-5 mm
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 221419
AirmontCPUx86-64Intel2015-01-012017-01-0114 nm
0.014 μm
1.4e-5 mm
1, 2, 4, 81214
Skylake (client)CPUx86-64Intel2015-08-0514 nm
0.014 μm
1.4e-5 mm
2, 41419
Kaby LakeCPUx86-64Intel2016-08-3014 nm
0.014 μm
1.4e-5 mm
2, 41419
GoldmontCPUx86-64Intel2016-08-3014 nm
0.014 μm
1.4e-5 mm
2, 4, 8, 12, 161214
KittsonCPUIA-64Intel2017-01-0122 nm
0.022 μm
2.2e-5 mm
1, 2
Skylake (server)CPUx86-64Intel2017-05-0414 nm
0.014 μm
1.4e-5 mm
4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 281419
Coffee LakeCPUx86-64Intel, dell2017-10-0514 nm
0.014 μm
1.4e-5 mm
1419
Goldmont PlusCPUx86-64Intel2017-12-1114 nm
0.014 μm
1.4e-5 mm
2, 4
Knights MillCPUx86-16, x86-32, x86-64Intel2017-12-182019-08-0914 nm
0.014 μm
1.4e-5 mm
Palm CoveCPUx86-64Intel2018-01-0110 nm
0.01 μm
1.0e-5 mm
21419
Whiskey LakeCPUx86-64Intel2018-04-0141419
Amber LakeCPUx86-64Intel2018-04-0114 nm
0.014 μm
1.4e-5 mm
21419
Cannon LakeCPUx86-64Intel2018-05-1510 nm
0.01 μm
1.0e-5 mm
21419
LakefieldCPUx86-64Intel2019-01-0122 nm
0.022 μm
2.2e-5 mm
, 10 nm
0.01 μm
1.0e-5 mm
5
Cascade LakeCPUx86-64Intel2019-01-0114 nm
0.014 μm
1.4e-5 mm
2, 4, 6, 8, 10, 12, 16, 18, 20, 22, 24, 26, 28, 32, 48, 561419
TremontCPUx86-64Intel2019-01-0110 nm
0.01 μm
1.0e-5 mm
Snow RidgeCPUx86-64Intel2019-01-0110 nm
0.01 μm
1.0e-5 mm
Sunny CoveCPUx86-64Intel2019-01-012021-01-0110 nm
0.01 μm
1.0e-5 mm
2, 4, 8, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 401419
Ice Lake (client)CPUx86-64Intel2019-05-2710 nm
0.01 μm
1.0e-5 mm
2, 41419
Willow CoveCPUx86-64Intel2020-01-0110 nm
0.01 μm
1.0e-5 mm
2, 4, 6, 81419
Cooper LakeCPUx86-64Intel2020-06-1814 nm
0.014 μm
1.4e-5 mm
28, 24, 20, 18, 16, 81419
Tiger LakeCPUx86-64Intel2020-09-0210 nm
0.01 μm
1.0e-5 mm
2, 4, 6, 81419
GracemontCPUx86-64Intel2021-01-0110 nm
0.01 μm
1.0e-5 mm
Alder LakeCPUx86-64Intel2021-01-0110 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
16, 14, 10, 6
Rocket LakeCPUx86-64Intel2021-03-1614 nm
0.014 μm
1.4e-5 mm
4, 6, 81419
Ice Lake (server)CPUx86-64Intel2021-04-018, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 401419
Golden CoveCPUx86-64Intel2021-11-0410 nm
0.01 μm
1.0e-5 mm
Ocean CoveCPUx86-64Intel2022-01-01
Raptor LakeCPUx86-64Intel2022-09-277 nm
0.007 μm
7.0e-6 mm
24, 16, 8
Meteor LakeCPUx86-64Intel2023-01-01
Sapphire RapidsCPUx86-64Intel2023-01-017 nm
0.007 μm
7.0e-6 mm
Emerald RapidsCPUx86-64Intel2023-01-017 nm
0.007 μm
7.0e-6 mm
Granite RapidsCPUx86-64Intel2024-01-01120, 80, 40
Sierra ForestCPUx86-64Intel2024-06-04
Diamond RapidsCPUx86-64Intel2025-01-01

Newest models[edit]

TSMC N3B (3 nm)
  • Lunar Lake (hybrid) • Lion Cove (P)/Skymont (E) • Ultra 200V • 2024-09
  • Arrow Lake (hybrid) • Ultra Series 2 • 2024-10 (desktop)/2025-01 (mobile)
Intel 18A
  • Panther Lake (hybrid) • Cougar Cove (P)/Darkmont (E) • Ultra 300 • 2025
  • Diamond Rapids • Panther Cove X (Mountain Stream) • 2025
Intel 18A (or TSMC 2 nm)

GPU Microarchitectures[edit]

Intel GPU Microarchitectures
GeneralDetails
µarchIntroductionPhase-outProcess
Gen11998-01-01
Gen22002-01-01
Gen32004-01-01
Gen3.52005-01-0190 nm
0.09 μm
9.0e-5 mm
Gen42006-01-0165 nm
0.065 μm
6.5e-5 mm
Gen52008-06-0345 nm
0.045 μm
4.5e-5 mm
Larrabee2008-08-122010-01-0132 nm
0.032 μm
3.2e-5 mm
, 45 nm
0.045 μm
4.5e-5 mm
Gen5.752010-01-0145 nm
0.045 μm
4.5e-5 mm
Gen62010-09-1332 nm
0.032 μm
3.2e-5 mm
Gen72011-05-0422 nm
0.022 μm
2.2e-5 mm
Gen7.52013-06-0422 nm
0.022 μm
2.2e-5 mm
Gen82014-10-0114 nm
0.014 μm
1.4e-5 mm
Gen92015-08-0514 nm
0.014 μm
1.4e-5 mm
Gen9.52016-08-3014 nm
0.014 μm
1.4e-5 mm
Gen112018-01-0110 nm
0.01 μm
1.0e-5 mm
Gen102018-01-0110 nm
0.01 μm
1.0e-5 mm
Arctic Sound2020-01-0110 nm
0.01 μm
1.0e-5 mm
Gen122020-01-0110 nm
0.01 μm
1.0e-5 mm
Jupiter Sound2022-01-0110 nm
0.01 μm
1.0e-5 mm

Intel Core Lines[edit]

See also: Intel, Core, Intel Atom, Lake, and intel/roadmap
Intel Core Roadmap
Fab
process 		Micro-
architecture 		Code
names 		Core
Gen 		Scalable
(Xeon)
Gen 		Release
date 		Processors
Mobile Desktop Enthusiast/
Workstation 		1P/2P
Server 		4P/8P
Server
180 nm NetBurst Willamette — 2000-11 — Willamette — Foster Foster MP
130 nm
90 nm 		Northwood
Prescott 		2002-01 Northwood
Mobile 		Northwood
Prescott 		Northwood-XE
Prescott 2M-XE 		Prestonia
Gallatin 		Gallatin
130 nm
90 nm
90 nm
65 nm 		Pentium M
.
.
Pentium D 		Banias
Dothan
Smithfield
Presler 		2004-02 Banias
Dothan 		Smithfield
Presler 		Smithfield-XE
Presler-XE 		Nocona
Irwindale
Paxville 		Potomac
Cranford
Paxville
65 nm Modified
Pentium M 		Yonah
Cedar Mill 		1
(Yonah) 		— 2006-01 Yonah Cedar Mill - Dempsey
Sossaman 		Tulsa
(Xeon)
Intel Core Merom 2 2006-07 Merom
Merom-L 		Conroe Kentsfield Woodcrest
Clovertown 		Tigerton
45 nm Penryn 2007-11 Penryn Wolfdale Yorkfield Harpertown Dunnington
Nehalem Nehalem 1
(Core i) 		2008-11 Clarksfield Lynnfield Bloomfield Gainestown Beckton
32 nm Westmere 2010-01 Arrandale Clarkdale Gulftown Westmere EP Westmere EX
Sandy Bridge Sandy Bridge 2 2011-01 Sandy Bridge M Sandy Bridge Sandy Bridge E Sandy Bridge EP —
22 nm Ivy Bridge 3 2012-04 Ivy Bridge M Ivy Bridge Ivy Bridge E Ivy Bridge EP Ivy Bridge EX
Haswell Haswell 4 2013-06 Haswell H
Haswell MB
Haswell ULP
Haswell ULX 		Haswell DT Haswell E Haswell EP Haswell EX
Devil's Canyon 2014-06 — Haswell DT —
14 nm Broadwell Broadwell 5 2014-09 Broadwell H
Broadwell U
Broadwell Y 		Broadwell DT
Broadwell DE 		Broadwell E Broadwell EP
(Xeon E5 v4) 		Broadwell EX
(Xeon E7 v4)
Skylake Skylake 6 Xeon 1 2015-08 Skylake H
Skylake U
Skylake Y 		Skylake DT
Skylake S 		Skylake W
Skylake X 		Skylake SP
(formerly Skylake-EP/EX)
(Xeon Gold, Platinum)
Kaby Lake Kaby Lake 7 / 8 — 2016-10 Kaby Lake G
Kaby Lake H
Kaby Lake U
Kaby Lake Y 		Kaby Lake S Kaby Lake X —
Coffee Lake Coffee Lake 8 / 9 2017-10 Coffee Lake B
Coffee Lake H
Coffee Lake U 		Coffee Lake S Coffee Lake W Coffee Lake
(Xeon E) 		—
Whiskey Lake Whiskey Lake 8 2018-08 Whiskey Lake U — —
Amber Lake Amber Lake 8 / 10 Amber Lake Y
Cascade Lake Cascade Lake — Xeon 2 2019-04 — Cascade Lake W
Cascade Lake X 		Cascade Lake AP
Cascade Lake SP (Xeon)
Comet Lake Comet Lake 10 — 2019-09 Comet Lake H
Comet Lake Y
Comet Lake U 		Comet Lake S Comet Lake W —
Cooper Lake Cooper Lake — Xeon 3 2020-06 — Cooper Lake SP
Rocket Lake Cypress Cove 11 — 2021-03 — Rocket Lake SP Rocket Lake W Rocket Lake
(Xeon E) 		—
10 nm Cannon Lake Palm Cove 8 2018-05 Cannon Lake U — —
Ice Lake
(client)
(server) 		Sunny Cove
.
.
+ 4x Tremont 		10 Xeon 3 2019-09
(client)
2021-04
(server) 		Ice Lake U
Ice Lake Y 		— Ice Lake W Ice Lake SP —
Lakefield
(hybrid)
(Foveros) 		— — 2020-06 Lakefield —
Tiger Lake Willow Cove 11 2020-09 Tiger Lake-H
Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4 		—
Intel 7 nm Alder Lake
(hybrid) 		Golden Cove (P)
Gracemont (E) 		12 2021-11 Alder Lake-H
Alder Lake-HX
Alder Lake-U
Alder Lake M 		Alder Lake S Alder Lake P —
Sapphire Rapids — Xeon 4 2023-01 — Sapphire
Rapids-WS 		Sapphire
Rapids-SP/HBM
(Xeon Max) 		Sapphire
Rapids-SP
Raptor Lake
(hybrid) 		Raptor Cove (P)
Gracemont (E) 		13 / 14 /
Series
1 / 2 		— 2022-10 Raptor Lake-HX
Raptor Lake-PX
Raptor Lake U 		Raptor Lake S Raptor Lake H
Raptor Lake P 		Raptor Lake
(Xeon E) 		—
Emerald Rapids — Xeon 5 2023-12 — Emerald
Rapids-SP
Intel 4 nm Meteor Lake
(hybrid) 		Redwood Cove (P)
Crestmont (E) 		Ultra
Series 1 		— 2023-12 Meteor Lake-H
Meteor Lake-U 		— —
Intel 3 nm Granite Rapids — Xeon 6 2024-09 — Granite Rapids-AP
Granite Rapids-SP 		—
TSMC N3B Lunar Lake
(hybrid) 		Lion Cove (P)
Skymont (E) 		Ultra
200V 		— 2024-09 Lunar Lake-V — —
Arrow Lake
(hybrid) 		Ultra
200
Series 2 		2024-10
(desktop)
2025-01
(mobile) 		Arrow Lake-H
Arrow Lake-HX
Arrow Lake-U 		Arrow Lake-S — —
Intel 18A Panther Lake
(hybrid) 		Cougar Cove (P)
Darkmont (E) 		Ultra
300 		2025 Panther Lake-H
Panther Lake-HL
Panther Lake-U
Panther Lake-UL 		 ? — —
Diamond Rapids Panther Cove X
(Mountain Stream) 		—  ? 2025 — — —
TBA
(TSMC
2 nm or
Intel 18A
Intel 14A) 		Wildcat Lake
(hybrid) 		Cougar Cove (P)
Darkmont (LPE) 		— 2025 — TBA TBA — —
Nova Lake
(hybrid) 		Coyote Cove (P)
Arctic Wolf (E) 		— 2026 — TBA TBA — —
Razer Lake
(hybrid) 		— 2027 — TBA TBA — —

Intel Mainstream CPU Generations comparison[edit]

Intel CPU
family 		Processor
process 		Processor
architecture 		Graphics
architecture 		Processors
cores/threads 		Platform Memory support PCIe support Launch
Alder Lake
(12th Gen) 		Intel 7 Golden Cove (P-Core)
Gracemont (E-Core) 		HD 700 Series 16/24 LGA 1700/1800 DDR5 / DDR4 PCIe Gen 5.0 2021
Raptor Lake
(13th Gen) 		Intel 7 Raptor Cove (P-Core)
Gracemont (E-Core) 		HD 700 Series 24/32 LGA 1700/1800 DDR5 / DDR4 PCIe Gen 5.0 2022
Raptor Lake
Refresh (14th Gen) 		Intel 7 Raptor Cove (P-Core)
Gracemont (E-Core) 		HD 700 Series 24/32 LGA 1700/1800 DDR5 / DDR4 PCIe Gen 5.0 2023
Meteor Lake
(Core Ultra 100) 		Intel 4 Redwood Cove (P-Core)
Crestmont (E-Core) 		Xe1 (Alchemist) 22/28 LGA 1851 DDR5 PCIe Gen 5.0 2024
Arrow Lake
(Core Ultra 200) 		TSMC N3B Lion Cove (P-Core)
Skymont (E-Core) 		Xe1 (Alchemist) 24/24 LGA 1851 DDR5 PCIe Gen 5.0 2024
Arrow Lake
Refresh (TBD) 		TSMC N3B ? Lion Cove (P-Core)
Skymont (E-Core) 		Xe1 (Alchemist) 24/24 LGA 1851 DDR5 PCIe Gen 5.0 2025
Lunar Lake
(Core Ultra 200V) 		Intel 18A Lion Cove (P-Core)
Skymont (E-Core) 		Xe2 (Battlemage) 8/8 ? LGA 1851 ? DDR5 PCIe Gen 5.0 ? 2024
Panther Lake
(Core Ultra 300) 		Intel 18A Cougar Cove (P-Core)
Skymont (E-Core) 		Xe3 (Celestial) 16/16 LGA 1851 ? DDR5 PCIe Gen 5.0 ? 2025
Wildcat Lake
(Core Ultra 300?) 		Intel 18A Cougar Cove (P-Core)
Darkmont (E-Core) 		Xe3 (Celestial) 16/32 LGA 1851 ? DDR5 PCIe Gen 6.0 ? 2025
Nova Lake
(Core Ultra 400?) 		TBA Coyote Cove (P-Core)
Arctic Wolf (E-Core) 		Xe4 ("Druid") ? 16(P)/32(E) ? TBA DDR5 ? PCIe Gen 6.0 ? 2026
Razer Lake
(Core Ultra 500?) 		TBA TBA TBA TBA TBA TBA TBA 2027 ?

Many-core[edit]

Under construction icon-blue.svg This article is a work in progress!

Initial effort & Polaris[edit]

Intel actual large effort research into the area of many-core started after the February 2004 Intel Developer Forum following Pradeep Dubey famous keynote titled "The Era of Tera." Around the 2004-2005 Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the Tera-scale Computing Research Program which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.

The first product to come directly from that project was Polaris, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a mesh topology. Fabricated on a 65 nm process, the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. 3D stacked SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 teraFLOPS of sustained performance.

Larrabee[edit]

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