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In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | ||
+ | |||
+ | == Subsidiaries == | ||
+ | * [[Barefoot Networks]] | ||
+ | * [[Movidius]] | ||
+ | * [[Nervana]] | ||
+ | * [[Mobileye]] | ||
== Find Chip == | == Find Chip == | ||
Line 73: | Line 79: | ||
* {{intel|Mobile Pentium II}} | * {{intel|Mobile Pentium II}} | ||
* {{intel|Pentium}} | * {{intel|Pentium}} | ||
+ | * {{intel|Pentium (2009)}} | ||
* {{intel|Pentium 4}} | * {{intel|Pentium 4}} | ||
* {{intel|Pentium 4 EE}} | * {{intel|Pentium 4 EE}} | ||
Line 78: | Line 85: | ||
* {{intel|Pentium D}} | * {{intel|Pentium D}} | ||
* {{intel|Pentium EE}} | * {{intel|Pentium EE}} | ||
+ | * {{intel|Pentium Gold}} | ||
* {{intel|Pentium II}} | * {{intel|Pentium II}} | ||
* {{intel|Pentium III}} | * {{intel|Pentium III}} | ||
Line 87: | Line 95: | ||
* {{intel|Pentium MMX}} | * {{intel|Pentium MMX}} | ||
* {{intel|Pentium Pro}} | * {{intel|Pentium Pro}} | ||
+ | * {{intel|Pentium Silver}} | ||
* {{intel|PXA}} | * {{intel|PXA}} | ||
* {{intel|Quark}} | * {{intel|Quark}} | ||
Line 92: | Line 101: | ||
* {{intel|Xeon Bronze}} | * {{intel|Xeon Bronze}} | ||
* {{intel|Xeon D}} | * {{intel|Xeon D}} | ||
+ | * {{intel|Xeon E}} | ||
* {{intel|Xeon E3}} | * {{intel|Xeon E3}} | ||
* {{intel|Xeon E5}} | * {{intel|Xeon E5}} | ||
Line 101: | Line 111: | ||
}} | }} | ||
− | == List of | + | == List of architectures == |
{{collist | {{collist | ||
| count = 1 | | count = 1 | ||
| | | | ||
− | * {{ | + | * {{\\|MCS-8/ISA|MCS-8 (8008)}} |
+ | * [[x86]] | ||
+ | * {{\\|Configurable Spatial Accelerator}} (CSA) | ||
+ | * {{\\|Programmable Unified Memory Architecture}} (PUMA) | ||
}} | }} | ||
Line 121: | Line 134: | ||
* {{intel|NetBurst|l=arch}} | * {{intel|NetBurst|l=arch}} | ||
* {{intel|Enhanced NetBurst|l=arch}} | * {{intel|Enhanced NetBurst|l=arch}} | ||
− | * {{intel|Core|l=arch}} | + | }} |
− | * {{intel|Penryn|l=arch}} | + | |
− | * {{intel|Nehalem|l=arch}} | + | |
− | * {{intel|Westmere|l=arch}} | + | {{collist |
− | * {{intel|Sandy Bridge|l=arch}} | + | | count = 4 |
− | * {{intel|Ivy Bridge|l=arch}} | + | | style= margin-left: 20px; |
− | * {{intel|Haswell|l=arch}} | + | | |
− | * {{intel|Broadwell|l=arch}} | + | '''Client SoC:''' |
− | * | + | * {{intel|Core (client)|l=arch}} |
+ | * {{intel|Penryn (client)|l=arch}} | ||
+ | * {{intel|Nehalem (client)|l=arch}} | ||
+ | * {{intel|Westmere (client)|l=arch}} | ||
+ | * {{intel|Sandy Bridge (client)|l=arch}} | ||
+ | * {{intel|Ivy Bridge (client)|l=arch}} | ||
+ | * {{intel|Haswell (client)|l=arch}} | ||
+ | * {{intel|Broadwell (client)|l=arch}} | ||
+ | * {{intel|Skylake (client)|l=arch}} | ||
* {{intel|Kaby Lake|l=arch}} | * {{intel|Kaby Lake|l=arch}} | ||
* {{intel|Coffee Lake|l=arch}} | * {{intel|Coffee Lake|l=arch}} | ||
− | * {{intel| | + | * {{intel|Whiskey Lake|l=arch}} |
− | * {{intel| | + | * {{intel|Amber Lake|l=arch}} |
− | * {{intel| | + | * {{intel|Comet Lake|l=arch}} |
+ | * {{intel|Keystone Lake|l=arch}} | ||
+ | * {{intel|Rocket Lake|l=arch}} | ||
+ | * {{intel|Cannon Lake|l=arch}} ("Skymont") | ||
+ | * {{intel|Ice Lake (client)|l=arch}} | ||
+ | * {{intel|Tiger Lake|l=arch}} | ||
+ | * {{intel|Alder Lake|l=arch}} | ||
+ | * {{intel|Raptor Lake|l=arch}} | ||
+ | * {{intel|Meteor Lake|l=arch}} | ||
+ | * {{intel|Arrow Lake|l=arch}} | ||
+ | * {{intel|Lunar Lake|l=arch}} | ||
+ | |||
}} | }} | ||
− | + | ||
+ | |||
{{collist | {{collist | ||
− | | count = | + | | count = 4 |
+ | | style= margin-left: 20px; | ||
+ | | | ||
+ | '''Server SoC:''' | ||
+ | * {{intel|Core (server)|l=arch}} | ||
+ | * {{intel|Penryn (server)|l=arch}} | ||
+ | * {{intel|Nehalem (server)|l=arch}} | ||
+ | * {{intel|Westmere (server)|l=arch}} | ||
+ | * {{intel|Sandy Bridge (server)|l=arch}} | ||
+ | * {{intel|Ivy Bridge (server)|l=arch}} | ||
+ | * {{intel|Haswell (server)|l=arch}} | ||
+ | * {{intel|Broadwell (server)|l=arch}} | ||
+ | * {{intel|Skylake (server)|l=arch}} | ||
+ | * {{intel|Cascade Lake|l=arch}} | ||
+ | * {{intel|Cooper Lake|l=arch}} | ||
+ | * {{intel|Ice Lake (server)|l=arch}} | ||
+ | * {{intel|Sapphire Rapids|l=arch}} | ||
+ | * {{intel|Emerald Rapids|l=arch}} | ||
+ | * {{intel|Granite Rapids|l=arch}} | ||
+ | * {{intel|Diamond Rapids|l=arch}} | ||
+ | }} | ||
+ | |||
+ | |||
+ | {{collist | ||
+ | | count = 4 | ||
+ | | style= margin-left: 20px; | ||
+ | | | ||
+ | '''Networking SoC:''' | ||
+ | * {{intel|Snow Ridge|l=arch}} | ||
+ | * {{intel|Tanner Ridge|l=arch}} | ||
+ | }} | ||
+ | |||
+ | |||
+ | {{collist | ||
+ | | count = 4 | ||
+ | | style= margin-left: 20px; | ||
+ | | | ||
+ | '''High-Perf (Big Cores):''' | ||
+ | * {{intel|Palm Cove|l=arch}} | ||
+ | * {{intel|Sunny Cove|l=arch}} | ||
+ | * {{intel|Willow Cove|l=arch}} | ||
+ | * {{intel|Golden Cove|l=arch}} | ||
+ | * {{intel|Ocean Cove|l=arch}} | ||
+ | }} | ||
+ | |||
+ | |||
+ | {{collist | ||
+ | | count = 4 | ||
+ | | style= margin-left: 20px; | ||
| | | | ||
+ | '''High-Efficiency (Small Cores)''' | ||
* {{intel|Bonnell|l=arch}} | * {{intel|Bonnell|l=arch}} | ||
* {{intel|Saltwell|l=arch}} | * {{intel|Saltwell|l=arch}} | ||
Line 146: | Line 228: | ||
* {{intel|Goldmont|l=arch}} | * {{intel|Goldmont|l=arch}} | ||
* {{intel|Goldmont Plus|l=arch}} | * {{intel|Goldmont Plus|l=arch}} | ||
+ | * {{intel|Tremont|l=arch}} | ||
+ | }} | ||
+ | |||
+ | '''MCU:''' | ||
+ | {{collist | ||
+ | | count = 1 | ||
+ | | | ||
+ | * {{intel|Lakemont|l=arch}} | ||
}} | }} | ||
+ | |||
'''ULP ([[ARM]]):''' | '''ULP ([[ARM]]):''' | ||
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
| | | | ||
+ | * .. From [[DEC]] | ||
* {{intel|XScale|l=arch}} | * {{intel|XScale|l=arch}} | ||
* {{intel|XScale 2|l=arch}} | * {{intel|XScale 2|l=arch}} | ||
Line 157: | Line 249: | ||
* Continued by [[Marvell]] .. | * Continued by [[Marvell]] .. | ||
}} | }} | ||
+ | |||
+ | |||
'''Server (EPIC) ([[Itanium]]):''' | '''Server (EPIC) ([[Itanium]]):''' | ||
{{collist | {{collist | ||
Line 177: | Line 271: | ||
* {{intel|Kittson|l=arch}} | * {{intel|Kittson|l=arch}} | ||
}} | }} | ||
− | '''{{ | + | '''[[Many-core]]:''' |
+ | {{collist | ||
+ | | count = 2 | ||
+ | | style= margin-left: 20px; | ||
+ | | | ||
+ | '''Early Research:''' | ||
+ | * {{intel|Polaris|l=arch}} | ||
+ | * {{intel|Larrabee|l=arch}} | ||
+ | * {{intel|Rock Creek|l=arch}} | ||
+ | }} | ||
+ | {{clear}} | ||
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
+ | | style= margin-left: 20px; | ||
| | | | ||
− | + | '''{{intel|MIC Architectures}}:''' | |
− | * {{intel|Knights Ferry|l=arch}} | + | * {{intel|Knights Ferry|l=arch}} (Aubrey Isle) |
− | * {{intel|Knights Corner|l=arch}} | + | * {{intel|Knights Corner|l=arch}} (Angel Isle) |
* {{intel|Knights Landing|l=arch}} | * {{intel|Knights Landing|l=arch}} | ||
+ | * {{intel|Knights Mill|l=arch}} | ||
* {{intel|Knights Hill|l=arch}} | * {{intel|Knights Hill|l=arch}} | ||
− | * {{intel|Knights | + | * {{intel|Knights Peak|l=arch}} |
+ | }} | ||
+ | '''Heterogeneous:''' | ||
+ | {{collist | ||
+ | | count = 1 | ||
+ | | | ||
+ | * {{intel|Lakefield|l=arch}} | ||
+ | * {{intel|Ryefield|l=arch}} | ||
}} | }} | ||
+ | |||
+ | |||
'''GPU:''' | '''GPU:''' | ||
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
− | | | + | | style= margin-left: 20px; |
| | | | ||
+ | '''Integrated:''' | ||
* {{intel|Gen1|l=arch}} | * {{intel|Gen1|l=arch}} | ||
* {{intel|Gen2|l=arch}} | * {{intel|Gen2|l=arch}} | ||
Line 208: | Line 324: | ||
* {{intel|Gen10|l=arch}} | * {{intel|Gen10|l=arch}} | ||
* {{intel|Gen11|l=arch}} | * {{intel|Gen11|l=arch}} | ||
+ | * {{intel|Gen12|l=arch}} | ||
+ | }} | ||
+ | {{clear}} | ||
+ | {{collist | ||
+ | | count = 1 | ||
+ | | style= margin-left: 20px; | ||
+ | | | ||
+ | '''Discrete:''' | ||
+ | * {{intel|Arctic Sound|l=arch}} | ||
+ | * {{intel|Jupiter Sound|l=arch}} | ||
+ | }} | ||
+ | |||
+ | '''Artificial Intelligence:''' | ||
+ | {{collist | ||
+ | | count = 3 | ||
+ | | style= margin-left: 20px; | ||
+ | | | ||
+ | '''Training:''' | ||
+ | * {{intel|Lake Crest|l=arch}} | ||
+ | * {{intel|Spring Crest|l=arch}} | ||
+ | }} | ||
+ | {{clear}} | ||
+ | {{collist | ||
+ | | count = 3 | ||
+ | | style= margin-left: 20px; | ||
+ | | | ||
+ | '''Inference:''' | ||
+ | * {{intel|Spring Hill|l=arch}} | ||
}} | }} | ||
Line 214: | Line 358: | ||
| count = 1 | | count = 1 | ||
| | | | ||
+ | '''Neuromorphic:''' | ||
+ | * {{intel|Loihi}} | ||
+ | * {{intel|Loihi 2}} | ||
+ | '''Artificial Intelligence''' | ||
+ | * {{intel|ETANN}} | ||
+ | '''Quantum:''' | ||
+ | * {{intel|Surface-17}} | ||
+ | * {{intel|Tangle Lake}} | ||
+ | '''RAM:''' | ||
* {{intel|3101}} | * {{intel|3101}} | ||
* {{intel|1103}} | * {{intel|1103}} | ||
+ | }} | ||
+ | |||
+ | == Architectural Concepts == | ||
+ | {{collist | ||
+ | | count = 1 | ||
+ | | | ||
+ | * {{\\|Mesh Interconnect Architecture}} | ||
+ | * {{\\|Ring Interconnect Architecture}} | ||
}} | }} | ||
Line 233: | Line 394: | ||
| count = 2 | | count = 2 | ||
| | | | ||
− | * {{ | + | * {{\\|CPUID}} |
− | * {{ | + | * {{\\|CNVi}} |
− | * {{ | + | * {{\\|Flexpoint}} |
− | * {{ | + | * {{\\|Frequency Behavior}} |
+ | * {{\\|Innovation Engine}} (IE) | ||
+ | * {{\\|Management Engine}} (ME) | ||
+ | * {{\\|Process-Architecture-Optimization}} (PAO) | ||
+ | * {{\\|Process Technology}} | ||
+ | * {{\\|Tick-Tock}} | ||
+ | }} | ||
+ | |||
+ | == Technologies == | ||
+ | {{collist | ||
+ | | count = 2 | ||
+ | | | ||
+ | * {{\\|Dynamic Tuning}} | ||
+ | * {{\\|Hyper Scaling}} | ||
+ | * {{\\|Speed Select Technology}} (SST) | ||
+ | * {{\\|Turbo Boost Technology}} (TBT) | ||
+ | * {{\\|Thermal Velocity Boost}} (TVB) | ||
+ | * {{\\|DL Boost}} | ||
+ | }} | ||
+ | |||
+ | == Packaging Technologies == | ||
+ | {{collist | ||
+ | | count = 2 | ||
+ | | | ||
+ | * {{\\|Foveros}} | ||
+ | * {{\\|EMIB}} | ||
}} | }} | ||
== Documents == | == Documents == | ||
− | + | See {{\\|Documents}}. | |
[[Category:intel]] | [[Category:intel]] |
Latest revision as of 00:03, 2 October 2022
Intel | |||||||||
![]() | |||||||||
Type | Public | ||||||||
Founded | July 18, 1968 Mountain View, California | ||||||||
Founder | Gordon Moore Robert Noyce Andrew Grove | ||||||||
Headquarters | Santa Clara, California | ||||||||
Website | http://www.intel.com | ||||||||
|
Intel Corporation is an American semiconductor company. While most notably known for their development of microprocessors and x86, Intel also designs and manufactures other integrated circuits including flash memory, network interface controllers, GPUs, chipsets, motherboards, and computers.
In addition to x86, Intel used to also design and manufacture ARM-based chips as well as embed ARC-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
Contents
Subsidiaries[edit]
Find Chip[edit]
- By S-Spec
List of processor families[edit]
- 3000
- 80186
- 80188
- 80286
- 80376
- 80386
- 80486
- Atom
- Atom x3
- Atom x5
- Atom x7
- Celeron
- Celeron D
- Celeron M
- Core 2 Duo
- Core 2 Extreme
- Core 2 Quad
- Core 2 Quad Extreme
- Core 2 Solo
- Core Duo
- Core i3
- Core i5
- Core i7
- Core i7 EE
- Core i9
- Core M
- Core Solo
- EP80579
- i860
- i960
- iAPX432
- Itanium
- Itanium 2
- MCS-4
- MCS-40
- MCS-48
- MCS-51
- MCS-8
- MCS-80
- MCS-85
- MCS-86
- MCS-88
- MCS-96
- Mobile Pentium II
- Pentium
- Pentium (2009)
- Pentium 4
- Pentium 4 EE
- Pentium 4-M
- Pentium D
- Pentium EE
- Pentium Gold
- Pentium II
- Pentium III
- Pentium III Mobile
- Pentium III Xeon
- Pentium II Mobile
- Pentium II Xeon
- Pentium M
- Pentium MMX
- Pentium Pro
- Pentium Silver
- PXA
- Quark
- Xeon
- Xeon Bronze
- Xeon D
- Xeon E
- Xeon E3
- Xeon E5
- Xeon E7
- Xeon Gold
- Xeon Platinum
- Xeon Silver
- Xeon W
List of architectures[edit]
List of microarchitectures[edit]
Mainstream (x86):
Client SoC:
- Core (client)
- Penryn (client)
- Nehalem (client)
- Westmere (client)
- Sandy Bridge (client)
- Ivy Bridge (client)
- Haswell (client)
- Broadwell (client)
- Skylake (client)
- Kaby Lake
- Coffee Lake
- Whiskey Lake
- Amber Lake
- Comet Lake
- Keystone Lake
- Rocket Lake
- Cannon Lake ("Skymont")
- Ice Lake (client)
- Tiger Lake
- Alder Lake
- Raptor Lake
- Meteor Lake
- Arrow Lake
- Lunar Lake
Server SoC:
Networking SoC:
High-Perf (Big Cores):
High-Efficiency (Small Cores)
MCU:
ULP (ARM):
Server (EPIC) (Itanium):
Early Research:
- Knights Ferry (Aubrey Isle)
- Knights Corner (Angel Isle)
- Knights Landing
- Knights Mill
- Knights Hill
- Knights Peak
Heterogeneous:
GPU:
Integrated:
Discrete:
Artificial Intelligence:
Training:
Inference:
Other Chips[edit]
Neuromorphic:
Artificial Intelligence
Quantum:
RAM:
Architectural Concepts[edit]
Other[edit]
Other topics[edit]
Technologies[edit]
Packaging Technologies[edit]
Documents[edit]
See Documents.
company type | public + |
founded | July 18, 1968 + |
founded location | Mountain View, California + |
founder | Gordon Moore +, Robert Noyce + and Andrew Grove + |
full page name | intel + |
headquarters | Santa Clara, California + |
instance of | semiconductor company + |
name | Intel + |
website | http://www.intel.com + |
wikidata id | Q248 + |