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{{intel title|Microarchitectures}}
 
{{intel title|Microarchitectures}}
 
Below is a list of [[Intel]] [[microarchitectures]]:
 
Below is a list of [[Intel]] [[microarchitectures]]:
−
== Microarchitectures ==
+
== CPU Microarchitectures ==
 +
<table class="wikitable sortable">
 +
<tr><th colspan="12" style="background:#D6D6FF;">Intel CPU Microarchitectures</th></tr>
 +
<tr><th colspan="3">General</th><th colspan="5">Details</th></tr>
 +
<tr><th>µarch</th><th>Introduction</th><th>Phase-out</th><th>[[technology node|Process]]</th><th>Cores</th><th colspan="3">Pipeline</th></tr>
 
{{#ask:
 
{{#ask:
 +
[[Category:cpu microarchitectures by intel]]
 
  [[instance of::microarchitecture]]
 
  [[instance of::microarchitecture]]
 
  [[designer::Intel]]  
 
  [[designer::Intel]]  
 +
|?full page name
 
  |?name
 
  |?name
−
  |?first launched
+
  |?first launched#ISO
−
  |?phase-out
+
  |?phase-out#ISO
 
  |?process
 
  |?process
 
  |?core count
 
  |?core count
 
  |?pipeline stages
 
  |?pipeline stages
−
  |format=count
+
|?pipeline stages (min)
−
  |sep=,
+
|?pipeline stages (max)
 +
|sort=first launched
 +
|order=ascending
 +
  |format=template
 +
  |template=proc table 2
 +
|userparam=9
 +
|valuesep=,
 +
|mainlabel=-
 
}}
 
}}
 +
</table>
 +
 +
== GPU Microarchitectures ==
 +
<table class="wikitable sortable">
 +
<tr><th colspan="12" style="background:#D6D6FF;">Intel GPU Microarchitectures</th></tr>
 +
<tr><th colspan="3">General</th><th colspan="5">Details</th></tr>
 +
<tr><th>µarch</th><th>Introduction</th><th>Phase-out</th><th>[[technology node|Process]]</th></tr>
 +
{{#ask:
 +
[[Category:gpu microarchitectures by intel]]
 +
[[instance of::microarchitecture]]
 +
[[designer::Intel]]
 +
|?full page name
 +
|?name
 +
|?first launched#ISO
 +
|?phase-out#ISO
 +
|?process
 +
|sort=first launched
 +
|order=ascending
 +
|format=template
 +
|template=proc table 2
 +
|userparam=5
 +
|valuesep=,
 +
|mainlabel=-
 +
}}
 +
</table>
 +
 +
== Many-core ==
 +
{{work-in-progress}}
 +
 +
=== Initial effort & Polaris ===
 +
Intel actual large effort research into the area of [[many-core]] started after the February 2004 [[Intel Developer Forum]] following Pradeep Dubey famous keynote titled "The Era of Tera." Around the [[2004]]-[[2005]] Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the {{intel|Tera-scale Computing Research Program}} which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.
 +
 +
The first product to come directly from that project was {{intel|Polaris|l=arch}}, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a [[mesh topology]]. Fabricated on a [[65 nm process]], the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. [[3D IC|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustained performance.
 +
 +
=== Larrabee ===
 +
{{empty section}}

Latest revision as of 19:59, 8 February 2022

Below is a list of Intel microarchitectures:

CPU Microarchitectures[edit]

... further results
Intel CPU Microarchitectures
GeneralDetails
µarchIntroductionPhase-outProcessCoresPipeline
803861984-03-011989-01-011,500 nm
1.5 μm
0.0015 mm
804861989-04-101995-01-011,000 nm
1 μm
0.001 mm
, 800 nm
0.8 μm
8.0e-4 mm
, 600 nm
0.6 μm
6.0e-4 mm
P51993-04-011995-10-01600 nm
0.6 μm
6.0e-4 mm
P61995-10-012000-12-01350 nm
0.35 μm
3.5e-4 mm
, 250 nm
0.25 μm
2.5e-4 mm
NetBurst2000-11-202006-04-01180 nm
0.18 μm
1.8e-4 mm
Merced2001-06-01180 nm
0.18 μm
1.8e-4 mm
1
McKinley2002-07-08180 nm
0.18 μm
1.8e-4 mm
1, 2
Pentium M2003-01-012005-01-01130 nm
0.13 μm
1.3e-4 mm
, 90 nm
0.09 μm
9.0e-5 mm
Madison2003-06-30130 nm
0.13 μm
1.3e-4 mm
1
Madison 9M2004-11-08130 nm
0.13 μm
1.3e-4 mm
1
Modified Pentium M2006-01-012008-01-0165 nm
0.065 μm
6.5e-5 mm
Core2006-04-012009-05-0165 nm
0.065 μm
6.5e-5 mm
Montecito2006-07-1890 nm
0.09 μm
9.0e-5 mm
1, 2
Polaris2007-02-0165 nm
0.065 μm
6.5e-5 mm
809
Montvale2007-10-3190 nm
0.09 μm
9.0e-5 mm
1, 2
Penryn2007-11-012008-09-0145 nm
0.045 μm
4.5e-5 mm
Bonnell2008-03-022011-01-0145 nm
0.045 μm
4.5e-5 mm
1, 21619
Nehalem2008-08-012010-03-0145 nm
0.045 μm
4.5e-5 mm
Rock Creek2009-12-0145 nm
0.045 μm
4.5e-5 mm
48
Westmere2010-01-012011-08-0132 nm
0.032 μm
3.2e-5 mm
Tukwila2010-02-0865 nm
0.065 μm
6.5e-5 mm
1, 2
Knights Ferry2010-05-312011-01-0145 nm
0.045 μm
4.5e-5 mm
32
Sandy Bridge (client)2010-09-132012-11-0132 nm
0.032 μm
3.2e-5 mm
2, 41419
Saltwell2011-01-012013-01-0132 nm
0.032 μm
3.2e-5 mm
1, 216
Knights Corner2011-01-012013-01-0122 nm
0.022 μm
2.2e-5 mm
57, 60, 61
Ivy Bridge2011-05-042013-04-0122 nm
0.022 μm
2.2e-5 mm
Poulson2012-11-0832 nm
0.032 μm
3.2e-5 mm
1, 2
Silvermont2013-01-012015-01-0122 nm
0.022 μm
2.2e-5 mm
1, 2, 4, 81214
Haswell2013-06-042015-01-0122 nm
0.022 μm
2.2e-5 mm
2, 4, 6, 8, 16, 10, 12, 14, 181419
Broadwell2014-10-0114 nm
0.014 μm
1.4e-5 mm
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 221419
Airmont2015-01-012017-01-0114 nm
0.014 μm
1.4e-5 mm
1, 2, 4, 81214
Skylake (client)2015-08-0514 nm
0.014 μm
1.4e-5 mm
2, 41419
Kaby Lake2016-08-3014 nm
0.014 μm
1.4e-5 mm
2, 41419
Goldmont2016-08-3014 nm
0.014 μm
1.4e-5 mm
2, 4, 8, 12, 161214
Kittson2017-01-0122 nm
0.022 μm
2.2e-5 mm
1, 2
Skylake (server)2017-05-0414 nm
0.014 μm
1.4e-5 mm
4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 281419
Coffee Lake2017-10-0514 nm
0.014 μm
1.4e-5 mm
1419
Goldmont Plus2017-12-1114 nm
0.014 μm
1.4e-5 mm
2, 4
Knights Mill2017-12-182019-08-0914 nm
0.014 μm
1.4e-5 mm
Palm Cove2018-01-0110 nm
0.01 μm
1.0e-5 mm
21419
Whiskey Lake2018-04-0141419
Amber Lake2018-04-0114 nm
0.014 μm
1.4e-5 mm
21419
Cannon Lake2018-05-1510 nm
0.01 μm
1.0e-5 mm
21419
Lakefield2019-01-0122 nm
0.022 μm
2.2e-5 mm
, 10 nm
0.01 μm
1.0e-5 mm
5
Cascade Lake2019-01-0114 nm
0.014 μm
1.4e-5 mm
2, 4, 6, 8, 10, 12, 16, 18, 20, 22, 24, 26, 28, 32, 48, 561419
Tremont2019-01-0110 nm
0.01 μm
1.0e-5 mm
Snow Ridge2019-01-0110 nm
0.01 μm
1.0e-5 mm
Sunny Cove2019-01-012021-01-0110 nm
0.01 μm
1.0e-5 mm
2, 4, 8, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 401419
Ice Lake (client)2019-05-2710 nm
0.01 μm
1.0e-5 mm
2, 41419
Willow Cove2020-01-0110 nm
0.01 μm
1.0e-5 mm
2, 4, 6, 81419

GPU Microarchitectures[edit]

Intel GPU Microarchitectures
GeneralDetails
µarchIntroductionPhase-outProcess
Gen11998-01-01
Gen22002-01-01
Gen32004-01-01
Gen3.52005-01-0190 nm
0.09 μm
9.0e-5 mm
Gen42006-01-0165 nm
0.065 μm
6.5e-5 mm
Gen52008-06-0345 nm
0.045 μm
4.5e-5 mm
Larrabee2008-08-122010-01-0132 nm
0.032 μm
3.2e-5 mm
, 45 nm
0.045 μm
4.5e-5 mm
Gen5.752010-01-0145 nm
0.045 μm
4.5e-5 mm
Gen62010-09-1332 nm
0.032 μm
3.2e-5 mm
Gen72011-05-0422 nm
0.022 μm
2.2e-5 mm
Gen7.52013-06-0422 nm
0.022 μm
2.2e-5 mm
Gen82014-10-0114 nm
0.014 μm
1.4e-5 mm
Gen92015-08-0514 nm
0.014 μm
1.4e-5 mm
Gen9.52016-08-3014 nm
0.014 μm
1.4e-5 mm
Gen102018-01-0110 nm
0.01 μm
1.0e-5 mm
Gen112018-01-0110 nm
0.01 μm
1.0e-5 mm
Gen122020-01-0110 nm
0.01 μm
1.0e-5 mm
Arctic Sound2020-01-0110 nm
0.01 μm
1.0e-5 mm
Jupiter Sound2022-01-0110 nm
0.01 μm
1.0e-5 mm

Many-core[edit]

Under construction icon-blue.svg This article is a work in progress!

Initial effort & Polaris[edit]

Intel actual large effort research into the area of many-core started after the February 2004 Intel Developer Forum following Pradeep Dubey famous keynote titled "The Era of Tera." Around the 2004-2005 Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the Tera-scale Computing Research Program which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.

The first product to come directly from that project was Polaris, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a mesh topology. Fabricated on a 65 nm process, the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. 3D stacked SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 teraFLOPS of sustained performance.

Larrabee[edit]

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