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Difference between revisions of "intel"

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In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
 
In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.
 +
 +
== Subsidiaries ==
 +
* [[Barefoot Networks]]
 +
* [[Movidius]]
 +
* [[Nervana]]
 +
* [[Mobileye]]
  
 
== Find Chip ==
 
== Find Chip ==
Line 29: Line 35:
 
|
 
|
 
* {{intel|3000}}
 
* {{intel|3000}}
 +
* {{intel|8086}}
 
* {{intel|80186}}
 
* {{intel|80186}}
 
* {{intel|80188}}
 
* {{intel|80188}}
Line 35: Line 42:
 
* {{intel|80386}}
 
* {{intel|80386}}
 
* {{intel|80486}}
 
* {{intel|80486}}
−
* {{intel|Atom}}
+
 
 +
* {{intel|MCS-4}}
 +
* {{intel|MCS-40}}
 +
* {{intel|MCS-48}}
 +
* {{intel|MCS-8}}
 +
* {{intel|MCS-80}}
 +
* {{intel|MCS-85}}
 +
* {{intel|MCS-86}}
 +
* {{intel|MCS-88}}
 +
* {{intel|MCS-96}}
 +
* {{intel|MCS-51}}
 +
* {{intel|MCS-151}}
 +
* {{intel|MCS-251}}
 +
 
 +
* {{intel|EP80579}}
 +
* {{intel|iAPX432}}
 +
* {{intel|i860}}
 +
* {{intel|i960}}
 +
 
 +
* '''{{intel|Atom}}'''
 
* {{intel|Atom x3}}
 
* {{intel|Atom x3}}
 
* {{intel|Atom x5}}
 
* {{intel|Atom x5}}
 
* {{intel|Atom x7}}
 
* {{intel|Atom x7}}
−
* {{intel|Celeron}}
+
 
 +
* '''{{intel|Celeron}}'''
 +
* {{intel|Celeron Dual Core}}
 
* {{intel|Celeron D}}
 
* {{intel|Celeron D}}
 
* {{intel|Celeron M}}
 
* {{intel|Celeron M}}
 +
 +
* '''{{intel|Core}}'''
 +
* {{intel|Core M}} • {{intel|Core X|X}}
 +
* {{intel|Core Solo}}
 +
* {{intel|Core Duo}}
 +
* {{intel|Core 2 Solo}}
 
* {{intel|Core 2 Duo}}
 
* {{intel|Core 2 Duo}}
 +
* {{intel|Core 2 Quad}} <!--(Extreme)-->
 
* {{intel|Core 2 Extreme}}
 
* {{intel|Core 2 Extreme}}
−
* {{intel|Core 2 Quad}}
 
−
* {{intel|Core 2 Quad Extreme}}
 
−
* {{intel|Core 2 Solo}}
 
−
* {{intel|Core Duo}}
 
 
* {{intel|Core i3}}
 
* {{intel|Core i3}}
 
* {{intel|Core i5}}
 
* {{intel|Core i5}}
−
* {{intel|Core i7}}
+
* {{intel|Core i7}} ({{intel|Core i7 EE|EE}})
−
* {{intel|Core i7 EE}}
 
 
* {{intel|Core i9}}
 
* {{intel|Core i9}}
−
* {{intel|Core M}}
+
* {{intel|Core Ultra}}
−
* {{intel|Core Solo}}
+
* {{intel|Core Ultra 3}}
−
* {{intel|EP80579}}
+
* {{intel|Core Ultra 5}}
−
* {{intel|i860}}
+
* {{intel|Core Ultra 7}}
−
* {{intel|i960}}
+
 
−
* {{intel|iAPX432}}
+
* '''{{intel|Quark}}'''
 
* {{intel|Itanium}}
 
* {{intel|Itanium}}
 
* {{intel|Itanium 2}}
 
* {{intel|Itanium 2}}
−
* {{intel|MCS-4}}
+
* {{intel|XScale}} (PXA)
−
* {{intel|MCS-40}}
+
 
−
* {{intel|MCS-48}}
+
* '''{{intel|Pentium}}'''
−
* {{intel|MCS-51}}
 
−
* {{intel|MCS-8}}
 
−
* {{intel|MCS-80}}
 
−
* {{intel|MCS-85}}
 
−
* {{intel|MCS-86}}
 
−
* {{intel|MCS-88}}
 
−
* {{intel|MCS-96}}
 
−
* {{intel|Mobile Pentium II}}
 
−
* {{intel|Pentium}}
 
 
* {{intel|Pentium (2009)}}
 
* {{intel|Pentium (2009)}}
−
* {{intel|Pentium 4}}
+
* {{intel|Pentium Gold}}
−
* {{intel|Pentium 4 EE}}
+
* {{intel|Pentium Silver}}
−
* {{intel|Pentium 4-M}}
 
 
* {{intel|Pentium D}}
 
* {{intel|Pentium D}}
 
* {{intel|Pentium EE}}
 
* {{intel|Pentium EE}}
−
* {{intel|Pentium Gold}}
+
* {{intel|Pentium M}}
 +
* {{intel|Pentium MMX}}
 +
* {{intel|Pentium Pro}}
 
* {{intel|Pentium II}}
 
* {{intel|Pentium II}}
 +
* {{intel|Mobile Pentium II|Pentium II Mobile}}
 +
* {{intel|Pentium II Xeon}}
 
* {{intel|Pentium III}}
 
* {{intel|Pentium III}}
 
* {{intel|Pentium III Mobile}}
 
* {{intel|Pentium III Mobile}}
 
* {{intel|Pentium III Xeon}}
 
* {{intel|Pentium III Xeon}}
−
* {{intel|Pentium II Mobile}}
+
* {{intel|Pentium 4}} (-M/EE) <!--
−
* {{intel|Pentium II Xeon}}
+
* {{intel|Pentium 4 EE}}
−
* {{intel|Pentium M}}
+
* {{intel|Pentium 4-M}} -->
−
* {{intel|Pentium MMX}}
+
 
−
* {{intel|Pentium Pro}}
+
* '''{{intel|Xeon}}'''
−
* {{intel|Pentium Silver}}
 
−
* {{intel|PXA}}
 
−
* {{intel|Quark}}
 
−
* {{intel|Xeon}}
 
−
* {{intel|Xeon Bronze}}
 
 
* {{intel|Xeon D}}
 
* {{intel|Xeon D}}
 
* {{intel|Xeon E}}
 
* {{intel|Xeon E}}
Line 99: Line 118:
 
* {{intel|Xeon E5}}
 
* {{intel|Xeon E5}}
 
* {{intel|Xeon E7}}
 
* {{intel|Xeon E7}}
 +
* {{intel|Xeon Bronze}}
 +
* {{intel|Xeon Silver}}
 
* {{intel|Xeon Gold}}
 
* {{intel|Xeon Gold}}
 
* {{intel|Xeon Platinum}}
 
* {{intel|Xeon Platinum}}
−
* {{intel|Xeon Silver}}
+
* {{intel|Xeon Scalable}}
−
* {{intel|Xeon W}}
+
* {{intel|Xeon W}} • {{intel|Xeon Phi}}
 
}}
 
}}
 +
<!--
 +
:• Intel • 3000 • 8088 • 80186 • 80188 • 80286 • 80386 • 80486 • 80860 • 80960
 +
:• MCS-4 • MCS-40 • MCS-8 • MCS-48 • MCS-80 • MCS-85 • MCS-86 • MCS-88 • MCS-96 • MCS-51 • MCS-151 • MCS-251
 +
:• iAPX 432 • iFX730 • iFX740 • iFX780 • iFX8160 • iPLD22 • iPLD610 • iPLD910 • H-EPLD
 +
:• Atom • Atom x3 • Atom x5 • Atom x7
 +
:• Celeron • Celeron D • Celeron M
 +
:• Core M • Core Solo • Core Duo • Core 2 Duo • Core i3 • Core i5 • Core i7
 +
:• Itanium • Itanium 2 • Quark • Timna • XScale
 +
:• Pentium • Pentium D • Pentium M • Pentium EE • Pentium II • Pentium III • Pentium 4
 +
:• Xeon • Xeon D • Xeon E3 • Xeon E5 • Xeon E7 • Xeon Phi
 +
-->
  
−
== List of instruction set architectures ==
+
== List of architectures ==
 
{{collist
 
{{collist
 
| count = 1
 
| count = 1
 
|
 
|
−
* {{intel|MCS-8/ISA|MCS-8 (8008)}}
+
* {{\\|MCS-8/ISA|MCS-8 (8008)}}
 +
* [[x86]]
 +
* {{\\|Configurable Spatial Accelerator}} (CSA)
 +
* {{\\|Programmable Unified Memory Architecture}} (PUMA)
 
}}
 
}}
  
Line 126: Line 161:
 
* {{intel|Enhanced NetBurst|l=arch}}
 
* {{intel|Enhanced NetBurst|l=arch}}
 
}}
 
}}
 +
  
 
{{collist
 
{{collist
Line 131: Line 167:
 
| style= margin-left: 20px;
 
| style= margin-left: 20px;
 
|
 
|
−
'''Client:'''
+
'''Client SoC:'''
 
* {{intel|Core (client)|l=arch}}
 
* {{intel|Core (client)|l=arch}}
 
* {{intel|Penryn (client)|l=arch}}
 
* {{intel|Penryn (client)|l=arch}}
Line 144: Line 180:
 
* {{intel|Coffee Lake|l=arch}}
 
* {{intel|Coffee Lake|l=arch}}
 
* {{intel|Whiskey Lake|l=arch}}
 
* {{intel|Whiskey Lake|l=arch}}
 +
* {{intel|Amber Lake|l=arch}}
 +
* {{intel|Comet Lake|l=arch}}
 +
* {{intel|Keystone Lake|l=arch}}
 +
* {{intel|Rocket Lake|l=arch}}
 
* {{intel|Cannon Lake|l=arch}} ("Skymont")
 
* {{intel|Cannon Lake|l=arch}} ("Skymont")
 
* {{intel|Ice Lake (client)|l=arch}}
 
* {{intel|Ice Lake (client)|l=arch}}
−
* {{intel|Tigerlake|l=arch}}
+
* {{intel|Tiger Lake|l=arch}}
 
* {{intel|Alder Lake|l=arch}}
 
* {{intel|Alder Lake|l=arch}}
 +
* {{intel|Raptor Lake|l=arch}}
 
* {{intel|Meteor Lake|l=arch}}
 
* {{intel|Meteor Lake|l=arch}}
 +
* {{intel|Lunar Lake|l=arch}}
 +
* {{intel|Arrow Lake|l=arch}}
 +
* {{intel|Panther Lake|l=arch}}
 +
* {{intel|Nova Lake|l=arch}}
 
}}
 
}}
 +
  
 
{{collist
 
{{collist
Line 155: Line 201:
 
| style= margin-left: 20px;
 
| style= margin-left: 20px;
 
|
 
|
−
'''Server:'''
+
'''Server SoC:'''
 
* {{intel|Core (server)|l=arch}}
 
* {{intel|Core (server)|l=arch}}
 
* {{intel|Penryn (server)|l=arch}}
 
* {{intel|Penryn (server)|l=arch}}
Line 166: Line 212:
 
* {{intel|Skylake (server)|l=arch}}
 
* {{intel|Skylake (server)|l=arch}}
 
* {{intel|Cascade Lake|l=arch}}
 
* {{intel|Cascade Lake|l=arch}}
 +
* {{intel|Cooper Lake|l=arch}}
 
* {{intel|Ice Lake (server)|l=arch}}
 
* {{intel|Ice Lake (server)|l=arch}}
 
* {{intel|Sapphire Rapids|l=arch}}
 
* {{intel|Sapphire Rapids|l=arch}}
 +
* {{intel|Emerald Rapids|l=arch}}
 
* {{intel|Granite Rapids|l=arch}}
 
* {{intel|Granite Rapids|l=arch}}
 +
* {{intel|Diamond Rapids|l=arch}}
 
}}
 
}}
  
−
'''ULP ([[x86]]):'''
+
 
 
{{collist
 
{{collist
−
| count = 2
+
| count = 4
 +
| style= margin-left: 20px;
 +
|
 +
'''High-Efficiency (Small Cores) Server SoC:'''
 +
* {{intel|Sierra Forest (server)|l=arch}}
 +
* {{intel|Clearwater Forest (server)|l=arch}}
 +
}}
 +
 
 +
 
 +
 
 +
{{collist
 +
| count = 4
 +
| style= margin-left: 20px;
 +
|
 +
'''Networking SoC:'''
 +
* {{intel|Snow Ridge|l=arch}}
 +
* {{intel|Tanner Ridge|l=arch}}
 +
}}
 +
 
 +
 
 +
{{collist
 +
| count = 4
 +
| style= margin-left: 20px;
 +
|
 +
'''High-Perf (Big Cores):'''
 +
* {{intel|Palm Cove|l=arch}}
 +
* {{intel|Sunny Cove|l=arch}}
 +
* {{intel|Willow Cove|l=arch}}
 +
* {{intel|Cypress Cove|l=arch}}
 +
* {{intel|Golden Cove|l=arch}}
 +
* {{intel|Raptor Cove|l=arch}}
 +
* {{intel|Redwood Cove|l=arch}}
 +
* {{intel|Lion Cove|l=arch}}
 +
* {{intel|Cougar Cove|l=arch}}
 +
* {{intel|Coyote Cove|l=arch}}
 +
* {{intel|Ocean Cove|l=arch}}
 +
}}
 +
 
 +
 
 +
{{collist
 +
| count = 4
 +
| style= margin-left: 20px;
 
|
 
|
 +
'''High-Efficiency (Small Cores)'''
 
* {{intel|Bonnell|l=arch}}
 
* {{intel|Bonnell|l=arch}}
 
* {{intel|Saltwell|l=arch}}
 
* {{intel|Saltwell|l=arch}}
Line 181: Line 272:
 
* {{intel|Goldmont|l=arch}}
 
* {{intel|Goldmont|l=arch}}
 
* {{intel|Goldmont Plus|l=arch}}
 
* {{intel|Goldmont Plus|l=arch}}
 +
* {{intel|Tremont|l=arch}}
 +
* {{intel|Gracemont|l=arch}}
 +
* {{intel|Crestmont|l=arch}}
 +
* {{intel|Skymont|l=arch}}
 +
* {{intel|Darkmont|l=arch}}
 
}}
 
}}
 +
 
'''MCU:'''
 
'''MCU:'''
 
{{collist
 
{{collist
Line 188: Line 285:
 
* {{intel|Lakemont|l=arch}}
 
* {{intel|Lakemont|l=arch}}
 
}}
 
}}
 +
 
'''ULP ([[ARM]]):'''
 
'''ULP ([[ARM]]):'''
 
{{collist
 
{{collist
Line 199: Line 297:
 
* Continued by [[Marvell]] ..
 
* Continued by [[Marvell]] ..
 
}}
 
}}
 +
 +
 
'''Server (EPIC) ([[Itanium]]):'''
 
'''Server (EPIC) ([[Itanium]]):'''
 
{{collist
 
{{collist
Line 219: Line 319:
 
* {{intel|Kittson|l=arch}}
 
* {{intel|Kittson|l=arch}}
 
}}
 
}}
−
'''{{intel|MIC Architectures}}:'''
+
'''[[Many-core]]:'''
 +
{{collist
 +
| count = 2
 +
| style= margin-left: 20px;
 +
|
 +
'''Early Research:'''
 +
* {{intel|Polaris|l=arch}}
 +
* {{intel|Larrabee|l=arch}}
 +
* {{intel|Rock Creek|l=arch}}
 +
}}
 +
{{clear}}
 
{{collist
 
{{collist
 
| count = 3
 
| count = 3
 +
| style= margin-left: 20px;
 
|
 
|
−
* {{intel|Larrabee|l=arch}}
+
'''{{intel|MIC Architectures}}:'''
−
* {{intel|Knights Ferry|l=arch}}
+
* {{intel|Knights Ferry|l=arch}} (Aubrey Isle)
−
* {{intel|Knights Corner|l=arch}}
+
* {{intel|Knights Corner|l=arch}} (Angel Isle)
 
* {{intel|Knights Landing|l=arch}}
 
* {{intel|Knights Landing|l=arch}}
 
* {{intel|Knights Mill|l=arch}}
 
* {{intel|Knights Mill|l=arch}}
Line 231: Line 342:
 
* {{intel|Knights Peak|l=arch}}
 
* {{intel|Knights Peak|l=arch}}
 
}}
 
}}
 +
'''Heterogeneous:'''
 +
{{collist
 +
| count = 1
 +
|
 +
* {{intel|Lakefield|l=arch}}
 +
* {{intel|Ryefield|l=arch}}
 +
}}
 +
 +
 
'''GPU:'''
 
'''GPU:'''
 
{{collist
 
{{collist
 
| count = 3
 
| count = 3
−
| width = 500px
+
| style= margin-left: 20px;
 
|
 
|
 +
'''Integrated:'''
 
* {{intel|Gen1|l=arch}}
 
* {{intel|Gen1|l=arch}}
 
* {{intel|Gen2|l=arch}}
 
* {{intel|Gen2|l=arch}}
Line 252: Line 373:
 
* {{intel|Gen11|l=arch}}
 
* {{intel|Gen11|l=arch}}
 
* {{intel|Gen12|l=arch}}
 
* {{intel|Gen12|l=arch}}
 +
}}
 +
{{clear}}
 +
{{collist
 +
| count = 1
 +
| style= margin-left: 20px;
 +
|
 +
'''Discrete:'''
 +
* {{intel|Arctic Sound|l=arch}}
 +
* {{intel|Jupiter Sound|l=arch}}
 +
}}
 +
 +
'''Artificial Intelligence:'''
 +
{{collist
 +
| count = 3
 +
| style= margin-left: 20px;
 +
|
 +
'''Training:'''
 +
* {{intel|Lake Crest|l=arch}}
 +
* {{intel|Spring Crest|l=arch}}
 +
}}
 +
{{clear}}
 +
{{collist
 +
| count = 3
 +
| style= margin-left: 20px;
 +
|
 +
'''Inference:'''
 +
* {{intel|Spring Hill|l=arch}}
 
}}
 
}}
  
Line 260: Line 408:
 
'''Neuromorphic:'''
 
'''Neuromorphic:'''
 
* {{intel|Loihi}}
 
* {{intel|Loihi}}
 +
* {{intel|Loihi 2}}
 
'''Artificial Intelligence'''
 
'''Artificial Intelligence'''
 
* {{intel|ETANN}}
 
* {{intel|ETANN}}
 
'''Quantum:'''
 
'''Quantum:'''
 
* {{intel|Surface-17}}
 
* {{intel|Surface-17}}
 +
* {{intel|Tangle Lake}}
 
'''RAM:'''
 
'''RAM:'''
 
* {{intel|3101}}
 
* {{intel|3101}}
Line 308: Line 458:
 
|
 
|
 
* {{\\|Dynamic Tuning}}
 
* {{\\|Dynamic Tuning}}
 +
* {{\\|Hyper Scaling}}
 +
* {{\\|Speed Select Technology}} (SST)
 
* {{\\|Turbo Boost Technology}} (TBT)
 
* {{\\|Turbo Boost Technology}} (TBT)
 
* {{\\|Thermal Velocity Boost}} (TVB)
 
* {{\\|Thermal Velocity Boost}} (TVB)
 +
* {{\\|DL Boost}}
 +
}}
 +
 +
== Packaging Technologies ==
 +
{{collist
 +
| count = 2
 +
|
 +
* {{\\|Foveros}}
 +
* {{\\|EMIB}}
 
}}
 
}}
  

Latest revision as of 17:01, 8 March 2025

Intel
Intel logo (2006-2020).svg
Type Public
Founded July 18, 1968
Mountain View, California
Founder Gordon Moore
Robert Noyce
Andrew Grove
Headquarters Santa Clara, California
Website http://www.intel.com
IC Identification
Logo Example Package
ic logo (intel).svg ic example (intel).svg
By Prefix • By Logo

Intel Corporation is an American semiconductor company. While most notably known for their development of microprocessors and x86, Intel also designs and manufactures other integrated circuits including flash memory, network interface controllers, GPUs, chipsets, motherboards, and computers.

In addition to x86, Intel used to also design and manufacture ARM-based chips as well as embed ARC-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.

Subsidiaries[edit]

Find Chip[edit]

List of processor families[edit]

List of architectures[edit]

List of microarchitectures[edit]

Mainstream (x86):


Client SoC:


Server SoC:


High-Efficiency (Small Cores) Server SoC:


Networking SoC:


High-Perf (Big Cores):


High-Efficiency (Small Cores)

MCU:

ULP (ARM):


Server (EPIC) (Itanium):

Many-core:

Early Research:

MIC Architectures:

Heterogeneous:


GPU:

Integrated:

Discrete:

Artificial Intelligence:

Training:

Inference:

Other Chips[edit]

Neuromorphic:

Artificial Intelligence

Quantum:

RAM:

Architectural Concepts[edit]

Other[edit]

Other topics[edit]

Technologies[edit]

Packaging Technologies[edit]

Documents[edit]

See Documents.

Retrieved from "https://en.wikichip.org/w/index.php?title=intel&oldid=102949"
Facts about "Intel"
RDF feed
company typepublic +
foundedJuly 18, 1968 +
founded locationMountain View, California +
founderGordon Moore +, Robert Noyce + and Andrew Grove +
full page nameintel +
headquartersSanta Clara, California +
instance ofsemiconductor company +
nameIntel +
websitehttp://www.intel.com +
wikidata idQ248 +