Semiconductor & Computer Engineering
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- | microarch 6 = Broadwell | proc = 45 nm43 KB (5,739 words) - 21:30, 22 April 2024
- | microarch 6 = Westmere | proc = 350 nm13 KB (1,417 words) - 12:37, 22 December 2018
- |process=5 nm |process 2=6 nm4 KB (693 words) - 01:48, 2 April 2023
- |process=5 nm |process 2=6 nm4 KB (666 words) - 01:48, 2 April 2023
- [[File:intel mask.jpg|right|thumb|Modern Intel 6" [[14 nm]]/[[10 nm]] test reticle.]]3 KB (533 words) - 17:17, 29 January 2024
- | process = 22 nm |l3 cache=6 MiB4 KB (404 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (401 words) - 14:24, 12 February 2019
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (400 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:22, 13 December 2017
- |process=22 nm |l3 cache=6 MiB3 KB (386 words) - 09:14, 26 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (401 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (397 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (398 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB4 KB (406 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (396 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (391 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (596 words) - 16:15, 13 December 2017
- |core family=6 |process=14 nm4 KB (596 words) - 16:15, 13 December 2017
- |core family=6 |process=14 nm4 KB (627 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (627 words) - 16:20, 13 December 2017
- |core family=6 |process=14 nm4 KB (640 words) - 02:21, 16 January 2019
- |core family=6 |process=14 nm4 KB (650 words) - 02:21, 16 January 2019
- | process = 14 nm |l3 cache=6 MiB4 KB (407 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (401 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (395 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (424 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (405 words) - 16:22, 13 December 2017
- |process=14 nm |l3 cache=6 MiB4 KB (460 words) - 15:03, 24 March 2019
- |core family=6 |process=14 nm4 KB (631 words) - 16:18, 13 December 2017
- |core family=6 |process=14 nm4 KB (649 words) - 16:20, 13 December 2017
- | proc = 45 nm | proc 2 = 32 nm17 KB (2,292 words) - 09:32, 16 July 2019
- | proc = 800 nm | proc 2 = 600 nm10 KB (1,057 words) - 19:30, 1 November 2021
- | microarch 6 = Excavator | proc = 32 nm6 KB (700 words) - 15:43, 1 December 2019
- ...lithography process|28 nm process]] (HN) / [[22 nm lithography process|22 nm process]] (FN) in 2012. TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the [[self-aligned via patter10 KB (1,090 words) - 19:14, 8 July 2021
- ...e 14 nm node was introduced in 2014/2015 and has been replaced by the [[10 nm process]]. | process 1 lith = 193 nm17 KB (2,243 words) - 19:32, 25 May 2023
- | process = 14 nm |l1d desc=6-way set associative4 KB (462 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative4 KB (472 words) - 16:15, 13 December 2017
- |process=14 nm |l1d desc=6-way set associative4 KB (475 words) - 17:42, 27 March 2018
- | process = 14 nm |l1d desc=6-way set associative5 KB (573 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative5 KB (572 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative6 KB (744 words) - 18:35, 14 January 2019
- |process=14 nm |l1d desc=6-way set associative5 KB (736 words) - 03:44, 19 August 2023
- | process = 14 nm |l1d desc=6-way set associative5 KB (558 words) - 16:15, 13 December 2017
- ...lithography process|40 nm process]] (HN) / [[32 nm lithography process|32 nm process]] (FN) in 2010. ...on, {{intel|Fab 32}} in Arizona and {{intel|Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-5 KB (602 words) - 05:51, 20 July 2018
- |process=45 nm |extension 6=SSSE338 KB (5,468 words) - 20:29, 23 May 2019
- | process = 32 nm | extension 6 = SSSE37 KB (872 words) - 19:42, 30 November 2017
- | process = 22 nm | extension 6 = SSSE39 KB (1,160 words) - 09:35, 25 September 2019
- | process = 14 nm | extension 6 = SSSE35 KB (568 words) - 19:40, 30 November 2017
- |process=14 nm |extension 6=SSSE37 KB (956 words) - 23:05, 23 March 2020
- | microarch 6 = Haswell | proc = 45 nm20 KB (2,661 words) - 00:45, 11 October 2017
- | microarch 6 = Westmere | proc = 350 nm25 KB (3,201 words) - 03:13, 22 September 2018
- |process=14 nm |tdp=6.5 W4 KB (529 words) - 17:41, 27 March 2018
- |process=14 nm |tdp=6 W5 KB (701 words) - 17:40, 27 March 2018
- |process=14 nm |tdp=6 W4 KB (540 words) - 17:40, 27 March 2018
- |process=14 nm ...d by Intel and introduced in early 2015. The N3000 is manufactured in [[14 nm process]] based on the {{intel|Airmont}} microarchitecture. This chip opera4 KB (544 words) - 17:43, 27 March 2018
- |process=14 nm |tdp=6 W4 KB (580 words) - 09:40, 8 July 2022
- |process=14 nm |tdp=6 W5 KB (724 words) - 06:10, 2 December 2018
- |process=14 nm ...d by Intel and introduced in early 2016. The N3010 is manufactured in [[14 nm process]] based on the {{intel|Airmont}} microarchitecture. This chip opera4 KB (539 words) - 17:39, 27 March 2018
- |process=14 nm ...based on the {{intel|Airmont}} microarchitecture. This chip operates at 1.6 GHz with turbo mode of up to 2.24 GHz. This SoC incorporates the {{intel|HD4 KB (535 words) - 17:39, 27 March 2018
- |process=14 nm |tdp=6 W5 KB (722 words) - 01:50, 24 November 2018
- |process=14 nm |tdp=6 W4 KB (533 words) - 17:41, 27 March 2018
- |process=14 nm |tdp=6 W4 KB (539 words) - 17:39, 27 March 2018
- |core family=6 |core model=64 KB (593 words) - 02:17, 1 April 2019
- |core family=6 |core model=64 KB (593 words) - 02:18, 1 April 2019
- |core family=6 |core model=64 KB (582 words) - 02:21, 1 April 2019
- |core family=6 |core model=64 KB (596 words) - 02:18, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (593 words) - 02:17, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (596 words) - 02:17, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 09:36, 14 May 2021
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:18, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:17, 1 April 2019
- |process=14 nm |cores 3=614 KB (1,891 words) - 14:37, 6 January 2022
- |process=22 nm |cores 3=627 KB (3,750 words) - 06:57, 18 November 2023
- ...hy process|20 nm process]] (HN) in 2014 and [[16 nm lithography process|16 nm process]] (FN) in late 2015. The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the7 KB (891 words) - 09:52, 25 November 2020
- | microarch 6 = Broadwell | proc = 45 nm4 KB (572 words) - 16:03, 1 June 2017
- | core family = 6 | process = 45 nm4 KB (522 words) - 20:46, 4 October 2018
- | core family = 6 | process = 45 nm4 KB (537 words) - 15:01, 13 December 2019
- | process = 22 nm ...ge''' ('''IVB''') was [[Intel]]'s [[microarchitecture]] based on the [[22 nm process]] for desktops and servers. Ivy Bridge was introduced in 2011 as a5 KB (689 words) - 13:44, 2 May 2020
- |process=32 nm ...formerly '''Gesher''', is [[Intel]]'s successor to {{\\|Westmere}}, a [[32 nm process]] [[microarchitecture]] for mainstream workstations, desktops, and84 KB (13,075 words) - 00:54, 29 December 2020
- | process = 32 nm '''Westmere''' ('''WSM''') was the [[microarchitecture]] for [[Intel]]'s [[32 nm process]] for desktops and servers. Westmere was introduced in 2010 as a [[10 KB (1,258 words) - 21:07, 9 March 2018
- | process = 45 nm '''Penryn''' was the [[microarchitecture]] for [[Intel]]'s [[45 nm process]] for desktops and servers as a successor to {{\\|Core}}. Penryn wa1 KB (133 words) - 21:08, 9 March 2018
- |process=14 nm |extension 6=SSSE379 KB (11,922 words) - 06:46, 11 November 2022
- |process=14 nm |extension 6=SSSE338 KB (5,431 words) - 10:41, 8 April 2024
- |process=10 nm |extension 6=SSSE37 KB (887 words) - 12:53, 5 August 2019
- |process=10 nm |extension 6=SSSE323 KB (3,613 words) - 12:31, 20 June 2021
- |process=10 nm |cores 3=63 KB (406 words) - 10:46, 19 July 2023
- | bus rate = 6.4 GT/s | process = 32 nm4 KB (419 words) - 16:24, 13 December 2017
- | bus rate = 6.4 GT/s | process = 32 nm4 KB (414 words) - 16:24, 13 December 2017
- ...lithography process|55 nm process]] (HN) / [[45 nm lithography process|45 nm process]] (FN) in 2007. ...nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ4 KB (407 words) - 05:55, 20 July 2018
- | last shipment = March 6, 2015 | platform = 6 Series Chipset5 KB (517 words) - 23:32, 22 September 2019
- | last shipment = March 6, 2015 | platform = 6 Series Chipset4 KB (456 words) - 16:24, 13 December 2017
- |process=22 nm |core count=64 KB (492 words) - 23:23, 12 March 2019
- |core family=6 |process=32 nm5 KB (710 words) - 16:24, 13 December 2017
- |core family=6 |process=32 nm5 KB (710 words) - 03:49, 26 June 2018
- | last shipment = February 6, 2015 | process = 22 nm5 KB (573 words) - 16:24, 13 December 2017
- |core family=6 |process=14 nm4 KB (649 words) - 16:22, 13 December 2017
- |core family=6 |process=14 nm4 KB (649 words) - 16:22, 13 December 2017
- |core family=6 |process=14 nm4 KB (654 words) - 17:22, 26 March 2018
- ...y process|110 nm process]] (HN) in 2003 and [[90 nm lithography process|90 nm process]] (FN) in 2004. ...8 || colspan="2" | || colspan="2" | 5 || colspan="2" | 7 || colspan="2" | 6 || colspan="2" | 75 KB (500 words) - 16:02, 13 May 2020
- ...process|150 nm process]] (HN) in 2000 and [[130 nm lithography process|130 nm process]] (FN) in 2001. The 180 nm process was first to use Cu metalization as a replacement for Al for interc4 KB (413 words) - 03:04, 17 August 2023
- ...m node is currently being introduced and is set to get replaced by the [[7 nm process]] in 2018/2019. ...in range of 50-60s nm and a [[minimum metal pitch]] in the range of 30-40s nm. Due to the small feature sizes, for the [[critical dimensions]], [[quad pa14 KB (1,903 words) - 06:52, 17 February 2023
- ...g-edge foundries by 2020/21 timeframe where it will be replaced by the [[5 nm node]]. The term "7 nm" is simply a commercial name for a generation of a certain size and its tec13 KB (1,941 words) - 02:40, 5 November 2022
- ...nm process]] node. Commercial [[integrated circuit]] manufacturing using 5 nm process is set to begin sometime around 2020. The term "5 nm" is simply a commercial name for a generation of a certain size and its tec11 KB (1,662 words) - 02:58, 2 October 2022
- ...nm process began in late 1995. 350 nm was phased out and replaced by [[250 nm]] in 1999. ..." | || colspan="2" | CS-34 || colspan="2" | CS-34EX || colspan="2" | CMOS-6 || colspan="2" | CS-60 || colspan="2" | || colspan="2" | || colspan="2" |5 KB (586 words) - 22:44, 4 April 2022
- ...hy process|130 nm]] and [[90 nm lithography process|90 nm]] processes. 110 nm process was used in the early 2000s. | colspan="6" | Bulk1 KB (143 words) - 05:57, 20 July 2018
- ...This technology superseded by commercial [[130 nm]], [[110 nm]], and [[90 nm]] processes. ...d for the production of 128 MiB, 256 MiB and [[Rambus]] [[DRAM]]s on a 150 nm process. Line 10 opened in the third quarter of [[2000]] producing 16,000 [2 KB (238 words) - 02:56, 27 September 2020
- ...nies during the early to mid 1970s. This process was later superseded by [[6 µm]], [[5 µm]], and [[3 µm]] processes. | ? nm710 bytes (91 words) - 06:15, 18 January 2022
- | 2000 || HiPerMOS 6 || [[0.18 µm]] || 1.5 V || | 2004 || HiPerMOS 8 || [[90 nm]] || || SOI943 bytes (88 words) - 01:19, 27 April 2016
- ...began in late 1990s. 220 nm and was phased out and later replaced by [[180 nm]] processes. | ? nm || ? nm975 bytes (117 words) - 06:10, 20 July 2018
- | core family = 6 | process = 250 nm3 KB (316 words) - 16:25, 13 December 2017
- | core family = 6 | process = 250 nm3 KB (319 words) - 16:25, 13 December 2017
- | core family = 6 | process = 250 nm3 KB (313 words) - 16:25, 13 December 2017
- | core family = 6 | core model = 63 KB (366 words) - 16:25, 13 December 2017
- | core family = 6 | core model = 63 KB (360 words) - 16:25, 13 December 2017
- | core family = 6 | core model = 63 KB (320 words) - 16:25, 13 December 2017
- | core family = 6 | core model = 63 KB (309 words) - 16:25, 13 December 2017
- | clock multiplier = 6 | core family = 63 KB (345 words) - 16:25, 13 December 2017
- |core family=6 |process=14 nm3 KB (485 words) - 00:29, 7 April 2018
- |core family=6 |process=14 nm4 KB (620 words) - 00:27, 7 April 2018
- |core family=6 |process=14 nm3 KB (490 words) - 00:29, 7 April 2018
- |core family=6 |process=14 nm3 KB (489 words) - 16:26, 13 December 2017
- |core family=6 |process=14 nm4 KB (609 words) - 00:29, 7 April 2018
- |core family=6 |process=14 nm3 KB (484 words) - 16:26, 13 December 2017
- |core family=6 |process=14 nm3 KB (490 words) - 00:29, 7 April 2018
- |core family=6 |process=14 nm4 KB (608 words) - 16:26, 13 December 2017
- |core family=6 |process=14 nm3 KB (506 words) - 00:29, 7 April 2018
- |core family=6 |process=14 nm4 KB (620 words) - 00:24, 7 April 2018
- |core family=6 |process=14 nm3 KB (490 words) - 00:29, 7 April 2018
- |core family=6 |process=14 nm4 KB (624 words) - 00:27, 7 April 2018
- |core family=6 |process=14 nm4 KB (648 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (646 words) - 05:24, 14 July 2018
- |core family=6 |process=14 nm4 KB (654 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (654 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (663 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (640 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (607 words) - 16:25, 13 December 2017
- |core family=6 |process=14 nm4 KB (610 words) - 16:25, 13 December 2017
- |core family=6 |process=14 nm4 KB (616 words) - 16:25, 13 December 2017
- |core family=6 |process=14 nm4 KB (623 words) - 06:18, 5 November 2020
- |core family=6 |process=14 nm4 KB (610 words) - 16:25, 13 December 2017
- |core family=6 |process=14 nm4 KB (606 words) - 16:25, 13 December 2017
- |core family=6 |process=14 nm4 KB (581 words) - 17:57, 28 August 2018
- |core family=6 |process=14 nm4 KB (597 words) - 16:25, 13 December 2017
- |core family=6 |core model=64 KB (613 words) - 02:20, 1 April 2019
- |core family=6 |core model=64 KB (596 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (596 words) - 02:16, 1 April 2019
- | process = 14 nm | ctdp up = 6 W6 KB (626 words) - 19:52, 6 October 2020
- | process = 14 nm | ctdp up = 6 W6 KB (623 words) - 16:24, 13 December 2017
- | process = 14 nm | ctdp up = 6 W6 KB (623 words) - 16:24, 13 December 2017
- | process = 14 nm | ctdp up = 6 W6 KB (627 words) - 16:24, 13 December 2017
- |core family=6 |process=14 nm4 KB (613 words) - 17:58, 28 August 2018
- |core family=6 |process=14 nm4 KB (613 words) - 17:58, 28 August 2018
- |core family=6 |process=14 nm4 KB (613 words) - 17:58, 28 August 2018
- |core family=6 |process=14 nm4 KB (613 words) - 17:58, 28 August 2018
- | proc 2 = 800 nm | proc 3 = 600 nm8 KB (953 words) - 08:27, 29 October 2022
- | s-spec 6 = SX493 | process 2 = 800 nm3 KB (256 words) - 16:13, 13 December 2017
- | part number 6 = SB80486DX-33 | s-spec 6 = SX7293 KB (321 words) - 02:59, 18 December 2017
- | s-spec 6 = SX705 | process 2 = 800 nm3 KB (265 words) - 16:13, 13 December 2017
- | s-spec 6 = SX749 | process 2 = 800 nm3 KB (345 words) - 16:13, 13 December 2017
- | part number 6 = TQ80486DX266 | s-spec 6 = SX7394 KB (372 words) - 06:28, 15 February 2024
- | part number 6 = FC80486DX4WB75 | s-spec 6 = SK0523 KB (354 words) - 16:13, 13 December 2017
- | part number 6 = MQ80486DX4100 | s-spec 6 = SX9004 KB (414 words) - 16:13, 13 December 2017
- | s-spec 6 = SX671 | process 2 = 800 nm3 KB (240 words) - 16:14, 13 December 2017
- | s-spec 6 = SX587 | process 2 = 800 nm3 KB (251 words) - 16:14, 13 December 2017
- | s-spec 6 = SX676 | cpuid 6 = 42A4 KB (332 words) - 16:14, 13 December 2017
- | part number 6 = FA80486SX33 | s-spec 6 = SX8474 KB (345 words) - 16:14, 13 December 2017
- |core family=6 |process=14 nm4 KB (616 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (609 words) - 16:18, 13 December 2017
- |core family=6 |process=14 nm4 KB (618 words) - 16:18, 13 December 2017
- |core family=6 |process=14 nm4 KB (612 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (611 words) - 16:18, 13 December 2017
- |core family=6 |process=14 nm4 KB (615 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (615 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (613 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (613 words) - 02:11, 16 January 2019
- |core family=6 |process=14 nm4 KB (613 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (609 words) - 16:16, 13 December 2017
- |core family=6 |process=14 nm4 KB (606 words) - 16:16, 13 December 2017
- | microarch 6 = Skylake | proc = 32 nm25 KB (3,397 words) - 03:12, 3 October 2022
- | microarch 6 = Broadwell | proc = 45 nm34 KB (4,663 words) - 20:38, 20 February 2023
- | first launched = November 6, 1995 | proc = 350 nm7 KB (1,043 words) - 16:50, 14 June 2020
- | caption = AMD-X5-133ADZ, 1996 Week 6 | process = 350 nm3 KB (372 words) - 16:35, 9 July 2018
- | proc = 350 nm * 6 x external interrupts9 KB (1,276 words) - 16:07, 28 June 2016
- | bus speed = 6.25 MHz | bus rate = 6.25 MT/s3 KB (334 words) - 16:57, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (334 words) - 16:58, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (334 words) - 16:58, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (333 words) - 16:59, 30 June 2017
- | bus speed = 6.25 MHz | bus rate = 6.25 MT/s3 KB (344 words) - 16:57, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (344 words) - 16:58, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (344 words) - 16:58, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (343 words) - 16:59, 30 June 2017
- | bus speed = 6.25 MHz | bus rate = 6.25 MT/s3 KB (334 words) - 16:57, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (334 words) - 16:57, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (334 words) - 16:58, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (333 words) - 16:59, 30 June 2017
- | bus speed = 6.25 MHz | bus rate = 6.25 MT/s3 KB (345 words) - 16:57, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (345 words) - 16:57, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (345 words) - 16:58, 30 June 2017
- | process = 350 nm | irq lines = 63 KB (344 words) - 16:59, 30 June 2017
- | core family = 6 | process = 32 nm4 KB (473 words) - 16:28, 13 December 2017
- | core family = 6 | process = 32 nm4 KB (475 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (520 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (528 words) - 16:28, 13 December 2017
- | core family = 6 | process = 32 nm4 KB (520 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (522 words) - 16:28, 13 December 2017
- | core family = 6 | process = 32 nm4 KB (518 words) - 05:10, 18 February 2020
- | bus rate = 6.40 GT/s | core family = 64 KB (518 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (539 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (539 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (539 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (542 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (539 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (539 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (537 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (541 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (537 words) - 16:28, 13 December 2017
- | bus rate = 6.40 GT/s | core family = 64 KB (537 words) - 16:28, 13 December 2017
- | proc = 130 nm |userparam=611 KB (1,421 words) - 14:45, 9 December 2018
- | proc = 130 nm * [[:File:RAID 6 Q Encode.pdf|RAID 6 Q Encoder Implementation]]5 KB (596 words) - 21:23, 19 November 2017
- | process = 130 nm | power = 6 W3 KB (334 words) - 16:31, 13 December 2017
- | first announced = January 6, 1997 | first launched = January 6, 19973 KB (298 words) - 16:07, 13 December 2017
- | first announced = January 6, 1997 | first launched = January 6, 19973 KB (296 words) - 16:08, 13 December 2017
- | first announced = January 6, 1997 | first launched = January 6, 19973 KB (296 words) - 16:08, 13 December 2017
- | first announced = January 6, 1997 | first launched = January 6, 19973 KB (317 words) - 16:08, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (333 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (333 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (343 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (298 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (298 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (314 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (322 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (298 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (314 words) - 16:09, 13 December 2017
- | core model = 6 | process = 350 nm3 KB (316 words) - 01:23, 9 November 2020
- | proc = 250 nm | ex 6 = F13 KB (1,969 words) - 18:07, 2 October 2019
- |process=14 nm |extension 6=SSSE330 KB (4,192 words) - 13:48, 10 December 2023
- |process=7 nm |core count=65 KB (748 words) - 00:43, 26 March 2023
- | proc = 180 nm | proc 2 = 250 nm9 KB (1,264 words) - 02:29, 19 January 2017
- | proc = 180 nm | proc 2 = 130 nm19 KB (2,874 words) - 17:30, 3 December 2016
- | core family = 6 | process = 180 nm4 KB (423 words) - 16:07, 13 December 2017
- | clock multiplier = 6 | core family = 64 KB (438 words) - 16:07, 13 December 2017
- | clock multiplier = 6.5 | core family = 64 KB (423 words) - 16:07, 13 December 2017
- | core family = 6 | process = 180 nm4 KB (423 words) - 16:07, 13 December 2017
