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- ...ating over a large number of hash table entries to find the item needed is CPU intensive and mIRC might start to feel unresponsive.30 KB (5,149 words) - 01:46, 30 November 2018
- * CPU Instructions18 KB (2,445 words) - 08:24, 9 November 2019
- | [[Config register - MIPS|Config]] || 16 || rowspan="4" | CPU setup3 KB (384 words) - 10:11, 19 February 2018
- === Dispatching example - CPU info === ;get some cool information about the CPU here27 KB (3,608 words) - 11:41, 25 October 2018
- ...ly available [[microprocessor]]. The 4004 was a [[4-bit architecture|4-bit CPU]], designed for use in the [[Busicom]] 141-PF printing calculator<ref>[http5 KB (748 words) - 21:37, 21 November 2021
- | image = Rockwell PPS4 11660 CPU.jpg ...It's full compatible with all the original {{rockwell|pps-4/10660|PPS-4}} CPU and all the other parts.2 KB (240 words) - 16:32, 13 December 2017
- | arch = 4-bit ...ROM]] chip, a [[RAM]] chip, [[shift register]], and a [[4-bit architecture|4-bit]] [[microprocessor]]. The chipset was first produced first quarter of 1975.2 KB (266 words) - 00:54, 19 May 2016
- ...10, its CPU was also a custom-designed [[transistor-transistor logic|TTL]] CPU. ...[[Voyager Flight Data System|Voyager's data computer]], which was a custom 4-bit CMOS microprocessor.11 KB (1,334 words) - 18:26, 10 May 2019
- | caption = Intel D3002, CPU of the 3000 series | {{\|3002}} || CPU3 KB (308 words) - 05:03, 18 February 2020
- ...iterations per chunk (bearing in mind that it may run on PCs of different CPU powers). Clearly you want to keep the iterations small enough that mIRC con13 KB (2,047 words) - 07:44, 23 February 2023
- | arch = 4-bit word, 8-bit instruction, BCD-oriented ...re chipset was made of four individual chips, including the [[/4004|4004]] CPU which became the first commercial microprocessor. MCS-4 was completed by Ma4 KB (433 words) - 22:40, 27 June 2019
- {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}4 KB (460 words) - 15:03, 24 March 2019
- ...em to function as a single computer on a chip. This usually includes the [[CPU]], [[program memory|program]] and [[data memory]], [[programmable I/O|progr2 KB (344 words) - 15:51, 21 March 2024
- | arch = 4-bit words, 8-bit instruction The '''PPS-4''' (Parallel Processing System - 4-bit word) was a [[microprocessor family|family]] of {{arch|4}} [[microprocessor3 KB (359 words) - 17:26, 19 May 2016
- ...1980 Catalog, "μCOM-4: 4-Bit Single Chip Microcomputer Family, μCOM-43SL CPU μPD557L", 104, 125-126 pp. *NEC Microcomputers, Inc., 1981 Catalog, "μCOM-4: 4-Bit Single Chip Microcomputer Family, μPD557L μCOM-43SL", 155, 177-178 pp.2 KB (244 words) - 06:13, 1 August 2018
- | arch = 4-bit words, 8-bit instruction ...system (hence the "/1"). It's full compatible with all the original PPS-4 CPU and all the other parts.2 KB (219 words) - 01:00, 19 May 2016
- ...power came from its simplicity, being an [[in-order]] dual-issue pipelined CPU. All Bonnell-based processors were manufactured on Intel's [[45 nm process] Silverthorne chips have an incredibly simple design featuring only the CPU itself on-die. The [[southbridge]] and [[northbridge]] are integrated on a17 KB (2,292 words) - 09:32, 16 July 2019
- | caption = The F3850 [[CPU]] component | {{\|3850}} || [[CPU]]2 KB (172 words) - 17:18, 12 December 2016
- The CPU 6309 by HITACHI has secret features which is not written in with instructions of the Hitachi 6301 CPU. Read the manual of the 630131 KB (2,938 words) - 14:54, 17 March 2016
- | caption = CPU, {{\|8008-1}} higher speed variant ...[Intel]]. Introduced on April, [[1972]], the MCS-8 featured the {{\|8008}} CPU.3 KB (382 words) - 17:58, 19 May 2016
- | caption = {{\|8080}}, the CPU of the MCS-80 system ...y [[Intel]]. Introduced on April, 1974, the MCS-80 featured the {{\|8080}} CPU, the forefather of all modern [[x86]]-based microprocessors.4 KB (406 words) - 16:10, 26 January 2019
- | process 1 name = P1268 (CPU) / P1269 (SoC)10 KB (1,090 words) - 19:14, 8 July 2021
- | process 1 name = P1272 (CPU) / P1273 (SoC) ...or performance and high frequency (e.g., high-switching circuitry in the [[CPU]]) whereas short cells are optimized for density (e.g., GPU shader arrays).17 KB (2,243 words) - 19:32, 25 May 2023
- | colspan="2" | P1266 (CPU) / P1266.8 (SoC) / P1269 (SoC) || colspan="2" | CS-300 || colspan="2" | ||5 KB (602 words) - 05:51, 20 July 2018
- |atype=CPU ...tel turned to higher integration, moving [[integrated graphics|Graphics]], CPU core, Video Acceleration, [[Display Controller]], and [[Memory Controller]]38 KB (5,468 words) - 20:29, 23 May 2019
- | atype = CPU <tr><th colspan="8">CPU</th><th colspan="3">IGP</th></tr>7 KB (872 words) - 19:42, 30 November 2017
- | atype = CPU9 KB (1,160 words) - 09:35, 25 September 2019
- | atype = CPU5 KB (568 words) - 19:40, 30 November 2017
- |atype=CPU7 KB (956 words) - 23:05, 23 March 2020
- <tr><th colspan="8">CPU</th><th colspan="3">IGP</th></tr> ...ated the [[integrated graphics]] on this same die as the newly architected CPU, allowing for higher performance and lower power than previous generation.20 KB (2,661 words) - 00:45, 11 October 2017
- <tr><th colspan="8">CPU</th><th colspan="3">IGP</th></tr>25 KB (3,201 words) - 03:13, 22 September 2018
- All models are a single-chip solution, meaning both the [[CPU]] [[die]] and the [[chipset]] die are packaged together on the same substra All models are a single-chip solution, meaning both the [[CPU]] [[die]] and the [[chipset]] die are packaged together on the same substra13 KB (1,784 words) - 08:04, 6 April 2019
- |atype=CPU ...l]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]] [[max cpu count::1]]14 KB (1,891 words) - 14:37, 6 January 2022
- |atype=CPU ==== CPU changes ====27 KB (3,750 words) - 06:57, 18 November 2023
- | atype = CPU * 4 CPU cores5 KB (689 words) - 13:44, 2 May 2020
- |atype=CPU ...diagram from Intel. The master design incorporates the [[quad-core|four]] CPU [[physical cores|cores]], the [[GPU]] with 12 execution units, the 8 MiB sh84 KB (13,075 words) - 00:54, 29 December 2020
- | atype = CPU ...l]] [[instance of::microprocessor]] [[microarchitecture::Westmere ]] [[max cpu count::1]]10 KB (1,258 words) - 21:07, 9 March 2018
- | atype = CPU4 KB (459 words) - 21:44, 26 December 2023
- | atype = CPU3 KB (325 words) - 21:34, 22 February 2020
- |atype=CPU **** Limits motherboard trace design to 7 inches max from the CPU to chipset (down from 8)79 KB (11,922 words) - 06:46, 11 November 2022
- |atype=CPU ...her via Intel's standard [[DMI 3.0]] bus interface which utilizes 4 of the CPU's 20 [[PCIe]] 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only {38 KB (5,431 words) - 10:41, 8 April 2024
- |atype=CPU * 2 CPU cores + 40 GPU EUs7 KB (887 words) - 12:53, 5 August 2019
- |atype=CPU ...in-and-light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|G23 KB (3,613 words) - 12:31, 20 June 2021
- |atype=CPU3 KB (406 words) - 10:46, 19 July 2023
- {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}4 KB (564 words) - 14:29, 24 March 2019
- | process 1 name = P1274 (CPU) / P1275 (SoC) ** CPU14 KB (1,903 words) - 06:52, 17 February 2023
- == CPU Families == '''CPU:'''3 KB (261 words) - 16:48, 20 March 2024
- File:Intel i486 DX33 CPU SX 419.jpg|A80486DX-33, S-Spec SX4193 KB (321 words) - 02:59, 18 December 2017
- | image = CPU Intel 80486DX-50.JPG File:Intel i486 DX 50 CPU.jpg|A80486DX-50, S-Spec SX7103 KB (265 words) - 16:13, 13 December 2017
- | image = Ic-photo-Intel--SB80486DX2-50--(486-CPU).JPG3 KB (345 words) - 16:13, 13 December 2017
- File:Intel i486 DX2 66 CPU SX750.jpg|A80486DX2-66, S-Spec SX750 File:Intel i486 DX2 66 CPU SX955.jpg|A80486DX2-66, S-Spec SX9554 KB (372 words) - 06:28, 15 February 2024
- | image = Ic-photo-Intel--FC80486DX4-75--(486-CPU).png3 KB (354 words) - 16:13, 13 December 2017
- Ic-photo-Intel--A80486DX4100-(486DX4-CPU).png|A80486DX4100, S-Spec SK0964 KB (414 words) - 16:13, 13 December 2017
- File:Ic-photo-Intel--SB80486SX-33--(486-CPU).JPG|SB80486SX-334 KB (345 words) - 16:14, 13 December 2017
- | image = Ic-photo-AMD--Am486DX-40-(A80486DX-40)-(486-CPU).jpg File:AMD Am486 DX 40 CPU E.jpg3 KB (270 words) - 15:18, 13 December 2017
- This is the fastest regular 486-type CPU that has also been available as a native 5 Volt part.1 KB (209 words) - 21:53, 7 February 2024
- File:AMD Am486 DX2 66 CPU E6.jpg| File:AMD Am486 DX2 66 CPU D.jpg3 KB (286 words) - 15:18, 13 December 2017
- | image = Ic-photo-AMD--A80486DX4-100NV8T-(486-CPU).png File:AMD Am486 DX4 100 NV8T CPU.jpg|3 KB (348 words) - 15:19, 13 December 2017
- * [[:File:CPU Thermal Management (Am486, Am5x86, K5) (August 1995).pdf|CPU Thermal Management]]; Publication #18448 Revision D/0; August 1995.7 KB (1,043 words) - 16:50, 14 June 2020
- | image = Ic-photo-AMD--Am5x86-P75-(Am486DX5-133W16BGC)-(486-CPU).jpg File:Ic-photo-AMD--Am5x86-P75-(Am486DX5-133W16BGC)-(486-CPU).jpg|1997, Week 463 KB (358 words) - 15:19, 13 December 2017
- File:Ic-photo-AMD--AM486DX5-133V16BHC--(Am5x86-P75)--(486-CPU).JPG3 KB (342 words) - 15:19, 13 December 2017
- File:Ic-photo-AMD--AMD-X5-133ADW-(Am5x86-P75)-(586-CPU).png|From 1996 Week 103 KB (336 words) - 15:19, 13 December 2017
- | image = Ic-photo-AMD--N80L286-16 S-(286-CPU).png3 KB (281 words) - 15:18, 13 December 2017
- | image = Ic-photo-AMD--R80286-10 S-(286-CPU).png3 KB (296 words) - 15:18, 13 December 2017
- * CPU shutdown mode; System shutdown mode3 KB (339 words) - 15:18, 13 December 2017
- * CPU shutdown mode; System shutdown mode3 KB (339 words) - 15:18, 13 December 2017
- | image = Ic-photo-AMD--N80C186-(186-CPU).png3 KB (280 words) - 04:32, 22 October 2019
- | image = Ic-photo-AMD--N80C186-16-(186-CPU).png3 KB (286 words) - 15:17, 13 December 2017
- | image = Ic-photo-AMD--R80186-6 B4-(186-CPU).png3 KB (250 words) - 15:17, 13 December 2017
- |?max cpu count4 KB (482 words) - 05:08, 18 February 2020
- ...e 1025 model is the same as the 1024 model with an additional IBM Power PC CPU core incorporated as well for general-purpose tasks. These two models appea2 KB (254 words) - 03:53, 25 June 2016
- *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU3 KB (367 words) - 15:16, 13 December 2017
- *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU3 KB (280 words) - 15:16, 13 December 2017
- *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU3 KB (280 words) - 15:16, 13 December 2017
- *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU3 KB (280 words) - 15:16, 13 December 2017
- *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU3 KB (344 words) - 15:16, 13 December 2017
- *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU3 KB (256 words) - 15:16, 13 December 2017
- *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU3 KB (256 words) - 15:16, 13 December 2017
- | arch = 32-bit vector/matrix math processor + RISC cpu ...as a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity]]. The chips were developed using Intrinsity'4 KB (464 words) - 17:41, 3 July 2016
- ...erating at 1.5 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.3 KB (317 words) - 16:30, 13 December 2017
- ...operating at 2 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.3 KB (318 words) - 16:30, 13 December 2017
- ...operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-powe3 KB (334 words) - 16:31, 13 December 2017
- ...operating at 3 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.3 KB (306 words) - 16:31, 13 December 2017
- File:Ic-photo-AMD--AMD-SSA 5-75ABR-(AMD5k86-P75-CPU).png3 KB (313 words) - 16:08, 13 December 2017
- File:Ic-photo-AMD--AMD-K5-PR100ABQ-(K5-CPU).jpg3 KB (308 words) - 16:07, 13 December 2017
- File:Ic-photo-AMD--AMD-K6-166ALR-(K6-CPU).jpg|166ALR, Week 35, 1997 File:Ic-photo-AMD--AMD-K6-166ALR-(K6-CPU).png|166ALR, Week 35, 19973 KB (343 words) - 16:09, 13 December 2017
- |atype=CPU The Coffee Lake system on a chip consists of a five major components: CPU [[physical core|cores]], [[last level cache|LLC]], Ring interconnect, {{int30 KB (4,192 words) - 13:48, 10 December 2023
- | image = Ic-photo-AMD--AMD-K6-2 333AFR-(K6-2-CPU).png3 KB (387 words) - 16:08, 13 December 2017
- | image = Ic-photo-AMD--AMD-K6-2 500AFX-(K6-2-CPU).png3 KB (353 words) - 16:08, 13 December 2017
- | image = Ic-photo-AMD--AMD-K6-2 380ACK--(K6-2 CPU).jpg3 KB (347 words) - 16:08, 13 December 2017
- ...ame pinout and bus interface, a single system can be used by replacing the CPU between tests. Section 3 lists the hardware components for the systems and11 KB (1,244 words) - 06:26, 8 July 2020
- | image = CPU AMD Duron 800.jpg4 KB (438 words) - 16:07, 13 December 2017
- | image = Ic-photo-AMD--D900AUT1B-(K7-Duron-CPU).png4 KB (437 words) - 16:07, 13 December 2017
- ...] core (+L1$), an L1.5 cache, L2 cache, a [[floating-point unit]] (FPU), a CPU Cache-Crossbar (CCX) arbiter, and three [[network on chip]] (NoC) routers.6 KB (731 words) - 15:41, 5 July 2018
- | atype = CPU4 KB (578 words) - 18:57, 22 May 2019
- |atype=CPU ...s by amd]] [[instance of::microprocessor]] [[microarchitecture::K7]] [[max cpu count::1]]6 KB (923 words) - 16:48, 3 March 2022
- |atype=CPU2 KB (261 words) - 01:06, 19 June 2023
- | atype = CPU2 KB (287 words) - 17:28, 1 December 2018
- |atype=CPU2 KB (261 words) - 16:24, 4 January 2022
- |atype=CPU2 KB (223 words) - 19:54, 14 July 2021