From WikiChip
Difference between revisions of "arm/microarchitectures"
< arm

(add tables)
(add links)
 
Line 1: Line 1:
 
<!--#REDIRECT [[arm/versions]]-->
 
<!--#REDIRECT [[arm/versions]]-->
−
 
+
=== [[ARM Holdings]] ===
 
:;[[ARM]] • [[arm/versions|Versions]] • [[Cortex]] • [[Neoverse]]
 
:;[[ARM]] • [[arm/versions|Versions]] • [[Cortex]] • [[Neoverse]]
  
Line 32: Line 32:
 
}}
 
}}
 
</table>
 
</table>
 +
 +
==== Comparison ====
 +
:;"LITTLE" core
 +
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
 +
|-
 +
! [[Microarchitecture|µArch]]
 +
! {{armh|Cortex-A53|l=arch}}
 +
! {{armh|Cortex-A55|l=arch}}
 +
! {{armh|Cortex-A510|l=arch}}
 +
! {{armh|Cortex-A520|l=arch}}
 +
! {{armh|Cortex-A530|l=arch}}
 +
|-
 +
! Codename
 +
| ''{{armh|Apollo|l=arch}}''
 +
| ''{{armh|Ananke|l=arch}}''
 +
| ''{{armh|Klein|l=arch}}''
 +
| ''{{armh|Hayes|l=arch}}''
 +
| ''Nevis''
 +
|-
 +
! Peak clock speed
 +
| 2.3&nbsp;GHz
 +
| 2.1&nbsp;GHz
 +
| 2.0&nbsp;GHz
 +
| 2.0&nbsp;GHz
 +
| -
 +
|-
 +
! Architecture
 +
| [[ARMv8]].0-A
 +
| [[ARMv8]].2-A
 +
| [[ARMv9]].0-A
 +
| [[ARMv9]].2-A
 +
| [[ARMv9]].4-A
 +
|-
 +
! '''AArch'''
 +
| colspan="3" | 32-bit and 64-bit
 +
| colspan="2" | 64-bit
 +
|-
 +
! '''L1 (I + D)''' (KiB)
 +
| 8/64 + 8/64 KiB
 +
| 16/64 + 16/64 KiB
 +
| colspan="2" | 32/64 + 32/64 KiB
 +
| -
 +
|-
 +
! L2 Cache (KiB)
 +
| colspan="2" | 0–256 KiB
 +
| colspan="2" | 0–512 KiB
 +
| -
 +
|-
 +
! L3 Cache (MiB)
 +
| -
 +
| 0–4 MiB
 +
| 0–16 MiB
 +
| 0–32 MiB
 +
| -
 +
|-
 +
! Decode width
 +
| colspan="2" | 2-way
 +
| 3-way
 +
| 3-way (2 ALU)
 +
| -
 +
|-
 +
! Dispatch
 +
| colspan="2" | 8 Mops/cycle
 +
| -
 +
| -
 +
| -
 +
|-
 +
|}
 +
 +
:;"big" core
 +
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
 +
|-
 +
! [[Microarchitecture|µArch]]
 +
! {{armh|Cortex-A77|l=arch}}
 +
! {{armh|Cortex-A78|l=arch}}
 +
! {{armh|Cortex-A710|l=arch}}
 +
! {{armh|Cortex-A715|l=arch}}
 +
! {{armh|Cortex-A720|l=arch}}
 +
! {{armh|Cortex-A725|l=arch}}
 +
! {{armh|Cortex-A730|l=arch}}
 +
|-
 +
! Codename
 +
| ''{{armh|Deimos|l=arch}}''
 +
| ''{{armh|Hercules|l=arch}}''
 +
| ''{{armh|Matterhorn|l=arch}}''
 +
| ''{{armh|Makalu|l=arch}}''
 +
| ''{{armh|Hunter|l=arch}}''
 +
| ''{{armh|Chaberton|l=arch}}''
 +
| ''Gelas''
 +
|-
 +
! Peak clock speed
 +
| 2.6&nbsp;GHz
 +
| colspan="4" | ~3.0&nbsp;GHz
 +
| -
 +
| -
 +
|-
 +
! Architecture
 +
| colspan="2" | [[ARMv8]].2-A
 +
| colspan="2" | [[ARMv9]].0-A
 +
| colspan="2" | [[ARMv9]].2-A
 +
| [[ARMv9]].4-A
 +
|-
 +
! AArch
 +
| -
 +
| colspan="2" | 32-bit and 64-bit
 +
| colspan="2" | 64-bit
 +
| colspan="2" | 64-bit
 +
|-
 +
! Max In-flight
 +
| 2x 160
 +
| 2x 160
 +
| ?
 +
| 2x 192+ <ref>{{cite book |title=Arm introduces Cortex-A715 |url=https://fuse.wikichip.org/news/6853/arm-introduces-the-cortex-a715/ |website=WikiChip Fuse |date=2022-06-28}}</ref>
 +
| ?
 +
| -
 +
| -
 +
|-
 +
! L0 (Mops entries)
 +
| -
 +
| colspan="2" | 1536
 +
| colspan="2" | 0
 +
| -
 +
| -
 +
|-
 +
! '''L1 (I + D)''' (KiB)
 +
| 64 + 64 KiB
 +
| colspan="4" | 32/64 + 32/64 KiB
 +
| 64 + 64 KiB
 +
| -
 +
|-
 +
! L2 Cache (KiB)
 +
| 256–512 KiB
 +
| colspan="4" | 128–512 KiB
 +
| 0.25–1 MiB <ref>{{cite book |title=Arm launches next gen big core Cortex-A725 |website=WikiChip Fuse |url=https://fuse.wikichip.org/news/7829/arm-launches-next-gen-big-core-cortex-a725/ |date=2024-05-29}}</ref><!-- From 32K/512K/8M L1/2/3 on the Cortex-A720 to 64K/1M/16M L1/2/3 on the new Cortex-A725 ? -->
 +
| -
 +
|-
 +
! L3 Cache (MiB)
 +
| 0–4 MiB
 +
| 0–8 MiB
 +
| colspan="2" | 0–16 MiB
 +
| colspan="2" | 0–32 MiB <ref>{{cite book |title=Arm introduces a new big core Cortex-A720 |website=WikiChip Fuse |url=https://fuse.wikichip.org/news/7529/arm-introduces-a-new-big-core-the-cortex-a720/ |date=2023-05-28}}</ref>
 +
| -
 +
|-
 +
! Decode width
 +
| colspan="3" | 4-way
 +
| colspan="3" | 5-way
 +
| -
 +
|-
 +
! Dispatch
 +
| colspan="2" | 6 Mops/cycle
 +
| colspan="2" | 5 Mops/cycle
 +
| ?
 +
| -
 +
| -
 +
|-
 +
|}
 +
 +
=== Cortex-X ===
 +
:;"Prime" core
 +
{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
 +
|-
 +
! [[Microarchitecture|µArch]]
 +
! {{armh|Cortex-X1|l=arch}}(C)
 +
! {{armh|Cortex-X2|l=arch}}
 +
! {{armh|Cortex-X3|l=arch}}
 +
! {{armh|Cortex-X4|l=arch}}
 +
! <s>{{armh|Cortex-X5|l=arch}}</s>
 +
! {{armh|Cortex-X925|l=arch}}
 +
! {{armh|Cortex-X930|l=arch}}
 +
|-
 +
! Codename
 +
| ''{{armh|Hera|l=arch}}(-C)''
 +
| ''{{armh|Matterhorn-ELP|l=arch}}''
 +
| ''{{armh|Makalu-ELP|l=arch}}''
 +
| ''{{armh|Hunter-ELP|l=arch}}''
 +
| <s>''{{armh|Chaberton-ELP|l=arch}}''</s>
 +
| ''{{armh|Blackhawk|l=arch}}''
 +
| ''Travis'' /''Alto''
 +
|-
 +
! Peak clock speed
 +
| 3.0&nbsp;GHz
 +
| 3.0&nbsp;GHz
 +
| 3.3&nbsp;GHz
 +
| 3.4&nbsp;GHz
 +
| - -
 +
| 3.8&nbsp;GHz
 +
| 4.2&nbsp;GHz
 +
|-
 +
! Architecture
 +
| [[ARMv8]].2-A
 +
| colspan="2" | [[ARMv9]].0-A
 +
| colspan="3" | [[ARMv9]].2-A
 +
| [[ARMv9]].4-A
 +
|-
 +
! AArch
 +
| 32/64-bit
 +
| colspan="2" | 64-bit
 +
| colspan="2" | 64-bit
 +
| colspan="2" | 64-bit
 +
|-
 +
! Max in-flight
 +
| 2x 224 <ref>{{cite book |last=Schor |first=David |date=2020-05-26 |title=Arm Cortex-X1: The First From The Cortex-X Custom Program |url=https://fuse.wikichip.org/news/3543/arm-cortex-x1-the-first-from-the-cortex-x-custom-program/ |website=WikiChip Fuse}}</ref>
 +
| 2x 288
 +
| 2x 320
 +
| 2x 384
 +
| - -
 +
| 2x 768 <ref>https://www.androidauthority.com/arm-cortex-x925-g925-explained-3445480/</ref>
 +
| -
 +
|-
 +
! L0 (Mops entries)
 +
| colspan="2" | 3072 <ref>{{cite book |title=Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence |url=https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging |website=www.anandtech.com}}</ref>
 +
| 1536
 +
| 0 <ref>{{cite book |title=Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive |url=https://www.androidauthority.com/arm-cortex-x4-explained-3328008/ |website=Android Authority}}</ref>
 +
| - -
 +
| -
 +
| -
 +
|-
 +
! '''L1 (I + D)''' (KiB)
 +
| colspan="2" | 64 + 64 KiB
 +
| colspan="2" | 64 + 64 KiB
 +
| - -
 +
| 64 + 64 KiB
 +
| -
 +
|-
 +
! L2 Cache (KiB)
 +
| colspan="3" | 0.25–1 MiB
 +
| 0.5–2 MiB
 +
| - -
 +
| 2–3 MiB
 +
| -
 +
|-
 +
! L3 Cache (MiB)
 +
| 0–8 MiB
 +
| colspan="2" |0–16 MiB
 +
| colspan="3" |0–32 MiB
 +
| -
 +
|-
 +
! Decode width
 +
| colspan="2" | 5-way
 +
| 6-way
 +
| colspan="3" | 10-way
 +
| -
 +
|-
 +
! Dispatch
 +
| colspan="3" | 8 Mops/cycle
 +
| colspan="3" | 10 Mops/cycle
 +
| -
 +
|-
 +
|}
 +
 +
== References ==
  
  
 
[[Category:arm]]
 
[[Category:arm]]

Latest revision as of 09:30, 13 May 2025

ARM Holdings[edit]

ARM • Versions • Cortex • Neoverse

ARM Microarchitectures[edit]

CPU
ARM Microarchitectures
GeneralDetails
µarchTypeISADesignerIntroductionManufProcessCoresPipeline
Num•Min•Max
ARM1CPUARMv1Acorn Computers1985VLSI Technology3,000 nm
3 μm
0.003 mm
13
ARM2CPUARMv2Acorn Computers1986VLSI Technology, Sanyo2,000 nm
2 μm
0.002 mm
13
ARM3CPUARMv2aAcorn Computers1989VLSI Technology, Sanyo1,500 nm
1.5 μm
0.0015 mm
13
ARM250CPUARMv2aARM Holdings1992VLSI Technology1,000 nm
1 μm
0.001 mm
13
ARM7CPUARMv3ARM Holdings1993VLSI Technology
StrongARMCPUARMv4DEC, ARM Holdings5 February 1996DEC, Intel350 nm
0.35 μm
3.5e-4 mm
15
ARM8CPUARMv4ARM Holdings8 July 1996TSMC
ARM9CPUARM Holdings16 October 1997TSMC, VLSI Technology
ARM10CPUARM Holdings15 October 1998TSMC
ARM11CPUARM Holdings29 April 2002TSMC
Cortex-A8CPUARMv7ARM Holdings5 October 2005TSMC65 nm
0.065 μm
6.5e-5 mm
, 45 nm
0.045 μm
4.5e-5 mm
13
Cortex-A9CPUARMv7ARM Holdings3 October 2007TSMC40 nm
0.04 μm
4.0e-5 mm
Cortex-A5CPUARMv7ARM Holdings22 October 2009TSMC
Cortex-A15CPUARMv7ARM Holdings8 September 2010TSMC
Cortex-A7CPUARMv7ARM Holdings19 October 2011TSMC40 nm
0.04 μm
4.0e-5 mm
, 28 nm
0.028 μm
2.8e-5 mm
Cortex-A53CPUARMv8ARM Holdings30 October 2012TSMC, Samsung, GlobalFoundries40 nm
0.04 μm
4.0e-5 mm
, 28 nm
0.028 μm
2.8e-5 mm
, 20 nm
0.02 μm
2.0e-5 mm
, 16 nm
0.016 μm
1.6e-5 mm
, 14 nm
0.014 μm
1.4e-5 mm
, 10 nm
0.01 μm
1.0e-5 mm
1, 2, 3, 48
Cortex-A57CPUARMv8ARM Holdings30 October 2012TSMC
Cortex-A12CPUARMv7ARM Holdings2 June 2013TSMC
Cortex-A17CPUARMv7ARM Holdings11 February 2014TSMC
Cortex-A72CPUARMv8ARM Holdings23 April 2015TSMC
Cortex-A35CPUARMv8ARM Holdings10 November 2015TSMC
Cortex-A32CPUARMv8 AArch32ARM Holdings23 February 2016TSMC8
Cortex-A73CPUARMv8ARM Holdings29 May 2016TSMC
Cortex-A75CPUARMv8.2ARM Holdings29 May 2017TSMC16 nm
0.016 μm
1.6e-5 mm
, 14 nm
0.014 μm
1.4e-5 mm
, 10 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
1, 2, 4, 81113
Cortex-A55CPUARMv8.2ARM Holdings29 May 2017TSMC, Samsung, GlobalFoundries, SMIC16 nm
0.016 μm
1.6e-5 mm
, 14 nm
0.014 μm
1.4e-5 mm
, 10 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
1, 2, 3, 48
Cortex-A76CPUARMv8.2ARM Holdings31 May 2018TSMC12 nm
0.012 μm
1.2e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4, 6, 813
Neoverse N1CPUARMv8.2ARM Holdings20 February 2019TSMC7 nm
0.007 μm
7.0e-6 mm
4, 8, 16, 32, 64, 96, 12811
Cortex-A77CPUARMv8.2ARM Holdings27 May 2019TSMC, samsung, SMIC10 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4, 6, 813
Cortex-M55CPUARMv8.1-MARM Holdings10 February 2020TSMC55 nm
0.055 μm
5.5e-5 mm
, 45 nm
0.045 μm
4.5e-5 mm
, 32 nm
0.032 μm
3.2e-5 mm
, 28 nm
0.028 μm
2.8e-5 mm
, 22 nm
0.022 μm
2.2e-5 mm
, 16 nm
0.016 μm
1.6e-5 mm
, 10 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 445
Cortex-A78CPUARMv8.2ARM Holdings26 May 2020TSMC10 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4, 6, 813
Cortex-X1 (Hera)CPUARMv8.2ARM Holdings26 May 2020TSMC10 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4, 6, 813
Neoverse N2CPUARMv9.0-AARM Holdings22 September 2020TSMC7 nm
0.007 μm
7.0e-6 mm
4, 8, 16, 32, 64, 96, 12813
Cortex-A710 (Matterhorn)CPUARM Holdings2021TSMC7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4
Cortex-X2 (Matterhorn-ELP)CPUARMv9.0-AARM Holdings2021TSMC5 nm
0.005 μm
5.0e-6 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 10 nm
0.01 μm
1.0e-5 mm
1, 2, 4, 6, 8, 10, 12288
Neoverse V1CPUARMv8.4ARM Holdings27 April 2021TSMC7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
Cortex-A510 (Klein)CPUARMv9.0ARM Holdings25 May 2021TSMC, Samsung, GlobalFoundries, SMIC7 nm
0.007 μm
7.0e-6 mm
, 6 nm
0.006 μm
6.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2
Cortex-A715 (Makalu)CPUARM Holdings2022TSMC7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4
Cortex-X3 (Makalu-ELP)CPUARMv9.0-AARM Holdings2022TSMC10 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4, 6, 8, 10, 12320
Cortex-X4 (Hunter-ELP)CPUARMv9.2-AARM Holdings2023TSMC10 nm
0.01 μm
1.0e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4, 6, 8, 10, 12, 14384
Neoverse V3CPUARMv9.0-AARM Holdings2023TSMC5 nm
0.005 μm
5.0e-6 mm
, 4 nm
0.004 μm
4.0e-6 mm
Cortex-A720 (Hunter)CPUARM Holdings2023TSMC7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4
Cortex-A520 (Hayes)CPUARMv9.2-AARM HoldingsApril 2023TSMC4 nm
0.004 μm
4.0e-6 mm
4
Cortex-A725 (Chaberton)CPUARM Holdings2024TSMC7 nm
0.007 μm
7.0e-6 mm
, 5 nm
0.005 μm
5.0e-6 mm
1, 2, 4
Cortex-X5 (Chaberton-ELP)CPUARM Holdings2024TSMC

Comparison[edit]

"LITTLE" core
µArch Cortex-A53 Cortex-A55 Cortex-A510 Cortex-A520 Cortex-A530
Codename Apollo Ananke Klein Hayes Nevis
Peak clock speed 2.3 GHz 2.1 GHz 2.0 GHz 2.0 GHz -
Architecture ARMv8.0-A ARMv8.2-A ARMv9.0-A ARMv9.2-A ARMv9.4-A
AArch 32-bit and 64-bit 64-bit
L1 (I + D) (KiB) 8/64 + 8/64 KiB 16/64 + 16/64 KiB 32/64 + 32/64 KiB -
L2 Cache (KiB) 0–256 KiB 0–512 KiB -
L3 Cache (MiB) - 0–4 MiB 0–16 MiB 0–32 MiB -
Decode width 2-way 3-way 3-way (2 ALU) -
Dispatch 8 Mops/cycle - - -
"big" core
µArch Cortex-A77 Cortex-A78 Cortex-A710 Cortex-A715 Cortex-A720 Cortex-A725 Cortex-A730
Codename Deimos Hercules Matterhorn Makalu Hunter Chaberton Gelas
Peak clock speed 2.6 GHz ~3.0 GHz - -
Architecture ARMv8.2-A ARMv9.0-A ARMv9.2-A ARMv9.4-A
AArch - 32-bit and 64-bit 64-bit 64-bit
Max In-flight 2x 160 2x 160  ? 2x 192+ [1]  ? - -
L0 (Mops entries) - 1536 0 - -
L1 (I + D) (KiB) 64 + 64 KiB 32/64 + 32/64 KiB 64 + 64 KiB -
L2 Cache (KiB) 256–512 KiB 128–512 KiB 0.25–1 MiB [2] -
L3 Cache (MiB) 0–4 MiB 0–8 MiB 0–16 MiB 0–32 MiB [3] -
Decode width 4-way 5-way -
Dispatch 6 Mops/cycle 5 Mops/cycle  ? - -

Cortex-X[edit]

"Prime" core
µArch Cortex-X1(C) Cortex-X2 Cortex-X3 Cortex-X4 Cortex-X5 Cortex-X925 Cortex-X930
Codename Hera(-C) Matterhorn-ELP Makalu-ELP Hunter-ELP Chaberton-ELP Blackhawk Travis /Alto
Peak clock speed 3.0 GHz 3.0 GHz 3.3 GHz 3.4 GHz - - 3.8 GHz 4.2 GHz
Architecture ARMv8.2-A ARMv9.0-A ARMv9.2-A ARMv9.4-A
AArch 32/64-bit 64-bit 64-bit 64-bit
Max in-flight 2x 224 [4] 2x 288 2x 320 2x 384 - - 2x 768 [5] -
L0 (Mops entries) 3072 [6] 1536 0 [7] - - - -
L1 (I + D) (KiB) 64 + 64 KiB 64 + 64 KiB - - 64 + 64 KiB -
L2 Cache (KiB) 0.25–1 MiB 0.5–2 MiB - - 2–3 MiB -
L3 Cache (MiB) 0–8 MiB 0–16 MiB 0–32 MiB -
Decode width 5-way 6-way 10-way -
Dispatch 8 Mops/cycle 10 Mops/cycle -

References[edit]

  1. ↑ (2022-06-28) Arm introduces Cortex-A715.
  2. ↑ (2024-05-29) Arm launches next gen big core Cortex-A725.
  3. ↑ (2023-05-28) Arm introduces a new big core Cortex-A720.
  4. ↑ Schor, David (2020-05-26). Arm Cortex-X1: The First From The Cortex-X Custom Program.
  5. ↑ https://www.androidauthority.com/arm-cortex-x925-g925-explained-3445480/
  6. ↑ Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence.
  7. ↑ Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm/microarchitectures&oldid=103427"