Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "arm holdings"
(→Microarchitectures) |
(update new GPU IP) |
||
| (43 intermediate revisions by 7 users not shown) | |||
| Line 1: | Line 1: | ||
{{title|ARM Holdings}} | {{title|ARM Holdings}} | ||
{{semi company | {{semi company | ||
| − | | name = | + | | name = Arm Holdings |
| logo = ARM logo.svg | | logo = ARM logo.svg | ||
| logo size = 150px | | logo size = 150px | ||
| Line 27: | Line 27: | ||
}}--> | }}--> | ||
}} | }} | ||
| − | ''' | + | '''Arm Holdings''', usually simply '''Arm''' (previously '''ARM'''), is a British multinational semiconductor and software design company. ARM was spun-off from [[Acorn Computers]] in November [[1990]] as ''Advanced RISC Machines, Ltd.'' (''ARM, Ltd.'') as a joint venture between [[Acorn Computers]], [[Apple Computer]], and [[VLSI Technology]]. |
== Design Groups == | == Design Groups == | ||
| Line 33: | Line 33: | ||
* Austin (Texas) | * Austin (Texas) | ||
| − | ** {{armh|Cortex-A15|l=arch}}, {{armh|Cortex-A57|l=arch}}, {{armh|Cortex-A72|l=arch}}, {{armh|Cortex-A76|l=arch}} | + | ** {{armh|Cortex-A8|l=arch}}, {{armh|Cortex-A15|l=arch}}, {{armh|Cortex-A57|l=arch}}, {{armh|Cortex-A72|l=arch}}, {{armh|Cortex-A76|l=arch}}, {{armh|Cortex-A77|l=arch}}, {{armh|Cortex-A78|l=arch}} |
| + | ** {{armh|Cortex-X1|l=arch}}, {{armh|Cortex-X2|l=arch}}, {{armh|Cortex-X3|l=arch}} | ||
| + | ** {{armh|Neoverse N1|l=arch}}, {{armh|Neoverse N2|l=arch}}, {{armh|Neoverse V1|l=arch}} | ||
* Sophia-Antipolis (France) | * Sophia-Antipolis (France) | ||
| − | ** {{armh|Cortex-A9|l=arch}}, {{armh|Cortex-A12|l=arch}}, {{armh|Cortex-A17|l=arch}}, {{armh|Cortex-A73|l=arch}}, {{armh|Cortex-A75|l=arch}} | + | ** {{armh|ARM11|l=arch}}, {{armh|Cortex-A9|l=arch}}, {{armh|Cortex-A12|l=arch}}, {{armh|Cortex-A17|l=arch}}, {{armh|Cortex-A73|l=arch}}, {{armh|Cortex-A75|l=arch}} |
* Cambridge (UK) | * Cambridge (UK) | ||
** {{armh|Cortex-A5|l=arch}}, {{armh|Cortex-A7|l=arch}}, {{armh|Cortex-A53|l=arch}}, {{armh|Cortex-A35|l=arch}}, {{armh|Cortex-A55|l=arch}} | ** {{armh|Cortex-A5|l=arch}}, {{armh|Cortex-A7|l=arch}}, {{armh|Cortex-A53|l=arch}}, {{armh|Cortex-A35|l=arch}}, {{armh|Cortex-A55|l=arch}} | ||
== Microarchitectures == | == Microarchitectures == | ||
| − | === Classic === | + | === {{\|Classic}}=== |
| + | {{lbox | ||
| + | |'''Classic''' | ||
| + | | | ||
{{collist | {{collist | ||
| count = 4 | | count = 4 | ||
| Line 55: | Line 60: | ||
* {{armh|ARM11|l=arch}} | * {{armh|ARM11|l=arch}} | ||
}} | }} | ||
| − | + | <small>'''Note:''' ARM4 & ARM5 would've been during the time Acorn was spun off as ARM Holdings. The two versions were skipped.</small> | |
| − | === Cortex === | + | }} |
| − | '''Real-Time | + | === {{\|Cortex}} === |
| + | {{lbox | ||
| + | |'''Real-Time''' | ||
| + | | | ||
{{collist | {{collist | ||
| count = 4 | | count = 4 | ||
| Line 65: | Line 73: | ||
* {{armh|Cortex-R7|l=arch}} | * {{armh|Cortex-R7|l=arch}} | ||
* {{armh|Cortex-R8|l=arch}} | * {{armh|Cortex-R8|l=arch}} | ||
| + | * {{armh|Cortex-R82|l=arch}} | ||
'''Functional Safety:''' | '''Functional Safety:''' | ||
| − | * {{armh|Cortex-R4|l=arch}} | + | * {{armh|Cortex-R4|l=arch}} (Serval-E) |
* {{armh|Cortex-R5|l=arch}} | * {{armh|Cortex-R5|l=arch}} | ||
* {{armh|Cortex-R52|l=arch}} | * {{armh|Cortex-R52|l=arch}} | ||
}} | }} | ||
| − | '''Microcontroller | + | }} |
| + | |||
| + | {{lbox | ||
| + | |'''Microcontroller''' | ||
| + | | | ||
{{collist | {{collist | ||
| count = 4 | | count = 4 | ||
| Line 76: | Line 89: | ||
| | | | ||
'''LP/Area:''' | '''LP/Area:''' | ||
| − | * {{armh|Cortex-M0|l=arch}} | + | * {{armh|Cortex-M0|l=arch}} (Swift) |
| − | * {{armh|Cortex-M0+|l=arch}} | + | * {{armh|Cortex-M0+|l=arch}} (Flycatcher) |
| − | * {{armh|Cortex-M23|l=arch}} | + | * {{armh|Cortex-M23|l=arch}} (Grebe) |
'''Performance/efficiency:''' | '''Performance/efficiency:''' | ||
| − | * {{armh|Cortex-M3|l=arch}} | + | * {{armh|Cortex-M3|l=arch}} (Sandcat) |
| − | * {{armh|Cortex-M4|l=arch}} | + | * {{armh|Cortex-M4|l=arch}} (Merlin) |
| − | * {{armh|Cortex-M33|l=arch}} | + | * {{armh|Cortex-M33|l=arch}} (Teal) |
| − | * {{armh|Cortex-M35P|l=arch}} | + | * {{armh|Cortex-M35P|l=arch}} (Tahan) |
'''High Performance:''' | '''High Performance:''' | ||
| − | * {{armh|Cortex-M7|l=arch}} | + | * {{armh|Cortex-M7|l=arch}} (Pelican) |
| + | * {{armh|Cortex-M55|l=arch}} (Yamin) | ||
'''FPGA:''' | '''FPGA:''' | ||
| − | * {{armh|Cortex-M1|l=arch}} | + | * {{armh|Cortex-M1|l=arch}} (Proteus) |
}} | }} | ||
| − | '''Mainstream | + | }} |
| + | |||
| + | {{lbox | ||
| + | |'''Mainstream''' | ||
| + | | | ||
{{collist | {{collist | ||
| count = 4 | | count = 4 | ||
| Line 95: | Line 113: | ||
| | | | ||
* {{armh|Cortex-A8|l=arch}} (Tiger) | * {{armh|Cortex-A8|l=arch}} (Tiger) | ||
| − | * {{armh|Cortex-A9|l=arch}} | + | * {{armh|Cortex-A9|l=arch}} (Falcon) |
'''ULP:''' | '''ULP:''' | ||
| − | * {{armh|Cortex-A5|l=arch}} | + | * {{armh|Cortex-A5|l=arch}} (Sparrow) |
| + | * {{armh|Cortex-A34|l=arch}} (Metis) | ||
* {{armh|Cortex-A35|l=arch}} (Mercury) | * {{armh|Cortex-A35|l=arch}} (Mercury) | ||
| − | * {{armh|Cortex-A32|l=arch}} | + | * {{armh|Cortex-A32|l=arch}} (Minerva) |
'''[[little core|Little]]:''' | '''[[little core|Little]]:''' | ||
* {{armh|Cortex-A7|l=arch}} (Kingfisher) | * {{armh|Cortex-A7|l=arch}} (Kingfisher) | ||
* {{armh|Cortex-A53|l=arch}} (Apollo) | * {{armh|Cortex-A53|l=arch}} (Apollo) | ||
* {{armh|Cortex-A55|l=arch}} (Ananke) | * {{armh|Cortex-A55|l=arch}} (Ananke) | ||
| − | * {{armh| | + | * {{armh|Cortex-A510|l=arch}} (Klein) |
| + | * {{armh|Hayes|l=arch}} | ||
'''Mid-Range''' | '''Mid-Range''' | ||
* <s>{{armh|Cortex-A12|l=arch}}</s> (Owl) | * <s>{{armh|Cortex-A12|l=arch}}</s> (Owl) | ||
| − | * {{armh|Cortex-A17|l=arch}} | + | * {{armh|Cortex-A17|l=arch}} (Owl) |
'''[[big core|Big]]:''' | '''[[big core|Big]]:''' | ||
* {{armh|Cortex-A15|l=arch}} (Eagle) | * {{armh|Cortex-A15|l=arch}} (Eagle) | ||
* {{armh|Cortex-A57|l=arch}} (Atlas) | * {{armh|Cortex-A57|l=arch}} (Atlas) | ||
| − | * {{armh|Cortex-A72|l=arch}} ( | + | * {{armh|Cortex-A72|l=arch}} (Maia) |
* {{armh|Cortex-A73|l=arch}} (Artemis) | * {{armh|Cortex-A73|l=arch}} (Artemis) | ||
* {{armh|Cortex-A75|l=arch}} (Prometheus) | * {{armh|Cortex-A75|l=arch}} (Prometheus) | ||
* {{armh|Cortex-A76|l=arch}} (Enyo) | * {{armh|Cortex-A76|l=arch}} (Enyo) | ||
| − | * {{armh|Deimos|l=arch}} | + | * {{armh|Cortex-A77|l=arch}} (Deimos) |
| − | * {{armh|Hercules|l=arch}} | + | * {{armh|Cortex-A78|l=arch}} (Hercules) |
| + | * {{armh|Cortex-A710|l=arch}} (Matterhorn) | ||
| + | * {{armh|Cortex-A715|l=arch}} (Makalu) | ||
| + | * {{armh|Hunter|l=arch}} | ||
| + | * {{armh|Chaberton|l=arch}} | ||
| + | |||
| + | |||
| + | * {{armh|Cortex-A78C|l=arch}} (Hercules-C) | ||
| + | '''[[big core|Bigger]]:''' | ||
| + | * {{armh|Cortex-X1|l=arch}} (Hera) | ||
| + | * {{armh|Cortex-X2|l=arch}} (Matterhorn-ELP) | ||
| + | * {{armh|Cortex-X3|l=arch}} (Makalu-ELP) | ||
| + | * {{armh|Hunter-ELP|l=arch}} | ||
| + | * {{armh|Chaberton-ELP|l=arch}} | ||
| + | |||
| + | |||
| + | * {{armh|Cortex-X1C|l=arch}} (Hera-C) | ||
'''Autonomous Machines:''' | '''Autonomous Machines:''' | ||
| − | * {{armh|Cortex-A76AE|l=arch}} | + | * {{armh|Cortex-A76AE|l=arch}} (Enyo-SL) |
| − | * {{armh|Cortex-A65AE|l=arch}} | + | * {{armh|Cortex-A78AE|l=arch}} (Hercules-AE) |
| + | * {{armh|Cortex-A65AE|l=arch}} (Helios-SL) | ||
| + | }} | ||
}} | }} | ||
| − | === Neoverse === | + | === {{\|Neoverse}} === |
| − | '''Servers | + | {{lbox |
| + | |'''Servers''' | ||
| + | | | ||
{{collist | {{collist | ||
| count = 4 | | count = 4 | ||
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
| + | '''Performance''' | ||
* {{armh|Cosmos|l=arch}} | * {{armh|Cosmos|l=arch}} | ||
| − | * {{armh| | + | * {{armh|Neoverse N1|l=arch}} (Ares) |
| − | * {{armh| | + | * {{armh|Neoverse N2|l=arch}} (Perseus) |
* {{armh|Poseidon|l=arch}} | * {{armh|Poseidon|l=arch}} | ||
| + | '''HPC''' | ||
| + | * {{armh|Neoverse V1|l=arch}} (Zeus) | ||
| + | * {{armh|Demeter|l=arch}} | ||
| + | '''Throughput''' | ||
| + | * {{armh|Neoverse E1|l=arch}} (Helios) | ||
| + | }} | ||
}} | }} | ||
=== Other === | === Other === | ||
| + | {{lbox | ||
| + | |'''Other IP''' | ||
| + | | | ||
{{collist | {{collist | ||
| count = 4 | | count = 4 | ||
| Line 144: | Line 194: | ||
* {{armh|SC300|l=arch}} | * {{armh|SC300|l=arch}} | ||
'''[[Neural Processors]]:''' | '''[[Neural Processors]]:''' | ||
| − | * {{armh|ARM | + | * {{armh|ARM MLP|l=arch}} |
| + | * {{armh|Ethos}} | ||
| + | }} | ||
}} | }} | ||
| + | |||
| + | == GPUs == | ||
| + | * {{armh|Mali}} | ||
| + | * {{armh|Immortalis}} | ||
== Architectures == | == Architectures == | ||
Latest revision as of 21:02, 3 November 2022
| Arm Holdings | |
| |
| Type | Public |
| Founded | November 27, 1990 |
| Founder | Jamie Urquhart Mike Muller Tudor Brown Lee Smith John Biggs Harry Oldham Dave Howard Pete Harrod Harry Meekings Al Thomas Andy Merritt |
| Headquarters | Cambridge, England |
| Website | http://www.arm.com |
Arm Holdings, usually simply Arm (previously ARM), is a British multinational semiconductor and software design company. ARM was spun-off from Acorn Computers in November 1990 as Advanced RISC Machines, Ltd. (ARM, Ltd.) as a joint venture between Acorn Computers, Apple Computer, and VLSI Technology.
Contents
Design Groups[edit]
Arm processors can largely be grouped into the three design teams that design them in parallel:
- Austin (Texas)
- Sophia-Antipolis (France)
- Cambridge (UK)
Microarchitectures[edit]
Classic[edit]
Cortex[edit]
Real-Time
Microcontroller
LP/Area:
- Cortex-M0 (Swift)
- Cortex-M0+ (Flycatcher)
- Cortex-M23 (Grebe)
Performance/efficiency:
- Cortex-M3 (Sandcat)
- Cortex-M4 (Merlin)
- Cortex-M33 (Teal)
- Cortex-M35P (Tahan)
High Performance:
- Cortex-M7 (Pelican)
- Cortex-M55 (Yamin)
FPGA:
- Cortex-M1 (Proteus)
Mainstream
ULP:
- Cortex-A5 (Sparrow)
- Cortex-A34 (Metis)
- Cortex-A35 (Mercury)
- Cortex-A32 (Minerva)
- Cortex-A7 (Kingfisher)
- Cortex-A53 (Apollo)
- Cortex-A55 (Ananke)
- Cortex-A510 (Klein)
- Hayes
Mid-Range
-
Cortex-A12(Owl) - Cortex-A17 (Owl)
Big:
- Cortex-A15 (Eagle)
- Cortex-A57 (Atlas)
- Cortex-A72 (Maia)
- Cortex-A73 (Artemis)
- Cortex-A75 (Prometheus)
- Cortex-A76 (Enyo)
- Cortex-A77 (Deimos)
- Cortex-A78 (Hercules)
- Cortex-A710 (Matterhorn)
- Cortex-A715 (Makalu)
- Hunter
- Chaberton
- Cortex-A78C (Hercules-C)
- Cortex-X1 (Hera)
- Cortex-X2 (Matterhorn-ELP)
- Cortex-X3 (Makalu-ELP)
- Hunter-ELP
- Chaberton-ELP
- Cortex-X1C (Hera-C)
Autonomous Machines:
- Cortex-A76AE (Enyo-SL)
- Cortex-A78AE (Hercules-AE)
- Cortex-A65AE (Helios-SL)
Neoverse[edit]
Servers
Performance
- Cosmos
- Neoverse N1 (Ares)
- Neoverse N2 (Perseus)
- Poseidon
HPC
- Neoverse V1 (Zeus)
- Demeter
Throughput
- Neoverse E1 (Helios)
Other[edit]
GPUs[edit]
Architectures[edit]
GPU:
ISAs[edit]
Other topics[edit]
See Also[edit]
Facts about "ARM Holdings"
| company type | public + |
| founded | November 27, 1990 + |
| founder | Jamie Urquhart +, Mike Muller +, Tudor Brown +, Lee Smith +, John Biggs +, Harry Oldham +, Dave Howard +, Pete Harrod +, Harry Meekings +, Al Thomas + and Andy Merritt + |
| full page name | arm holdings + |
| headquarters | Cambridge, England + |
| instance of | semiconductor company + |
| name | Arm Holdings + |
| website | http://www.arm.com + |
| wikidata id | Q296782 + |