Page title matches

• arm holdings/microarchitectures/cortex-m55
  |designer=ARM Holdings ...be implemented in their own chips. The Cortex-M55, which implements the {{arm|ARMv8.1-M}} ISA, is an ultra-low-power core which is often found in microco
  12 KB (1,806 words) - 10:51, 12 January 2021
• arm holdings/microarchitectures/cortex-x1
  |designer=ARM Holdings |successor link=arm holdings/microarchitectures/cortex-x2
  7 KB (995 words) - 14:21, 4 July 2022
• arm holdings/microarchitectures/cortex-a715
  |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a710
  625 bytes (70 words) - 13:51, 4 July 2022
• arm holdings/microarchitectures/cortex-a510
  |designer=ARM Holdings ...to the {{armh|Cortex-A55|l=arch}}. The Cortex-A510, which implements the {{arm|ARMv9.0}} ISA, is typically found in smartphone and other embedded devices.
  15 KB (2,282 words) - 11:20, 10 January 2023
• arm holdings/microarchitectures/cortex-x2
  |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-x1
  588 bytes (63 words) - 14:27, 4 July 2022
• arm holdings/microarchitectures/cortex-x3
  |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-x2
  590 bytes (63 words) - 14:29, 4 July 2022

Page text matches

• renesas/r-car/m1a
  |designer 2=ARM Holdings |isa family=ARM
  3 KB (415 words) - 16:32, 13 December 2017
• renesas/r-car/m1s
  {{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
  2 KB (299 words) - 16:32, 13 December 2017
• renesas/r-car/e1
  |designer 2=ARM Holdings |isa family=ARM
  2 KB (337 words) - 16:32, 13 December 2017
• renesas/r-car/l1
  |designer 2=ARM Holdings |isa family=ARM
  2 KB (248 words) - 16:32, 13 December 2017
• renesas/r-car/h2
  |designer 2=ARM Holdings |isa family=ARM
  3 KB (420 words) - 16:32, 13 December 2017
• renesas/r-car/m2
  |designer 2=ARM Holdings |isa family=ARM
  3 KB (409 words) - 16:32, 13 December 2017
• renesas/r-car/e2
  |designer 2=ARM Holdings |isa family=ARM
  3 KB (409 words) - 16:32, 13 December 2017
• renesas/r-car/v2h
  |designer 2=ARM Holdings |isa family=ARM
  2 KB (346 words) - 16:32, 13 December 2017
• renesas/r-car/m3
  |designer 2=ARM Holdings |isa family=ARM
  3 KB (365 words) - 16:32, 13 December 2017
• renesas/r-car/m3 (sip)
  |designer 2=ARM Holdings |isa family=ARM
  3 KB (383 words) - 16:32, 13 December 2017
• renesas/r-car/h3
  |designer 2=ARM Holdings |isa family=ARM
  4 KB (571 words) - 15:43, 29 December 2018
• renesas/r-car/h3 (sip)
  |designer 2=ARM Holdings |isa family=ARM
  4 KB (495 words) - 16:32, 13 December 2017
• hisilicon/k3/k3v2
  |designer 2=ARM Holdings |isa family=ARM
  3 KB (467 words) - 04:41, 21 July 2018
• hisilicon/k3/k3v2e
  |designer 2=ARM Holdings |isa family=ARM
  2 KB (334 words) - 16:13, 13 December 2017
• hisilicon/kirin
  | developer 2 = ARM Holdings | arch = Performance mobile ARM SOCs
  3 KB (316 words) - 06:18, 3 October 2023
• hisilicon/kirin/970
  |designer 2=ARM Holdings |isa family=ARM
  6 KB (824 words) - 17:25, 1 January 2022
• mediatek/helio/mt6763t
  |designer 2=ARM Holdings |isa family=ARM
  4 KB (534 words) - 05:37, 26 May 2023
• mediatek/helio/p30
  |designer 2=ARM Holdings |isa family=ARM
  2 KB (307 words) - 06:55, 26 June 2019
• 2018
  * February 5: [[Ampere Computing]] announces their first ARM processor, the {{ampere|A1}}. * February 13: [[ARM Holdings|ARM]] announces two new [[neural processors]] IPs - the {{armh|ML processor}} f
  5 KB (639 words) - 01:27, 30 December 2019
• samsung/exynos/9810
  |designer 2=ARM Holdings |isa family=ARM
  5 KB (622 words) - 10:43, 7 March 2024

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