From WikiChip
Difference between revisions of "intel/microarchitectures"
< intel

(→‎CPU Microarchitectures)
(→‎CPU Microarchitectures)
 
Line 6: Line 6:
 
<table class="wikitable sortable">
 
<table class="wikitable sortable">
 
<tr><th colspan="12" style="background:#D6D6FF;">Intel CPU Microarchitectures</th></tr>
 
<tr><th colspan="12" style="background:#D6D6FF;">Intel CPU Microarchitectures</th></tr>
−
<tr><th colspan="5">General</th><th colspan="5">Details</th></tr>
+
<tr><th colspan="6">General</th><th colspan="5">Details</th></tr>
−
<tr><th>µarch</th><th>Type</th><th>Manuf</th><th>Introduction</th><th>Phase-out</th><th>[[technology node|Process]]</th><th>Cores</th><th colspan="3">Pipeline<br>Num•Min•Max</th></tr>
+
<tr><th>µarch</th><th>Type</th><th>[[ISA]]</th><th>Manuf</th><th>Introduction</th><th>Phase-out</th><th>[[technology node|Process]]</th><th>Cores</th><th colspan="3">Pipeline<br>Num•Min•Max</th></tr>
 
{{#ask:
 
{{#ask:
 
  [[Category:cpu microarchitectures by intel]]
 
  [[Category:cpu microarchitectures by intel]]
Line 15: Line 15:
 
  |?name
 
  |?name
 
  |?microarchitecture_type
 
  |?microarchitecture_type
 +
|?instruction_set_architecture
 
  |?manufacturer
 
  |?manufacturer
 
  |?first launched#ISO
 
  |?first launched#ISO
Line 28: Line 29:
 
  |format=template
 
  |format=template
 
  |template=proc table 2
 
  |template=proc table 2
−
  |userparam=11
+
  |userparam=12
 
  |valuesep=,
 
  |valuesep=,
 
  |mainlabel=-
 
  |mainlabel=-
Line 36: Line 37:
 
=== Newest models ===
 
=== Newest models ===
 
:;TSMC N3B ([[3 nm]])
 
:;TSMC N3B ([[3 nm]])
−
* {{intel|Lunar Lake|l=arch}} (hybrid) • Lion Cove (P)/Skymont (E) • Ultra 200V • 2024-09
+
* {{intel|Lunar Lake|l=arch}} (hybrid) • ''Lion Cove'' (P)/''Skymont'' (E) • Ultra 200V • 2024-09
−
* {{intel|Arrow Lake|l=arch}} (hybrid) • Ultra Series 2 • 2024-10 (desktop)/2025-01 (mobile)
+
* {{intel|Arrow Lake|l=arch}} (hybrid) • ''Ultra'' Series 2 • 2024-10 (desktop)/2025-01 (mobile)
 
:;[[Intel]] 18A
 
:;[[Intel]] 18A
−
* {{intel|Panther Lake|l=arch}} (hybrid) • ''Cougar Cove'' (P)/''Darkmont,, (E) • Ultra 300 • 2025
+
* {{intel|Panther Lake|l=arch}} (hybrid) • ''Cougar Cove'' (P)/''Darkmont'' (E) • ''Ultra'' 300 • 2025
 
* {{intel|Diamond Rapids|l=arch}} • ''Panther Cove X'' (''Mountain Stream'') • 2025
 
* {{intel|Diamond Rapids|l=arch}} • ''Panther Cove X'' (''Mountain Stream'') • 2025
 
:;[[Intel]] 18A (or [[TSMC]] [[2 nm]])
 
:;[[Intel]] 18A (or [[TSMC]] [[2 nm]])

Latest revision as of 05:00, 4 March 2025

Below is a list of Intel microarchitectures:

CPU Microarchitectures[edit]

See also: Intel, Lake, Core, and intel/core


Intel CPU Microarchitectures
GeneralDetails
µarchTypeISAManufIntroductionPhase-outProcessCoresPipeline
Num•Min•Max
80386CPUx86-32Intel1984-03-011989-01-011,500 nm
1.5 μm
0.0015 mm
80486CPUx86-32Intel, AMD1989-04-101995-01-011,000 nm
1 μm
0.001 mm
, 800 nm
0.8 μm
8.0e-4 mm
, 600 nm
0.6 μm
6.0e-4 mm
P5CPUx86-32Intel1993-04-011995-10-01600 nm
0.6 μm
6.0e-4 mm
P6CPUx86-32Intel1995-10-012000-12-01350 nm
0.35 μm
3.5e-4 mm
, 250 nm
0.25 μm
2.5e-4 mm
NetBurstCPUx86-32, x86-64Intel2000-11-202006-04-01180 nm
0.18 μm
1.8e-4 mm
MercedCPUIA-64Intel2001-06-01180 nm
0.18 μm
1.8e-4 mm
1
McKinleyCPUIA-64Intel2002-07-08180 nm
0.18 μm
1.8e-4 mm
1, 2
Pentium MCPUx86-16, x86-32Intel2003-01-012005-01-01130 nm
0.13 μm
1.3e-4 mm
, 90 nm
0.09 μm
9.0e-5 mm
MadisonCPUIA-64Intel2003-06-30130 nm
0.13 μm
1.3e-4 mm
1
Madison 9MCPUIA-64Intel2004-11-08130 nm
0.13 μm
1.3e-4 mm
1
Modified Pentium MCPUx86-16, x86-32Intel2006-01-012008-01-0165 nm
0.065 μm
6.5e-5 mm
CoreCPUx86-64Intel2006-04-012009-05-0165 nm
0.065 μm
6.5e-5 mm
MontecitoCPUIA-64Intel2006-07-1890 nm
0.09 μm
9.0e-5 mm
1, 2
PolarisCPUIntel2007-02-0165 nm
0.065 μm
6.5e-5 mm
809
MontvaleCPUIA-64Intel2007-10-3190 nm
0.09 μm
9.0e-5 mm
1, 2
PenrynCPUx86-64Intel2007-11-012008-09-0145 nm
0.045 μm
4.5e-5 mm
BonnellCPUx86-64Intel2008-03-022011-01-0145 nm
0.045 μm
4.5e-5 mm
1, 21619
NehalemCPUx86-64Intel2008-08-012010-03-0145 nm
0.045 μm
4.5e-5 mm
Rock CreekCPUx86Intel2009-12-0145 nm
0.045 μm
4.5e-5 mm
48
WestmereCPUx86-64Intel2010-01-012011-08-0132 nm
0.032 μm
3.2e-5 mm
TukwilaCPUIA-64Intel2010-02-0865 nm
0.065 μm
6.5e-5 mm
1, 2
Knights FerryCPUx86Intel2010-05-312011-01-0145 nm
0.045 μm
4.5e-5 mm
32
Sandy Bridge (client)CPUx86-64Intel2010-09-132012-11-0132 nm
0.032 μm
3.2e-5 mm
2, 41419
SaltwellCPUx86-64Intel2011-01-012013-01-0132 nm
0.032 μm
3.2e-5 mm
1, 216
Knights CornerCPUx86Intel2011-01-012013-01-0122 nm
0.022 μm
2.2e-5 mm
57, 60, 61
Ivy BridgeCPUx86-64Intel2011-05-042013-04-0122 nm
0.022 μm
2.2e-5 mm
PoulsonCPUIA-64Intel2012-11-0832 nm
0.032 μm
3.2e-5 mm
1, 2
SilvermontCPUx86-64Intel2013-01-012015-01-0122 nm
0.022 μm
2.2e-5 mm
1, 2, 4, 81214
HaswellCPUx86-64Intel2013-06-042015-01-0122 nm
0.022 μm
2.2e-5 mm
2, 4, 6, 8, 16, 10, 12, 14, 181419
BroadwellCPUx86-64Intel2014-10-0114 nm
0.014 μm
1.4e-5 mm
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 221419
AirmontCPUx86-64Intel2015-01-012017-01-0114 nm
0.014 μm
1.4e-5 mm
1, 2, 4, 81214
Skylake (client)CPUx86-64Intel2015-08-0514 nm
0.014 μm
1.4e-5 mm
2, 41419
Kaby LakeCPUx86-64Intel2016-08-3014 nm
0.014 μm
1.4e-5 mm
2, 41419
GoldmontCPUx86-64Intel2016-08-3014 nm
0.014 μm
1.4e-5 mm
2, 4, 8, 12, 161214
KittsonCPUIA-64Intel2017-01-0122 nm
0.022 μm
2.2e-5 mm
1, 2
Skylake (server)CPUx86-64Intel2017-05-0414 nm
0.014 μm
1.4e-5 mm
4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 281419
Coffee LakeCPUx86-64Intel, dell2017-10-0514 nm
0.014 μm
1.4e-5 mm
1419
Goldmont PlusCPUx86-64Intel2017-12-1114 nm
0.014 μm
1.4e-5 mm
2, 4
Knights MillCPUx86-16, x86-32, x86-64Intel2017-12-182019-08-0914 nm
0.014 μm
1.4e-5 mm
Palm CoveCPUx86-64Intel2018-01-0110 nm
0.01 μm
1.0e-5 mm
21419
Whiskey LakeCPUx86-64Intel2018-04-0141419
Amber LakeCPUx86-64Intel2018-04-0114 nm
0.014 μm
1.4e-5 mm
21419
Cannon LakeCPUx86-64Intel2018-05-1510 nm
0.01 μm
1.0e-5 mm
21419
LakefieldCPUx86-64Intel2019-01-0122 nm
0.022 μm
2.2e-5 mm
, 10 nm
0.01 μm
1.0e-5 mm
5
Cascade LakeCPUx86-64Intel2019-01-0114 nm
0.014 μm
1.4e-5 mm
2, 4, 6, 8, 10, 12, 16, 18, 20, 22, 24, 26, 28, 32, 48, 561419
TremontCPUx86-64Intel2019-01-0110 nm
0.01 μm
1.0e-5 mm
Snow RidgeCPUx86-64Intel2019-01-0110 nm
0.01 μm
1.0e-5 mm
Sunny CoveCPUx86-64Intel2019-01-012021-01-0110 nm
0.01 μm
1.0e-5 mm
2, 4, 8, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 401419
Ice Lake (client)CPUx86-64Intel2019-05-2710 nm
0.01 μm
1.0e-5 mm
2, 41419
Willow CoveCPUx86-64Intel2020-01-0110 nm
0.01 μm
1.0e-5 mm
2, 4, 6, 81419
Cooper LakeCPUx86-64Intel2020-06-1828, 24, 20, 18, 16, 81419
Tiger LakeCPUx86-64Intel2020-09-0210 nm
0.01 μm
1.0e-5 mm
2, 4, 6, 81419
GracemontCPUx86-64Intel2021-01-0110 nm
0.01 μm
1.0e-5 mm
Alder LakeCPUx86-64Intel2021-01-0110 nm
0.01 μm
1.0e-5 mm
16, 14, 10, 6
Rocket LakeCPUx86-64Intel2021-03-1614 nm
0.014 μm
1.4e-5 mm
4, 6, 81419
Ice Lake (server)CPUx86-64Intel2021-04-018, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 401419
Golden CoveCPUx86-64Intel2021-11-0410 nm
0.01 μm
1.0e-5 mm
Ocean CoveCPUx86-64Intel2022-01-01
Raptor LakeCPUx86-64Intel2022-09-2724, 16, 8
Sapphire RapidsCPUx86-64Intel2023-01-01
Emerald RapidsCPUx86-64Intel2023-01-01
Meteor LakeCPUx86-64Intel2023-01-01
Granite RapidsCPUx86-64Intel2024-01-01120, 80, 40
Sierra ForestCPUx86-64Intel2024-06-04
Diamond RapidsCPUx86-64Intel2025-01-01

Newest models[edit]

TSMC N3B (3 nm)
  • Lunar Lake (hybrid) • Lion Cove (P)/Skymont (E) • Ultra 200V • 2024-09
  • Arrow Lake (hybrid) • Ultra Series 2 • 2024-10 (desktop)/2025-01 (mobile)
Intel 18A
  • Panther Lake (hybrid) • Cougar Cove (P)/Darkmont (E) • Ultra 300 • 2025
  • Diamond Rapids • Panther Cove X (Mountain Stream) • 2025
Intel 18A (or TSMC 2 nm)

GPU Microarchitectures[edit]

Intel GPU Microarchitectures
GeneralDetails
µarchIntroductionPhase-outProcess
Gen11998-01-01
Gen22002-01-01
Gen32004-01-01
Gen3.52005-01-0190 nm
0.09 μm
9.0e-5 mm
Gen42006-01-0165 nm
0.065 μm
6.5e-5 mm
Gen52008-06-0345 nm
0.045 μm
4.5e-5 mm
Larrabee2008-08-122010-01-0132 nm
0.032 μm
3.2e-5 mm
, 45 nm
0.045 μm
4.5e-5 mm
Gen5.752010-01-0145 nm
0.045 μm
4.5e-5 mm
Gen62010-09-1332 nm
0.032 μm
3.2e-5 mm
Gen72011-05-0422 nm
0.022 μm
2.2e-5 mm
Gen7.52013-06-0422 nm
0.022 μm
2.2e-5 mm
Gen82014-10-0114 nm
0.014 μm
1.4e-5 mm
Gen92015-08-0514 nm
0.014 μm
1.4e-5 mm
Gen9.52016-08-3014 nm
0.014 μm
1.4e-5 mm
Gen112018-01-0110 nm
0.01 μm
1.0e-5 mm
Gen102018-01-0110 nm
0.01 μm
1.0e-5 mm
Gen122020-01-0110 nm
0.01 μm
1.0e-5 mm
Arctic Sound2020-01-0110 nm
0.01 μm
1.0e-5 mm
Jupiter Sound2022-01-0110 nm
0.01 μm
1.0e-5 mm

Many-core[edit]

Under construction icon-blue.svg This article is a work in progress!

Initial effort & Polaris[edit]

Intel actual large effort research into the area of many-core started after the February 2004 Intel Developer Forum following Pradeep Dubey famous keynote titled "The Era of Tera." Around the 2004-2005 Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the Tera-scale Computing Research Program which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.

The first product to come directly from that project was Polaris, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a mesh topology. Fabricated on a 65 nm process, the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. 3D stacked SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 teraFLOPS of sustained performance.

Larrabee[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures&oldid=102902"