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{{x86 title|Extensions}}
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{{x86 title|Extensions}}{{x86 isa main}}
 
The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations that added new [[instructions]] to performs specific tasks. These collections of new instructions are grouped into '''extensions'''. Different microprocessor models have different levels of support for certain extensions.
 
The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations that added new [[instructions]] to performs specific tasks. These collections of new instructions are grouped into '''extensions'''. Different microprocessor models have different levels of support for certain extensions.
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== Overview ==
 +
The [[x86]] ISA has been developed over the course of forty years. Various extensions have been proposed and implemented by various vendors in order to enhance the functionality of the base instruction set.
  
 
== Timeline ==
 
== Timeline ==
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| [[1978]] || {{\|Real}} || {{intel|8086|l=arch}} || Original Real mode
 
| [[1978]] || {{\|Real}} || {{intel|8086|l=arch}} || Original Real mode
 
|-
 
|-
−
| [[1982]] || {{\|Protected}} || {{intel|80186|l=arch}} || Protected mode
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| [[1982]] || {{\|Protected}} || {{intel|80286|l=arch}} || Protected mode
 
|-
 
|-
 
| [[1985]] || {{\|SMM}} || {{intel|80386|l=arch}} || System Management Mode
 
| [[1985]] || {{\|SMM}} || {{intel|80386|l=arch}} || System Management Mode
Line 24: Line 27:
 
| [[1999]] || {{\|Professional 3DNow!}} || || A name given by AMD for {{\|E3DNow!}} + {{\|SSE}}
 
| [[1999]] || {{\|Professional 3DNow!}} || || A name given by AMD for {{\|E3DNow!}} + {{\|SSE}}
 
|-
 
|-
−
| [[1999]] || {{\|EMMX}} || {{\|P6}} || Extended MMX; an extension to MMX
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| [[1999]] || {{\|EMMX}} || {{intel|P6|l=arch}} || Extended MMX; an extension to MMX
 
|-
 
|-
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| [[2001]] || {{x86|SSE2}} || {{intel|P6|l=arch}} || Attempt to replace the original {{\|MMX}} instructions; use wider {{x86|XMM}} registers have offer better performance
+
| [[2001]] || {{x86|SSE2}} || {{intel|P6|l=arch}} || Attempt to replace the original {{\|MMX}} instructions; wider {{x86|XMM}} registers offer better performance
 
|-
 
|-
 
| [[2004]] || {{x86|SSE3}} || {{intel|Core|l=arch}} || Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register
 
| [[2004]] || {{x86|SSE3}} || {{intel|Core|l=arch}} || Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register
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|-
 
|-
 
| [[2008]] || {{x86||SSE4}} || || Streaming SIMD Extensions 4; Another name for SSE4.1 + SSE4.2
 
| [[2008]] || {{x86||SSE4}} || || Streaming SIMD Extensions 4; Another name for SSE4.1 + SSE4.2
−
|-
 
−
| [[2009]] || {{x86|XOP}} || {{amd|Bulldozer|l=arch}} || eXtended Operations; various vector operations
 
 
|-
 
|-
 
| [[2010]] || {{x86|CLMUL}} || {{intel|Westmere|l=arch}} || Carry-less multiplication of two registers
 
| [[2010]] || {{x86|CLMUL}} || {{intel|Westmere|l=arch}} || Carry-less multiplication of two registers
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|-
 
|-
 
| [[2012]] || {{x86|F16C}} || {{intel|Ivy Bridge|l=arch}} || Extension for performing half-precision <-> single-precision conversions
 
| [[2012]] || {{x86|F16C}} || {{intel|Ivy Bridge|l=arch}} || Extension for performing half-precision <-> single-precision conversions
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|-
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| [[2011]] || {{x86|XOP}} || {{amd|Bulldozer|l=arch}} || eXtended Operations; various vector operations
 
|-
 
|-
 
| [[2011]] || {{x86|FMA4}} || {{amd|Bulldozer|l=arch}} || 4-operands fused multiply-add
 
| [[2011]] || {{x86|FMA4}} || {{amd|Bulldozer|l=arch}} || 4-operands fused multiply-add
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|-
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| [[2011]] || {{x86|LWP}} || {{amd|Bulldozer|l=arch}} || Lightweight Profiling
 
|-
 
|-
 
| [[2011]] || {{x86|SMX}} || {{intel|Nehalem|l=arch}} || Safer Mode Extensions; instructions needed to facilitate trust decisions (Part of Intel's {{intel|Trusted Execution Technology}})
 
| [[2011]] || {{x86|SMX}} || {{intel|Nehalem|l=arch}} || Safer Mode Extensions; instructions needed to facilitate trust decisions (Part of Intel's {{intel|Trusted Execution Technology}})
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| [[2013]] || {{x86|AVX2}} || {{intel|Haswell|l=arch}} || Advanced Vector Extensions; additional instructions
 
| [[2013]] || {{x86|AVX2}} || {{intel|Haswell|l=arch}} || Advanced Vector Extensions; additional instructions
 
|-
 
|-
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| [[2014]] || {{x86|ADX}} || {{intel|Haswell|l=arch}} || Multi-Precision Add-Carry Instruction extension  
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| [[2014]] || {{x86|ADX}} || {{intel|Broadwell|l=arch}} || Multi-Precision Add-Carry Instruction extension  
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|-
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| [[2014]] || {{x86|RdRand}} || {{intel|Broadwell|l=arch}} || Part of Secure Key Technology extension (RdRand, RDSEED)
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|-
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| [[2014]] || {{x86|PREFETCH}} || {{intel|Broadwell|l=arch}} || PREFETCH instructions (previously part of {{\|3DNow!}})
 
|-
 
|-
 
| [[2015]] || {{x86|AVX-512}} || {{intel|Airmont|l=arch}} || 512 bit register operations
 
| [[2015]] || {{x86|AVX-512}} || {{intel|Airmont|l=arch}} || 512 bit register operations
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|-
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| [[2015]] || {{x86|MPX}} || {{intel|Skylake|l=arch}} || Memory Protection Extensions
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|-
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| [[2015]] || {{x86|SGX}} || {{intel|Skylake|l=arch}} || Software Guard Extensions
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|-
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| [[2016]] || {{x86|SHA}} || {{intel|Goldmont|l=arch}} || SHA Extensions
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|-
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| [[2017]] || {{x86|SME}} || {{amd|Zen|l=arch}} || Secure Memory Extensions
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|-
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| [[2019]] || {{x86|TME}} || {{intel|Ice Lake (server)|Ice Lake|l=arch}} || Total Memory Encryption
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|}
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== Experimental Extensions ==
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{| class="wikitable"
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! !! Extension !! First [[µarch]] !! Description
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|-
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| [[2008]] || {{\|L1OM}} || {{intel|Larrabee|l=arch}} || 512-bit vector extension
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|-
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| [[2010]] || {{\|K1OM}} || {{intel|Knights Corner|l=arch}} || 512-bit vector extension
 
|}
 
|}
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== Backwards compatibility ==
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Generally speaking, all extensions are supported from their introductory date to present day. Extensions introduced by AMD's {{amd|K6-2|l=arch}} (i.e., {{x86|3DNow!}} & {{x86|E3DNow!}}) and those introduced by AMD's {{amd|Bulldozer|l=arch}} (i.e., {{x86|FMA4}}, {{x86|XOP}}, {{x86|LWP}}, and later {{x86|TBM}}) have been obsoleted. Note that {{amd|Zen|l=arch}}, at least for first stepping, still offered FMA4 support even though it's not indicated by {{x86|CPUID}}.
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== See also ==
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* {{arm|Versions|ARM's Versions}}
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 +
[[Category:x86]]

Latest revision as of 07:53, 7 June 2020

x86
Instruction Set Architecture
General
Variants
Topics
CPUIDs
Modes
Extensions(all)
v · d · e

The x86 ISA has gone through numerous iterations that added new instructions to performs specific tasks. These collections of new instructions are grouped into extensions. Different microprocessor models have different levels of support for certain extensions.

Overview[edit]

The x86 ISA has been developed over the course of forty years. Various extensions have been proposed and implemented by various vendors in order to enhance the functionality of the base instruction set.

Timeline[edit]

Extension First µarch Description
1978 Real 8086 Original Real mode
1982 Protected 80286 Protected mode
1985 SMM 80386 System Management Mode
1989 FPU 80486 Incorporates the x87 FPU into the same die
1996 MMX P5 First implementation for SIMD instructions
1998 3DNow! K6-2 SIMD extension for manipulating single-precision floating point
1999 SSE P5 Streaming SIMD Extensions, SIMD for single-precision floating point
1999 E3DNow! K7 Extended 3DNow! (New DSP instructions + some MMX instructions)
1999 Professional 3DNow! A name given by AMD for E3DNow! + SSE
1999 EMMX P6 Extended MMX; an extension to MMX
2001 SSE2 P6 Attempt to replace the original MMX instructions; wider XMM registers offer better performance
2004 SSE3 Core Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register
2006 SSSE3 Core Supplemental Streaming SIMD Extensions 3; additional instructions for working with packed integers
2007 SSE4.1 Penryn Streaming SIMD Extensions 4.1; initial set of instructions for manipulating media data
2007 SSE4a K10 4 SIMD instructions, not related to 4.1/4.2
2007 ABM K10 Advanced Bit Manipulation; bit counting instructions
2008 SSE4.2 Nehalem Streaming SIMD Extensions 4.2; second set of instructions for manipulating media data
2007 SSE5 Proposed by AMD in 2007 but was never implemented
2008 SSE4 Streaming SIMD Extensions 4; Another name for SSE4.1 + SSE4.2
2010 CLMUL Westmere Carry-less multiplication of two registers
2011 AVX Sandy Bridge Advanced Vector Extensions; introduces 256-bits integer operations
2012 F16C Ivy Bridge Extension for performing half-precision <-> single-precision conversions
2011 XOP Bulldozer eXtended Operations; various vector operations
2011 FMA4 Bulldozer 4-operands fused multiply-add
2011 LWP Bulldozer Lightweight Profiling
2011 SMX Nehalem Safer Mode Extensions; instructions needed to facilitate trust decisions (Part of Intel's Trusted Execution Technology)
2011 AES Westmere Instructions for optimizing AES operations
2012 TBM Piledriver Trailing Bit Manipulation; bit manipulation instructions designed to be compiler intrinsics
2013 BMI1 Jaguar Bit Manipulation Instruction Set 1; introduces a number of bit manipulation instructions
2013 BMI2 Haswell Bit Manipulation Instruction Set 2; introduces additional bit manipulation instructions
2013 FMA3 Haswell 3-operands fused multiply-add
2013 TSX Haswell Transactional Synchronization Extensions; adds transactional memory support
2013 AVX2 Haswell Advanced Vector Extensions; additional instructions
2014 ADX Broadwell Multi-Precision Add-Carry Instruction extension
2014 RdRand Broadwell Part of Secure Key Technology extension (RdRand, RDSEED)
2014 PREFETCH Broadwell PREFETCH instructions (previously part of 3DNow!)
2015 AVX-512 Airmont 512 bit register operations
2015 MPX Skylake Memory Protection Extensions
2015 SGX Skylake Software Guard Extensions
2016 SHA Goldmont SHA Extensions
2017 SME Zen Secure Memory Extensions
2019 TME Ice Lake Total Memory Encryption

Experimental Extensions[edit]

Extension First µarch Description
2008 L1OM Larrabee 512-bit vector extension
2010 K1OM Knights Corner 512-bit vector extension

Backwards compatibility[edit]

Generally speaking, all extensions are supported from their introductory date to present day. Extensions introduced by AMD's K6-2 (i.e., 3DNow! & E3DNow!) and those introduced by AMD's Bulldozer (i.e., FMA4, XOP, LWP, and later TBM) have been obsoleted. Note that Zen, at least for first stepping, still offered FMA4 support even though it's not indicated by CPUID.

See also[edit]

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