From WikiChip
Difference between revisions of "amd/microarchitectures/zen 5"
Line 4: | Line 4: | ||
|name=Zen 5 | |name=Zen 5 | ||
|designer=AMD | |designer=AMD | ||
− | |manufacturer=TSMC | + | |manufacturer=TSMC |
− | |process= | + | |process=N4X |
|cores=256 | |cores=256 | ||
|cores 2=224 | |cores 2=224 |
Latest revision as of 11:17, 5 September 2024
Edit Values | |
Zen 5 µarch | |
General Info | |
Arch Type | CPU |
Designer | AMD |
Manufacturer | TSMC |
Process | N4X |
Core Configs | 256, 224, 192, 144, 128, 96, 72, 64, 56, 48, 32, 28, 36, 24, 18, 12 |
PE Configs | 512, 448, 384, 288, 256, 192, 144, 128, 112, 96, 64, 56, 60, 40, 30, 20 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | x86-64, AVX512, AMX (Advanced Matrix Extensions) |
Cores | |
Core Names | Turin (EPYC server multiprocessor), Da Vinci (Threadripper Workstation), Granite Ridge (Gaming Desktop CPU), Strix Point (Gaming APU with RDNA3 or RDNA4) |
Succession | |
Zen 5 is a planned microarchitecture being developed by AMD as a successor to Zen 4.
Contents
History[edit]
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018[1].
Codenames[edit]
Product Codenames:
Core | C/T | Target |
---|---|---|
Turin | Up to ?/? | High-end server multiprocessors |
Da Vinci | Up to ?/? | Workstation & enthusiasts market processors |
Granite Ridge | Up to ?/? | Mainstream to high-end desktops & enthusiasts market processors |
Strix Point | Up to ?/? | Mainstream desktop & mobile processors with GPU |
Architectural Codenames:
Arch | Codename |
---|---|
Core | Nirvana |
CCD | Eldora |
Process Technology[edit]
Zen 5 is speculated to be produced on a 3nm process.
Architecture[edit]
Little is currently known about the architectural improvements that are being done to Zen 5.
-big.LITTLE design -More IPC and clock speed - possibly more L3 cache per chiplet
Key changes from Zen 4[edit]
![]() |
This section is empty; you can help add the missing info by editing this page. |
Designers[edit]
- David Suggs, chief architect
Bibliography[edit]
See Also[edit]
- AMD Zen
- Intel Meteor Lake
Facts about "Zen 5 - Microarchitectures - AMD"
codename | Zen 5 + |
core count | 256 +, 224 +, 192 +, 144 +, 128 +, 96 +, 72 +, 64 +, 56 +, 48 +, 32 +, 28 +, 36 +, 24 +, 18 + and 12 + |
designer | AMD + |
full page name | amd/microarchitectures/zen 5 + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + and AVX512, AMX (Advanced Matrix Extensions) + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Zen 5 + |
processing element count | 512 +, 448 +, 384 +, 288 +, 256 +, 192 +, 144 +, 128 +, 112 +, 96 +, 64 +, 56 +, 60 +, 40 +, 30 + and 20 + |