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Difference between revisions of "amd/microarchitectures/zen 2"
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|name=Zen 2
 
|name=Zen 2
 
|designer=AMD
 
|designer=AMD
|manufacturer=TSMC
+
|manufacturer=GlobalFoundries
 +
|manufacturer 2=TSMC
 
|introduction=2019
 
|introduction=2019
|process=7 nm
+
|process=14 nm
 +
|process 2=7 nm
 +
|process 3=12 nm
 +
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages=19
 +
|decode=4-way
 +
|isa=x86-64
 +
|extension=MOVBE
 +
|extension 2=MMX
 +
|extension 3=SSE
 +
|extension 4=SSE2
 +
|extension 5=SSE3
 +
|extension 6=SSSE3
 +
|extension 7=SSE4.1
 +
|extension 8=SSE4.2
 +
|extension 9=POPCNT
 +
|extension 10=AVX
 +
|extension 11=AVX2
 +
|extension 12=AES
 +
|extension 13=PCLMUL
 +
|extension 14=RDRND
 +
|extension 15=F16C
 +
|extension 16=BMI
 +
|extension 17=BMI2
 +
|extension 18=RDSEED
 +
|extension 19=ADCX
 +
|extension 20=PREFETCHW
 +
|extension 21=CLFLUSHOPT
 +
|extension 22=XSAVE
 +
|extension 23=SHA
 +
|extension 24=CLZERO
 +
|core name=Rome
 
|predecessor=Zen+
 
|predecessor=Zen+
 
|predecessor link=amd/microarchitectures/zen+
 
|predecessor link=amd/microarchitectures/zen+
 
|successor=Zen 3
 
|successor=Zen 3
 
|successor link=amd/microarchitectures/zen 3
 
|successor link=amd/microarchitectures/zen 3
|succession=Yes
 
 
}}
 
}}
'''Zen 2''' is a planned [[microarchitecture]] being developed by [[AMD]] as a successor to {{\\|Zen+}}. Zen 2 is expected to be succeeded by {{\\|Zen 3}}.
+
'''Zen 2''' is [[AMD]]'s successor to {{\\|Zen+}}, a [[7 nm process]] [[microarchitecture]] for mainstream mobile, desktops, workstations, and servers. Zen 2 will eventually be replaced by {{\\|Zen 3}}.
 +
 
 +
For performance desktop and mobile computing, Zen is branded as {{amd|Ryzen 3}}, {{amd|Ryzen 5}}, {{amd|Ryzen 7}} and {{amd|Ryzen Threadripper}} processors. For servers, Zen is branded as {{amd|EPYC}}.
  
 
== History ==
 
== History ==
[[File:amd zen future roadmap.jpg|400px|right]]
+
[[File:amd zen 2 logo.png|right|thumb|Zen 2]]
Zen 2 is set to succeed {{\\|Zen}} in the future, sometimes around 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later {{\\|Zen 3}}. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize [[7 nm process]].
+
Zen 2 is set to succeed {{\\|Zen}} in 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later {{\\|Zen 3}}. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize [[7 nm process]]. Initial details of Zen 2 and {{amd|Rome|l=core}} were unveiled during AMD's Next Horizon event on November 6 2018.
  
 
== Codenames ==
 
== Codenames ==
[[File:amd zen2-3 roadmap.png|400px|right]]
+
[[File:amd zen2-3 roadmap.png|thumb|right|Zen 2 on the roadmap]]
{{future information}}
 
  
 
{| class="wikitable"
 
{| class="wikitable"
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| {{amd|Rome|l=core}} || Up to 64/128 || High-end server [[multiprocessors]]
 
| {{amd|Rome|l=core}} || Up to 64/128 || High-end server [[multiprocessors]]
 
|-
 
|-
| {{amd|Castle Peak|l=core}} || ?/? || workstation & enthusiasts market processors
+
| {{amd|Castle Peak|l=core}} || Up to 64/128? || workstation & enthusiasts market processors
 +
|-
 +
| {{amd|Matisse|l=core}} || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
 +
|-
 +
| {{amd|Renoir|l=core}} || Up to 4/8? || Mainstream APUs with {{\\|Navi}} GPUs
 +
|-
 +
| {{amd|River Hawk|l=core}} || Up to 2/4? || Low-power/Cost-sensitive embedded processors with Navi GPU
 +
|}
 +
 
 +
== Brands ==
 +
[[File:amd ryzen black bg logo.png|thumb|right|Ryzen brand logo]]
 +
 
 +
{| class="wikitable" style="text-align: center;"
 +
|-
 +
! colspan="11" | AMD Zen-based processor brands
 +
|-
 +
! rowspan="2" | Logo || rowspan="2" | Family !! rowspan="2" | General Description !! colspan="8" | Differentiating Features
 +
|-
 +
! Cores !! Unlocked !! {{x86|AVX2}} !! [[SMT]]  !! [[IGP]] !! [[ECC]] !! [[Multiprocessing|MP]]
 +
|-
 +
! colspan="11" | Mainstream
 +
|-
 +
| [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || colspan="8" | ?
 +
|-
 +
| [[File:amd ryzen 5 logo.png|75px|link=Ryzen 5]] || {{amd|Ryzen 5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}}
 +
|-
 +
| [[File:amd ryzen 7 logo.png|75px|link=Ryzen 7]] || {{amd|Ryzen 7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}}
 +
|-
 +
| || {{amd|Ryzen 9}} || High-end Performance || [[12 cores|12]]-[[16 cores|16]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}}
 +
|-
 +
! colspan="10" | Enthusiasts / Workstations
 +
|-
 +
| [[File:ryzen threadripper logo.png|75px|link=Ryzen Threadripper]] || {{amd|Ryzen Threadripper}} || Enthusiasts  || colspan="8" | ?
 +
|-
 +
! colspan="10" | Servers
 +
|-
 +
| [[File:amd epyc logo.png|75px|link=amd/epyc]] || {{amd|EPYC}} || High-performance Server Processor || [[8 cores|8]]-[[64 cores|64]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}}
 
|-
 
|-
| {{amd|Matisse|l=core}} || ?/? || Mainstream to high-end desktops & enthusiasts market processors
+
! colspan="10" | Embedded / Edge
 
|-
 
|-
| {{amd|Picasso|l=core}} || ?/? || Mainstream desktop & mobile processors with GPU
+
| [[File:epyc embedded logo.png|75px|link=amd/epyc embedded]] || {{amd|EPYC Embedded}} || Embedded / Edge Server Processor  || colspan="8" | ?
 +
|-
 +
| [[File:ryzen embedded logo.png|75px|link=amd/ryzen embedded]] || {{amd|Ryzen Embedded}} || Embedded APUs  || colspan="8" | ?
 
|}
 
|}
  
 
== Process technology ==
 
== Process technology ==
Zen 2 is fabricated on [[TSMC]]'s [[7 nm process]].
+
Zen 2 comprises multiple different components:
 +
 
 +
* The Core Chiplet Die (CCD) is fabricated on [[TSMC]] [[7 nm process|7 nm HPC process]]
 +
* The client I/O Die (cIOD) is fabricated on [[GlobalFoundries]] [[12 nm process]]
 +
* The server I/O Die (sIOD) is fabricated on [[GlobalFoundries]] [[14 nm process]]
  
 
== Compiler support ==
 
== Compiler support ==
Line 45: Line 122:
 
|-
 
|-
 
| [[GCC]] || <code>-march=znver2</code> || <code>-mtune=znver2</code>
 
| [[GCC]] || <code>-march=znver2</code> || <code>-mtune=znver2</code>
 +
|-
 +
| [[LLVM]] || <code>-march=znver2</code> || <code>-mtune=znver2</code>
 
|}
 
|}
* '''Note:''' Initial support in GCC 9.
+
* '''Note:''' Initial support in GCC 9 and LLVM 9.
  
 
== Architecture ==
 
== Architecture ==
Zen 2 inherits most of the design from {{\\|Zen++}} but improves the instruction stream bandwidth and floating-point throughput performance.
+
Zen 2 inherits most of the design from {{\\|Zen+}} but improves the instruction stream bandwidth and floating-point throughput performance.
 +
 
 +
 
 +
{{work-in-progress}}
 +
 
  
 
=== Key changes from {{\\|Zen+}} ===
 
=== Key changes from {{\\|Zen+}} ===
* [[7 nm process]] (from [[12 nm]])
+
* [[7 nm process]] (from [[14 nm]])
** I/O die still utilizes [[14 nm]]
+
** I/O die utilizes [[14 nm]]
 
* Core
 
* Core
 +
** Higher [[IPC]] (AMD self-reported up to 15% IPC)
 
** Front-end
 
** Front-end
 
*** Improved [[branch prediction unit]]
 
*** Improved [[branch prediction unit]]
Line 60: Line 144:
 
*** Improved µOP cache tags
 
*** Improved µOP cache tags
 
*** Improved µOP cache
 
*** Improved µOP cache
**** Larger µOP cache (?? enters, up from 2048)
+
**** Larger µOP cache (4096 entries, up from 2048)
 
*** Increased dispatch bandwidth
 
*** Increased dispatch bandwidth
 
** Back-end
 
** Back-end
Line 68: Line 152:
 
**** 2x wider EUs (256-bit FMAs, up from 128-bit FMAs)
 
**** 2x wider EUs (256-bit FMAs, up from 128-bit FMAs)
 
**** 2x wider LSU (2x256-bit L/S, up from 128-bit)
 
**** 2x wider LSU (2x256-bit L/S, up from 128-bit)
 +
**** Improved mul latency (3 cycles, down from 4)
 +
*** Integer
 +
**** Increased number of registers (180, up from 168)
 +
**** Additional AGU (3, up from 2)
 +
**** Larger scheduler (4x16 ALU + 1x28 AGU, up from 4x14 ALU + 2x14 AGU
 +
**** Larger Reorder Buffer (224, up from 192)
 +
** Memory subsystem
 +
*** 0.5x L1 instruction cache (32 KiB, down from 64 KiB)
 +
*** 8-way associativity (from 4-way)
 +
*** 1.33 larger L2 DTLB (2048-entry, up from 1536)
 +
*** 48 entry store queue (was 44)
 +
* {{amd|CCX}}
 +
** 2x L3 cache slice (16 MiB, up from 8 MiB)
 +
** Increased L3 latency (~40 cycles, up from ~35 cycles)
 
* Security
 
* Security
 
** In-silicon Spectre enhancements
 
** In-silicon Spectre enhancements
Line 75: Line 173:
 
** {{amd|Infinity Fabric}} 2
 
** {{amd|Infinity Fabric}} 2
 
*** 2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s)
 
*** 2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s)
 +
** Decoupling of MemClk from FClk, allowing 2:1 ratio in addition to 1:1
 +
** DDR4-3200 support, up from DDR4-2933
  
 
{{expand list}}
 
{{expand list}}
Line 81: Line 181:
 
Zen 2 introduced a number of new [[x86]] instructions:
 
Zen 2 introduced a number of new [[x86]] instructions:
  
* <code>{{x86|CLWB}}</code> - Force cache line write-back without flush
+
* <code>{{x86|CLWB}}</code> - Write back modified cache line and may retain line in cache hierarchy
 +
* <code>{{x86|WBNOINVD}}</code> - Write back and do not flush internal caches, initiate same of external caches
 
* <code>{{x86|RDPID}}</code> - Read Processor ID
 
* <code>{{x86|RDPID}}</code> - Read Processor ID
* <code>{{x86|WBNOINVD}}</code> - Force cache line write-back without invalidation
 
  
 
=== Block Diagram ===
 
=== Block Diagram ===
Line 94: Line 194:
 
== Core ==
 
== Core ==
 
Zen 2 largely builds on {{\\|Zen}}. Most of the fine details have not been revealed by AMD yet.
 
Zen 2 largely builds on {{\\|Zen}}. Most of the fine details have not been revealed by AMD yet.
 +
 +
 +
{{work-in-progress}}
 +
 +
  
 
=== Front End ===
 
=== Front End ===
Line 105: Line 210:
  
 
With two 256-bit [[fused multiply-add unit|FMAs]], Zen 2 is capable of 16 [[FLOPs]]/cycle.
 
With two 256-bit [[fused multiply-add unit|FMAs]], Zen 2 is capable of 16 [[FLOPs]]/cycle.
 +
 +
== Rome ==
 +
{{amd|Rome|l=core}} is codename for AMD's server chip based on the Zen 2 core. Like prior generation ({{amd|Naples|l=core}}), Rome utilizes a [[chiplet]] multi-chip package design. Each chip comprises of nine [[dies]] - one centralized I/O die and eight compute dies. The compute dies are fabricated on [[TSMC]]'s [[7 nm process]] in order to take advantage of the lower power and [[transistor density|higher density]]. On the other hand, the I/O makes use of [[GlobalFoundries]] mature [[14 nm process]].
 +
 +
The centralized I/O die incorporates eight {{amd|Infinity Fabric}} links, 128 [[PCIe]] Gen 4 lanes, and eight [[DDR4]] memory channels. The full capabilities of the I/O have not been disclosed yet. Attached to the I/O die are eight compute dies - each with eight Zen 2 core - for a total of 64 cores and 128 threads per chip.
 +
 +
== All Zen 2 Chips ==
 +
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 +
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19">
 +
{{comp table header|main|20:List of all Zen-based Processors}}
 +
{{comp table header|main|12:Processor|4:Features}}
 +
{{comp table header|cols|Price|Process|Launched|Family|Core|C|T|TDP|L3|Base|Turbo|Max Mem|SMT|SEV|SME|TSME}}
 +
{{comp table header|lsep|25:[[Uniprocessors]]}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 2]] [[max cpu count::1]]
 +
|?full page name
 +
|?model number
 +
|?release price
 +
|?process
 +
|?first launched
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|?max memory#GiB
 +
|?has simultaneous multithreading
 +
|?has amd secure encrypted virtualization technology
 +
|?has amd secure memory encryption technology
 +
|?has amd transparent secure memory encryption technology
 +
|format=template
 +
|template=proc table 3
 +
|userparam=18:15
 +
|mainlabel=-
 +
|valuesep=,
 +
|limit=100
 +
}}
 +
{{comp table header|lsep|25:[[Multiprocessors]] (dual-socket)}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 2]] [[max cpu count::>>1]]
 +
|?full page name
 +
|?model number
 +
|?release price
 +
|?process
 +
|?first launched
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|?max memory#GiB
 +
|?has simultaneous multithreading
 +
|?has amd secure encrypted virtualization technology
 +
|?has amd secure memory encryption technology
 +
|?has amd transparent secure memory encryption technology
 +
|format=template
 +
|template=proc table 3
 +
|userparam=18:15
 +
|mainlabel=-
 +
|valuesep=,
 +
|limit=100
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 2]]}}
 +
</table>
 +
{{comp table end}}
  
 
== Bibliography ==
 
== Bibliography ==
Line 111: Line 293:
 
* AMD GCC 9 znver2 enablement [https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01982.html patch]
 
* AMD GCC 9 znver2 enablement [https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01982.html patch]
 
* AMD 'Next Horizon', November 6, 2018
 
* AMD 'Next Horizon', November 6, 2018
 +
* AMD. Lisa Su ''Keynote''. May 26, 2019
 +
* AMD 'Next Horizon Gaming' event at E3, June 10, 2019
  
 
== See Also ==
 
== See Also ==
 
* Intel {{intel|Ice Lake|l=arch}}
 
* Intel {{intel|Ice Lake|l=arch}}

Revision as of 02:18, 21 August 2019

Edit Values
Zen 2 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerGlobalFoundries, TSMC
Introduction2019
Process14 nm, 7 nm, 12 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages19
Decode4-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, RDRND, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SHA, CLZERO
Cores
Core NamesRome
Succession

Zen 2 is AMD's successor to Zen+, a 7 nm process microarchitecture for mainstream mobile, desktops, workstations, and servers. Zen 2 will eventually be replaced by Zen 3.

For performance desktop and mobile computing, Zen is branded as Ryzen 3, Ryzen 5, Ryzen 7 and Ryzen Threadripper processors. For servers, Zen is branded as EPYC.

History

Zen 2

Zen 2 is set to succeed Zen in 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later Zen 3. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize 7 nm process. Initial details of Zen 2 and Rome were unveiled during AMD's Next Horizon event on November 6 2018.

Codenames

Zen 2 on the roadmap
Core C/T Target
Rome Up to 64/128 High-end server multiprocessors
Castle Peak Up to 64/128? workstation & enthusiasts market processors
Matisse Up to 16/32 Mainstream to high-end desktops & enthusiasts market processors
Renoir Up to 4/8? Mainstream APUs with Navi GPUs
River Hawk Up to 2/4? Low-power/Cost-sensitive embedded processors with Navi GPU

Brands

Ryzen brand logo
AMD Zen-based processor brands
Logo Family General Description Differentiating Features
Cores Unlocked AVX2 SMT IGP ECC MP
Mainstream
amd ryzen 3 logo.png Ryzen 3 Entry level Performance  ?
amd ryzen 5 logo.png Ryzen 5 Mid-range Performance Hexa
amd ryzen 7 logo.png Ryzen 7 High-end Performance Octa
Ryzen 9 High-end Performance 12-16
Enthusiasts / Workstations
ryzen threadripper logo.png Ryzen Threadripper Enthusiasts  ?
Servers
amd epyc logo.png EPYC High-performance Server Processor 8-64
Embedded / Edge
epyc embedded logo.png EPYC Embedded Embedded / Edge Server Processor  ?
ryzen embedded logo.png Ryzen Embedded Embedded APUs  ?

Process technology

Zen 2 comprises multiple different components:

Compiler support

Compiler Arch-Specific Arch-Favorable
GCC -march=znver2 -mtune=znver2
LLVM -march=znver2 -mtune=znver2
  • Note: Initial support in GCC 9 and LLVM 9.

Architecture

Zen 2 inherits most of the design from Zen+ but improves the instruction stream bandwidth and floating-point throughput performance.


Under construction icon-blue.svg This article is a work in progress!


Key changes from Zen+

  • 7 nm process (from 14 nm)
  • Core
    • Higher IPC (AMD self-reported up to 15% IPC)
    • Front-end
      • Improved branch prediction unit
        • Improved prefetcher
      • Improved µOP cache tags
      • Improved µOP cache
        • Larger µOP cache (4096 entries, up from 2048)
      • Increased dispatch bandwidth
    • Back-end
      • Increased retire bandwidth (??-wide, up from 8-wide)
      • FPU
        • 2x wider datapath (256-bit, up from 128-bit)
        • 2x wider EUs (256-bit FMAs, up from 128-bit FMAs)
        • 2x wider LSU (2x256-bit L/S, up from 128-bit)
        • Improved mul latency (3 cycles, down from 4)
      • Integer
        • Increased number of registers (180, up from 168)
        • Additional AGU (3, up from 2)
        • Larger scheduler (4x16 ALU + 1x28 AGU, up from 4x14 ALU + 2x14 AGU
        • Larger Reorder Buffer (224, up from 192)
    • Memory subsystem
      • 0.5x L1 instruction cache (32 KiB, down from 64 KiB)
      • 8-way associativity (from 4-way)
      • 1.33 larger L2 DTLB (2048-entry, up from 1536)
      • 48 entry store queue (was 44)
  • CCX
    • 2x L3 cache slice (16 MiB, up from 8 MiB)
    • Increased L3 latency (~40 cycles, up from ~35 cycles)
  • Security
    • In-silicon Spectre enhancements
    • Increase number of keys/VMs supported
  • I/O
    • PCIe 4.0 (from 3.0)
    • Infinity Fabric 2
      • 2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s)
    • Decoupling of MemClk from FClk, allowing 2:1 ratio in addition to 1:1
    • DDR4-3200 support, up from DDR4-2933

This list is incomplete; you can help by expanding it.

New instructions

Zen 2 introduced a number of new x86 instructions:

  • CLWB - Write back modified cache line and may retain line in cache hierarchy
  • WBNOINVD - Write back and do not flush internal caches, initiate same of external caches
  • RDPID - Read Processor ID

Block Diagram

Individual Core

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

New text document.svg This section is empty; you can help add the missing info by editing this page.

Core

Zen 2 largely builds on Zen. Most of the fine details have not been revealed by AMD yet.


Under construction icon-blue.svg This article is a work in progress!


Front End

In order to feed the backend, which has been widened to support 256-bit operation, the front-end throughput was improved. AMD reported that the branch prediction unit has been reworked. This includes improvements to the prefetcher and various undisclosed optimizations to the instruction cache. The µOP cache was also tweaked including changes to the µOP cache tags and the µOP cache itself which has been enlarged to improve the instruction stream throughput.

Execution Engine

AMD stated that both the dispatch bandwidth and the retire bandwidth has been increased.

Floating Point

The floating-point unit underwent major modifications in Zen 2. In Zen, AVX2 256 bit single and double precision vector floating-point data types were supported through the use of two 128 bit micro-ops per instruction. Likewise, the floating-point load and store operations were 128 bits wide. In Zen 2, the datapath and the execution units were widened to 256 bits, doubling the vector throughput of the core.

With two 256-bit FMAs, Zen 2 is capable of 16 FLOPs/cycle.

Rome

Rome is codename for AMD's server chip based on the Zen 2 core. Like prior generation (Naples), Rome utilizes a chiplet multi-chip package design. Each chip comprises of nine dies - one centralized I/O die and eight compute dies. The compute dies are fabricated on TSMC's 7 nm process in order to take advantage of the lower power and higher density. On the other hand, the I/O makes use of GlobalFoundries mature 14 nm process.

The centralized I/O die incorporates eight Infinity Fabric links, 128 PCIe Gen 4 lanes, and eight DDR4 memory channels. The full capabilities of the I/O have not been disclosed yet. Attached to the I/O die are eight compute dies - each with eight Zen 2 core - for a total of 64 cores and 128 threads per chip.

All Zen 2 Chips

 List of all Zen-based Processors
 ProcessorFeatures
ModelPriceProcessLaunchedFamilyCoreCTTDPL3BaseTurboMax MemSMTSEVSMETSME
 Uniprocessors
7232P$ 450.00
€ 405.00
£ 364.50
¥ 46,498.50
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome816120 W
120,000 mW
0.161 hp
0.12 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.1 GHz
3,100 MHz
3,100,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7302P$ 825.00
€ 742.50
£ 668.25
¥ 85,247.25
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome1632155 W
155,000 mW
0.208 hp
0.155 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3 GHz
3,000 MHz
3,000,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7402P$ 1,250.00
€ 1,125.00
£ 1,012.50
¥ 129,162.50
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome2448180 W
180,000 mW
0.241 hp
0.18 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.8 GHz
2,800 MHz
2,800,000 kHz
3.35 GHz
3,350 MHz
3,350,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7502P$ 2,300.00
€ 2,070.00
£ 1,863.00
¥ 237,659.00
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome3264180 W
180,000 mW
0.241 hp
0.18 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.5 GHz
2,500 MHz
2,500,000 kHz
3.35 GHz
3,350 MHz
3,350,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7702P$ 4,425.00
€ 3,982.50
£ 3,584.25
¥ 457,235.25
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome64128200 W
200,000 mW
0.268 hp
0.2 kW
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2 GHz
2,000 MHz
2,000,000 kHz
3.35 GHz
3,350 MHz
3,350,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
3500X7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
Ryzen 5Matisse6665 W
65,000 mW
0.0872 hp
0.065 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
4.1 GHz
4,100 MHz
4,100,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
3600$ 199.00
€ 179.10
£ 161.19
¥ 20,562.67
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
7 July 2019Ryzen 5Matisse61265 W
65,000 mW
0.0872 hp
0.065 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
3600X$ 249.00
€ 224.10
£ 201.69
¥ 25,729.17
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
7 July 2019Ryzen 5Matisse61295 W
95,000 mW
0.127 hp
0.095 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
4.4 GHz
4,400 MHz
4,400,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
PRO 36007 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
30 September 2019Ryzen 5Matisse61265 W
65,000 mW
0.0872 hp
0.065 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
3700X$ 329.00
€ 296.10
£ 266.49
¥ 33,995.57
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
7 July 2019Ryzen 7Matisse81665 W
65,000 mW
0.0872 hp
0.065 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
4.4 GHz
4,400 MHz
4,400,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
3800X$ 399.00
€ 359.10
£ 323.19
¥ 41,228.67
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
7 July 2019Ryzen 7Matisse816105 W
105,000 mW
0.141 hp
0.105 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.9 GHz
3,900 MHz
3,900,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
PRO 37007 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
30 September 2019Ryzen 7Matisse81665 W
65,000 mW
0.0872 hp
0.065 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
4.4 GHz
4,400 MHz
4,400,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
3900X$ 499.00
€ 449.10
£ 404.19
¥ 51,561.67
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
7 July 2019Ryzen 9Matisse1224105 W
105,000 mW
0.141 hp
0.105 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
4.6 GHz
4,600 MHz
4,600,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
3950X$ 749.00
€ 674.10
£ 606.69
¥ 77,394.17
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
November 2019Ryzen 9Matisse1632105 W
105,000 mW
0.141 hp
0.105 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.5 GHz
3,500 MHz
3,500,000 kHz
4.7 GHz
4,700 MHz
4,700,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
PRO 39007 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
30 September 2019Ryzen 9Matisse122465 W
65,000 mW
0.0872 hp
0.065 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.1 GHz
3,100 MHz
3,100,000 kHz
4.3 GHz
4,300 MHz
4,300,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
 Multiprocessors (dual-socket)
7252$ 475.00
€ 427.50
£ 384.75
¥ 49,081.75
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome816120 W
120,000 mW
0.161 hp
0.12 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
2.8 GHz
2,800 MHz
2,800,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7262$ 575.00
€ 517.50
£ 465.75
¥ 59,414.75
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome816155 W
155,000 mW
0.208 hp
0.155 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3.1 GHz
3,100 MHz
3,100,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7272$ 625.00
€ 562.50
£ 506.25
¥ 64,581.25
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome1224120 W
120,000 mW
0.161 hp
0.12 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
2.6 GHz
2,600 MHz
2,600,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7282$ 650.00
€ 585.00
£ 526.50
¥ 67,164.50
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome1632120 W
120,000 mW
0.161 hp
0.12 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
2.8 GHz
2,800 MHz
2,800,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7302$ 978.00
€ 880.20
£ 792.18
¥ 101,056.74
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome1632155 W
155,000 mW
0.208 hp
0.155 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3 GHz
3,000 MHz
3,000,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7352$ 1,350.00
€ 1,215.00
£ 1,093.50
¥ 139,495.50
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome2448155 W
155,000 mW
0.208 hp
0.155 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.4 GHz
2,400 MHz
2,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7402$ 1,783.00
€ 1,604.70
£ 1,444.23
¥ 184,237.39
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome2448180 W
180,000 mW
0.241 hp
0.18 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.8 GHz
2,800 MHz
2,800,000 kHz
3.35 GHz
3,350 MHz
3,350,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7452$ 2,025.00
€ 1,822.50
£ 1,640.25
¥ 209,243.25
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome3264155 W
155,000 mW
0.208 hp
0.155 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.2 GHz
2,200 MHz
2,200,000 kHz
3.35 GHz
3,350 MHz
3,350,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7502$ 2,600.00
€ 2,340.00
£ 2,106.00
¥ 268,658.00
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome3264180 W
180,000 mW
0.241 hp
0.18 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.5 GHz
2,500 MHz
2,500,000 kHz
3.35 GHz
3,350 MHz
3,350,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7542$ 3,400.00
€ 3,060.00
£ 2,754.00
¥ 351,322.00
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome3264225 W
225,000 mW
0.302 hp
0.225 kW
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.9 GHz
2,900 MHz
2,900,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7552$ 4,025.00
€ 3,622.50
£ 3,260.25
¥ 415,903.25
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome4896200 W
200,000 mW
0.268 hp
0.2 kW
192 MiB
196,608 KiB
201,326,592 B
0.188 GiB
2.2 GHz
2,200 MHz
2,200,000 kHz
3.35 GHz
3,350 MHz
3,350,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7642$ 4,775.00
€ 4,297.50
£ 3,867.75
¥ 493,400.75
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome4896225 W
225,000 mW
0.302 hp
0.225 kW
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.4 GHz
2,400 MHz
2,400,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7702$ 6,450.00
€ 5,805.00
£ 5,224.50
¥ 666,478.50
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome64128200 W
200,000 mW
0.268 hp
0.2 kW
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2 GHz
2,000 MHz
2,000,000 kHz
3.35 GHz
3,350 MHz
3,350,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7742$ 6,950.00
€ 6,255.00
£ 5,629.50
¥ 718,143.50
7 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
7 August 2019EPYCRome64128225 W
225,000 mW
0.302 hp
0.225 kW
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.25 GHz
2,250 MHz
2,250,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
7H127 nm
0.007 μm
7.0e-6 mm
, 14 nm
0.014 μm
1.4e-5 mm
18 September 2019EPYCRome64128280 W
280,000 mW
0.375 hp
0.28 kW
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.6 GHz
2,600 MHz
2,600,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
4,096 GiB
4,194,304 MiB
4,294,967,296 KiB
4,398,046,511,104 B
4 TiB
Count: 30

Bibliography

  • AMD 'Tech Day', February 22, 2017
  • AMD 2017 Financial Analyst Day, May 16, 2017
  • AMD GCC 9 znver2 enablement patch
  • AMD 'Next Horizon', November 6, 2018
  • AMD. Lisa Su Keynote. May 26, 2019
  • AMD 'Next Horizon Gaming' event at E3, June 10, 2019

See Also

codenameZen 2 +
designerAMD +
first launched2019 +
full page nameamd/microarchitectures/zen 2 +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerGlobalFoundries + and TSMC +
microarchitecture typeCPU +
nameZen 2 +
pipeline stages19 +
process14 nm (0.014 μm, 1.4e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +