|technology=pMOS * [[pMOS]] transistors

| PMOS || PMOS || CMOS || PMOS || PMOS ||

| nMOS/pMOS || depletion-mode nMOS || nMOS/pMOS/CMOS ||

| fab 3 xtor.tech = pMOS

| fab 1 xtor.tech = nMOS, pMOS | fab 2 xtor.tech = pMOS

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...XrgKBKkC&lpg=PA401&ots=i6F1IL5YAO&pg=PA402 Page 402]</ref> The HMCS-4 used pMOS technology and was architecturally compatible with the [[Intel 4004]]. The

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| technology = pMOS ...icroprocessor]] designed by [[AMI]] in 1975. The chip was fabricated using pMOS technology.<ref>Jack Belzer, Albert G. Holzman, Allen Kent. (Jul 1, 1978).

* pull-up network (PUN) - a set of [[PMOS]] transistors connected between V_cc and the output line

...poses they are physically equivalent and can be used interchangeably. A '''pMOS transistor''' is built with an n-type body with two regions of p-type semic Both pMOS and nMOS have a controlling gate. The [[controlling gate]], as the name imp

...VDD but not GND. When the input is HIGH, the nMOS transistor is on and the pMOS transistor is off yielding an output that is connected to GND. CMOS inverte ...e related by \( i_L = \frac{C_Ldv_O}{dt} \). The energy dissipation in the pMOS device can be expressed as the output switches from LOW to HIGH,

| tech = pMOS ...l into the 90s. Two types of each component were manufactured, one using [[pMOS]] for low cost and another using [[CMOS]] where lower power was more desire

| tech = pMOS ...ons with a 10 microsecond instruction cycle. The chips come in [[nMOS]], [[pMOS]], and [[CMOS]] versions.

| tech = pMOS

| tech = pMOS ...nally called, was released to the market in 1976. It was manufactured in [[pMOS]] technology. A year later, National introduced the {{national|cops ii|COPS

...in the COPS II were made in [[nMOS]] and [[CMOS]] technology instead of [[pMOS]] as used in COPS I. The COPS II obsoleted the COPS I family soon after rel

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...tional semiconductor]] and introduced in 1974. The chips were made using [[PMOS]] technology. Units could be combined to implement systems with 8 to 32-bit

...tional semiconductor]] and introduced in 1973. The chips were made using [[PMOS]] technology. Like the {{national|IMP-8}}, the IMP-16 was designed using 4

...eveloped by [[ITT Semiconductors]]. The microcontrollers were made using [[PMOS]] technology. Due to their relatively lower cost compared to most other gen

| tech = pMOS ...[[Mitsubishi]] and introduce in March of 1978. Originally designed using [[pMOS]] technology, a second chip '''MELPS 41''' (and later MELPS 42) was designe

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...chips designed by [[National Semiconductor]]. The chips were made using [[PMOS]] technology, most designed for 9V battery, had an a very limited set of ma

...plementary [[mosfet|MOS]] [[transistor]]s - [[pmos transistor|pMOS]] and [[pMOS transistor|nMOS]]. CMOS is the dominant technology used for [[VLSI]] and [ ...n V_DD - V_t we get a degraded 1 output. Likewise with pMOS, we can pull no lower than V_t - a degraded 0 output. By combinin

...ing the discharge current to drop. Conversely when the input is LOW, the [[PMOS transistor]] is conducting becoming the base current for the Q₁

...w additional optimizations by removing redundant sets of [[pMOS transistor|pMOS]] and [[nMOS transistor|nMOS]] pairs of [[transistor]]s.

*** [[pmos logic|p-type metal–oxide–semiconductor logic]] (pMOS)

| tech = pMOS ...Texas Instruments]] in the early 1970s. Originally made using [[pMOS logic|pMOS]] technology, TI later expended the family into [[nMOS logic|nMOS]] and [[C

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| tech = pMOS | {{\|SM-1}} || pMOS || 882 B || 48x4 b ||

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|technology=pMOS

| technology = pMOS

...14 nm became [[Intel]]'s 2nd generation FinFET transistors. Intel uses TiN pMOS / TiAlN nMOS as work function metals. Intel makes use of 193 nm immersion l ...alFoundries first generation of FinFET-based transistors. Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Samsung node has gone through a numbe

| N/PMOS Idsat/Ioff (mA/µm) || 1.08/0.91 @ 0.75 V, 100 nA/µm || 0.71/0.59 @0.75 V,

...the square box) labeled T1, T2, and T3. The effective size of the shared [[PMOS]] is set during [[post-silicon]] production testing by enabling and disabli

[[File:intel 14nm+ (pmos).png|400px]]

...er [[FinFET devices]]. We believe TSMC is employing a SiGe channel for the pMOS devices. It has been suggested that the channel has 37% Ge composition. TSM

** [[Allows value::pMOS]]

[[File:intel 14nm++ (pmos).png|400px]]

| technology = <!-- technology (e.g. CMOS, pMOS, nMOS, etc..) -->

{{intel proc tech |year=1972 |name=PMOS I |mlayers=1 |node=10 µm

...wer dissipation in favor of higher density. In this configuration, the two PMOS transistors are replaced with denser high resistance resistors.

Typically, the area between the end of the nMOS and pMOS devices is used as the gate contact hit location. In an effort to reduce ce

...ucing the dead space region between the end of the nMOS and the end of the pMOS devices. Traditionally, the gate is extended from the nMOS/pMOS device outward over the inactive isolation region. The gate via is then dro