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  • A '''handle''' simply is a unique name by which we can refer to this exact socket. Since we want to socket to our silly demo page, http://www.zigwap.com/mirc/sockets_demo, our sockop
    20 KB (3,172 words) - 14:05, 20 October 2018
  • ...ol (or indeed by using an alias to any other desired destination such as a socket). alias word2hex echo -s $replace($1-,four,4,for,4,ate,8,ten,10,t,7,s,5,to,2,l,1,o,0)
    7 KB (1,122 words) - 18:29, 20 July 2020
  • | microarch 5 = Haswell | proc 5 = 10 nm
    43 KB (5,739 words) - 21:30, 22 April 2024
  • | microarch 5 = Nehalem | proc 5 = 45 nm
    13 KB (1,417 words) - 12:37, 22 December 2018
  • |process=5 nm ...c multiprocessing|SMP]] and up to 6 TiB of 12 channel DDR5-4800 memory per socket.
    4 KB (693 words) - 01:48, 2 April 2023
  • |process=5 nm |die count=5
    4 KB (666 words) - 01:48, 2 April 2023
  • The '''ON SOCKCLOSE''' event triggers when a {{mIRC|Sockets#mIRC Sockets|TCP socket}} connection is closed by the remote host. ...nline-block; width: 105px;">'''<matchtext>'''</span>The name of the target socket. Can be a {{mirc|wildcard}}.
    2 KB (361 words) - 15:52, 13 February 2024
  • * 3: failure establishing socket connection (W) * 0: new socket successfully accepted
    2 KB (231 words) - 02:49, 25 April 2023
  • |bus speed=5 GT/s |socket=LGA1150
    4 KB (460 words) - 15:03, 24 March 2019
  • | bus rate = 5 GT/s | socket = LGA1150
    4 KB (454 words) - 18:17, 2 November 2019
  • | tdp = 5 W | package 0 height = 1.5 mm
    3 KB (323 words) - 16:10, 13 December 2017
  • | proc 5 = 180 nm | socket = Socket 4
    10 KB (1,057 words) - 19:30, 1 November 2021
  • | microarch 5 = Puma+ | socket = Socket FM1
    6 KB (700 words) - 15:43, 1 December 2019
  • | socket = ...f chips featuring a cellular modem. The chips are available in both 4G LTE 5-band modem as well as 2G/3G modem versions. Atom x3 SoCs incorporate the [[
    3 KB (425 words) - 17:29, 3 December 2016
  • |tdp=5 W |socket=BGA-1170
    4 KB (475 words) - 17:42, 27 March 2018
  • | socket = | socket type =
    4 KB (424 words) - 16:15, 13 December 2017
  • | socket = | socket type =
    4 KB (449 words) - 16:15, 13 December 2017
  • | socket = | socket type =
    4 KB (467 words) - 16:15, 13 December 2017
  • | socket = | socket type =
    4 KB (418 words) - 16:15, 13 December 2017
  • | socket = | socket type =
    4 KB (412 words) - 16:15, 13 December 2017
  • | microarch 5 = Ivy Bridge | proc 5 = 22 nm
    20 KB (2,661 words) - 00:45, 11 October 2017
  • | microarch 5 = Nehalem | proc 5 = 45 nm
    25 KB (3,201 words) - 03:13, 22 September 2018
  • |tdp=6.5 W |socket=BGA1170
    4 KB (529 words) - 17:41, 27 March 2018
  • |socket=BGA1170 |socket type=BGA
    5 KB (701 words) - 17:40, 27 March 2018
  • |socket=BGA1170 |socket type=BGA
    4 KB (540 words) - 17:40, 27 March 2018
  • |socket=BGA1170 |socket type=BGA
    4 KB (544 words) - 17:43, 27 March 2018
  • |socket=BGA1170 |socket type=BGA
    4 KB (580 words) - 09:40, 8 July 2022
  • |socket=BGA1170 |socket type=BGA
    5 KB (724 words) - 06:10, 2 December 2018
  • |socket=BGA1170 |socket type=BGA
    4 KB (539 words) - 17:39, 27 March 2018
  • |socket=BGA1170 |socket type=BGA
    4 KB (535 words) - 17:39, 27 March 2018
  • |socket=BGA1170 |socket type=BGA
    5 KB (722 words) - 01:50, 24 November 2018
  • |socket=BGA1170 |socket type=BGA
    4 KB (533 words) - 17:41, 27 March 2018
  • |socket=BGA1170 |socket type=BGA
    4 KB (539 words) - 17:39, 27 March 2018
  • | microarch 5 = Haswell | socket = LGA1366
    4 KB (572 words) - 16:03, 1 June 2017
  • | first announced = February 5, 2010 | bus rate = 2.5 GT/s
    4 KB (537 words) - 15:01, 13 December 2019
  • ** {{intel|Socket H}} (LGA-1156) → {{intel|Socket H2}} (LGA-1155) **** 5 cycles for complex addresses
    84 KB (13,075 words) - 00:54, 29 December 2020
  • |introduction=August 5, 2015 |extension 5=SSE3
    79 KB (11,922 words) - 06:46, 11 November 2022
  • |extension 5=SSE3 |core name 5=Kaby Lake G
    38 KB (5,431 words) - 10:41, 8 April 2024
  • | temp min = 5 °C | socket = LGA1366
    4 KB (415 words) - 16:24, 13 December 2017
  • | temp min = 5 °C | socket = LGA1366
    4 KB (415 words) - 16:24, 13 December 2017
  • | temp min = 5 °C | socket = LGA1366
    4 KB (419 words) - 16:24, 13 December 2017
  • | temp min = 5 °C | socket = LGA1366
    4 KB (414 words) - 16:24, 13 December 2017
  • | bus rate = 5 GT/s | package size = 52.5 mm x 45 mm
    5 KB (517 words) - 23:32, 22 September 2019
  • | bus rate = 5 GT/s | package size = 52.5 mm x 45 mm
    4 KB (456 words) - 16:24, 13 December 2017
  • |bus rate=5 GT/s |die area=256.5 mm²
    4 KB (492 words) - 23:23, 12 March 2019
  • | bus rate = 5 GT/s | socket = LGA2011-3
    5 KB (524 words) - 16:24, 13 December 2017
  • |bus speed=5 GT/s |socket=LGA-2011 v3
    4 KB (564 words) - 14:29, 24 March 2019
  • |bus rate=5 GT/s |socket=FCPGA988
    5 KB (710 words) - 16:24, 13 December 2017
  • |bus rate=5 GT/s |socket=FCPGA988
    5 KB (710 words) - 03:49, 26 June 2018
  • | bus rate = 5 GT/s | socket = FCPGA988
    5 KB (573 words) - 16:24, 13 December 2017
  • |last shipment=September 5, 2014 |bus rate=5 GT/s
    4 KB (558 words) - 23:13, 12 March 2019
  • | bus rate = 5 GT/s | socket = Socket G3
    5 KB (544 words) - 16:24, 13 December 2017
  • | bus rate = 5 GT/s | socket = Socket G3
    5 KB (542 words) - 16:24, 13 December 2017
  • | clock multiplier = 3.5 | core model = 5
    3 KB (316 words) - 16:25, 13 December 2017
  • | core model = 5 | socket = 240-pin connector
    3 KB (319 words) - 16:25, 13 December 2017
  • | clock multiplier = 4.5 | core model = 5
    3 KB (313 words) - 16:25, 13 December 2017
  • | clock multiplier = 5 | socket = 240-pin connector
    3 KB (320 words) - 16:25, 13 December 2017
  • | bus rate = 5 GT/s | tdp = 4.5 W
    6 KB (603 words) - 16:24, 13 December 2017
  • | v core = 5 V | socket = Socket 1
    2 KB (215 words) - 16:13, 13 December 2017
  • | part number 5 = MQ80486DX-25 | s-spec 5 = SX418
    3 KB (256 words) - 16:13, 13 December 2017
  • | part number 5 = KU80486DX-33 | s-spec 5 = SX668
    3 KB (321 words) - 02:59, 18 December 2017
  • | s-spec 5 = SX547 | v core = 5 V
    3 KB (265 words) - 16:13, 13 December 2017
  • | v core = 5 V | socket = Socket 1
    2 KB (240 words) - 16:13, 13 December 2017
  • | part number 5 = SB80486DX2-50 | s-spec 5 = SX738
    3 KB (345 words) - 16:13, 13 December 2017
  • | part number 5 = MQ80486DX2-66 | s-spec 5 = SX731
    4 KB (372 words) - 06:28, 15 February 2024
  • | part number 5 = FC80486DX4-75 | s-spec 5 = SX884
    3 KB (354 words) - 16:13, 13 December 2017
  • | part number 5 = MQ80486DX4-100 | s-spec 5 = SX877
    4 KB (414 words) - 16:13, 13 December 2017
  • | socket = | socket 2 =
    2 KB (234 words) - 16:13, 13 December 2017
  • | s-spec 5 = SX806 | socket =
    3 KB (260 words) - 16:14, 13 December 2017
  • | socket = | socket 2 =
    3 KB (244 words) - 16:14, 13 December 2017
  • | s-spec 5 = SX677 | v core = 5 V
    3 KB (240 words) - 16:14, 13 December 2017
  • | s-spec 5 = SXE63 | v core = 5 V
    3 KB (251 words) - 16:14, 13 December 2017
  • | s-spec 5 = SX673 | cpuid 5 = 428
    4 KB (332 words) - 16:14, 13 December 2017
  • | part number 5 = KU80486SX-33 | s-spec 5 = SX797
    4 KB (345 words) - 16:14, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    2 KB (253 words) - 16:14, 13 December 2017
  • | v core = 5 V | socket = Socket 1
    2 KB (220 words) - 16:14, 13 December 2017
  • | microarch 5 = Broadwell | package 5 = FCBGA-1288
    25 KB (3,397 words) - 03:12, 3 October 2022
  • | microarch 5 = Haswell | package 5 = FCLGA-1155
    34 KB (4,663 words) - 20:38, 20 February 2023
  • | v core = 5 V | socket 0 = Socket 1
    2 KB (218 words) - 15:18, 13 December 2017
  • | v core = 5 V | socket 0 = Socket 1
    2 KB (227 words) - 15:18, 13 December 2017
  • | v core = 5 V | socket 0 = Socket 1
    3 KB (270 words) - 15:18, 13 December 2017
  • | v core = 5 V | socket 0 = Socket 1
    3 KB (237 words) - 15:18, 13 December 2017
  • |die length=44.5 |die width=44.5
    1 KB (209 words) - 21:53, 7 February 2024
  • | v core = 5 V | socket 0 = Socket 1
    3 KB (286 words) - 15:18, 13 December 2017
  • | first launched = June 5, 1995 | socket 0 = Socket 1
    2 KB (235 words) - 15:19, 13 December 2017
  • | socket 0 = Socket 1 | socket 0 type =
    2 KB (237 words) - 15:19, 13 December 2017
  • | v core = 5 V | socket 0 = Socket 1
    3 KB (235 words) - 15:19, 13 December 2017
  • | v core = 5 V | socket 0 = Socket 1
    3 KB (235 words) - 15:19, 13 December 2017
  • | v core = 5 V | socket 0 = Socket 1
    3 KB (256 words) - 15:19, 13 December 2017
  • | v core = 5 V | socket 0 = Socket 1
    3 KB (256 words) - 15:19, 13 December 2017
  • | socket = Socket 1 | socket 2 = Socket 2
    7 KB (1,043 words) - 16:50, 14 June 2020
  • | v core = 5 V | v core tolerance = 5%
    3 KB (288 words) - 15:18, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (290 words) - 15:18, 13 December 2017
  • | frequency = 12.5 MHz | bus speed = 12.5 MHz
    3 KB (290 words) - 15:18, 13 December 2017
  • | v core = 5 V | socket 0 = PLCC-68
    3 KB (260 words) - 15:18, 13 December 2017
  • | v core = 5 V | socket 0 = PLCC-68
    3 KB (261 words) - 15:18, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (275 words) - 15:18, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (274 words) - 15:18, 13 December 2017
  • | frequency = 12.5 MHz | bus speed = 12.5 MHz
    3 KB (289 words) - 15:18, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (281 words) - 15:18, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    2 KB (252 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (235 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (235 words) - 15:18, 13 December 2017
  • | frequency = 12.5 MHz | bus speed = 12.5 MHz
    2 KB (235 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (240 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (241 words) - 15:17, 13 December 2017
  • | frequency = 12.5 MHz | bus speed = 12.5 MHz
    2 KB (241 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (270 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (291 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (296 words) - 15:18, 13 December 2017
  • | frequency = 12.5 MHz | bus speed = 12.5 MHz
    3 KB (278 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (277 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (241 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (241 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (240 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (240 words) - 15:18, 13 December 2017
  • | frequency = 12.5 MHz | bus speed = 12.5 MHz
    2 KB (240 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (279 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (279 words) - 15:17, 13 December 2017
  • | frequency = 12.5 MHz | bus speed = 12.5 MHz
    3 KB (259 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    2 KB (239 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (263 words) - 15:17, 13 December 2017
  • | socket = ...= Computerworld| issue = | pages = 27-29| doi =| rmonth = 5| rday = 25| ryear = 2016}}</ref>. In an attempt to reduce power co
    5 KB (750 words) - 21:22, 24 May 2016
  • | v core = 5 V | v core tolerance = 5%
    3 KB (339 words) - 15:18, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (339 words) - 15:18, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (309 words) - 15:18, 13 December 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (309 words) - 15:18, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (275 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (273 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (269 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (255 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (271 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (263 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (255 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (265 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (256 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (258 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (267 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (267 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (267 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (267 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (267 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (267 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (261 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (264 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (277 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (277 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (278 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (278 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (280 words) - 04:32, 22 October 2019
  • | frequency = 12.5 MHz | v core = 5 V
    3 KB (281 words) - 15:17, 13 December 2017
  • | v core = 5 V | socket 0 = PLCC-68
    3 KB (286 words) - 15:17, 13 December 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (281 words) - 15:17, 13 December 2017
  • | v core = 5 V | socket 0 = PLCC-68
    3 KB (281 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (290 words) - 15:17, 13 December 2017
  • | frequency = 12.5 MHz | v core = 5 V
    3 KB (296 words) - 15:17, 13 December 2017
  • | v core = 5 V | v core tolerance = 5 %
    3 KB (296 words) - 15:17, 13 December 2017
  • | v core = 5 V | v core tolerance = 5 %
    3 KB (296 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (279 words) - 15:17, 13 December 2017
  • | frequency = 12.5 MHz | v core = 5 V
    3 KB (284 words) - 15:17, 13 December 2017
  • | v core = 5 V | socket 0 = PQFP-80
    3 KB (284 words) - 15:17, 13 December 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (284 words) - 15:17, 13 December 2017
  • | v core = 5 V | socket 0 = PQFP-80
    3 KB (284 words) - 15:17, 13 December 2017
  • | bus speed = 2.5 MHz | bus rate = 2.5 MT/s
    3 KB (279 words) - 15:17, 13 December 2017
  • | frequency = 12.5 MHz | v core = 5 V
    3 KB (284 words) - 15:17, 13 December 2017
  • | v core = 5 V | socket 0 = TQFP-80
    3 KB (284 words) - 15:17, 13 December 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (284 words) - 15:17, 13 December 2017
  • | v core = 5 V | socket 0 = TQFP-80
    3 KB (284 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (269 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (275 words) - 15:16, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (269 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (275 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (260 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (260 words) - 15:17, 13 December 2017
  • | process = 1.5 µm | v core = 5 V
    3 KB (260 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (260 words) - 15:17, 13 December 2017
  • | bus speed = 1.5 MHz | bus rate = 1.5 MT/s
    3 KB (250 words) - 15:17, 13 December 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (319 words) - 16:55, 30 June 2017
  • | v core = 5 V | socket 0 = TQFP-100
    3 KB (319 words) - 16:56, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (319 words) - 16:56, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (319 words) - 16:56, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (330 words) - 16:54, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (319 words) - 16:55, 30 June 2017
  • | v core = 5 V | socket 0 = PQFP-100
    3 KB (319 words) - 16:55, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (319 words) - 16:56, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (319 words) - 16:56, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (329 words) - 16:55, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (329 words) - 16:56, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (330 words) - 16:54, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    4 KB (387 words) - 17:00, 30 June 2017
  • | v core = 5 V | socket 0 = TQFP-100
    4 KB (387 words) - 17:01, 30 June 2017
  • | v core = 5 V | socket 0 = TQFP-100
    4 KB (387 words) - 17:01, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    4 KB (387 words) - 17:01, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    4 KB (402 words) - 16:59, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    4 KB (387 words) - 17:00, 30 June 2017
  • | v core = 5 V | socket 0 = PQFP-100
    4 KB (387 words) - 17:00, 30 June 2017
  • | v core = 5 V | socket 0 = PQFP-100
    4 KB (387 words) - 17:01, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    4 KB (387 words) - 17:01, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    4 KB (397 words) - 17:00, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    4 KB (397 words) - 17:01, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    4 KB (400 words) - 16:59, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (351 words) - 16:53, 30 June 2017
  • | v core = 5 V | socket 0 = TQFP-100
    3 KB (351 words) - 16:53, 30 June 2017
  • | v core = 5 V | socket 0 = TQFP-100
    3 KB (351 words) - 16:54, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (351 words) - 16:54, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (366 words) - 16:52, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (351 words) - 16:53, 30 June 2017
  • | v core = 5 V | socket 0 = PQFP-100
    3 KB (351 words) - 16:53, 30 June 2017
  • | v core = 5 V | socket 0 = PQFP-100
    3 KB (351 words) - 16:54, 30 June 2017
  • | v core = 5 V | socket 0 = PQFP-100
    3 KB (351 words) - 16:54, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (366 words) - 16:52, 30 June 2017
  • | bus speed = 5 MHz | bus rate = 5 MT/s
    3 KB (362 words) - 16:53, 30 June 2017
  • | v core = 5 V | v core tolerance = 5%
    3 KB (362 words) - 16:53, 30 June 2017
  • | clock min = 5 MHz | socket =
    5 KB (616 words) - 14:24, 1 May 2019
  • | first announced = April 5, 2011 | first launched = April 5, 2011
    4 KB (482 words) - 05:08, 18 February 2020
  • | socket 0 = BGA-676 | socket 0 type = BGA
    8 KB (1,031 words) - 14:09, 10 May 2019
  • | socket = <tr><th colspan="5" style="background:#D6D6FF;">Am2000 Models</th></tr>
    11 KB (1,421 words) - 14:45, 9 December 2018
  • | socket 0 = BGA-868 | socket 0 type = BGA
    3 KB (367 words) - 15:16, 13 December 2017
  • | socket = FCBGA-896 | socket 2 =
    4 KB (492 words) - 00:37, 28 June 2016
  • | socket = Socket 5 | socket 2 = Socket 7
    8 KB (1,002 words) - 22:19, 17 June 2022
  • | socket = ...p for the first nine months of [[volume production]]. The deal included a $5 million prepayment - a payment Apple never delivered.
    8 KB (1,228 words) - 20:49, 2 June 2019
  • | clock multiplier = 5 | socket 0 = BGA-359
    3 KB (331 words) - 16:13, 13 December 2017
  • | socket = Socket 7 | socket 2 =
    8 KB (1,156 words) - 23:10, 1 August 2016
  • {{amd title|AMD-SSA/5-75ABR}} | name = AMD-SSA/5-75ABR
    3 KB (313 words) - 16:08, 13 December 2017
  • {{amd title|AMD-SSA/5-90ABQ}} | name = AMD-SSA/5-90ABQ
    3 KB (292 words) - 16:08, 13 December 2017
  • | series = SSA/5 | clock multiplier = 1.5
    3 KB (303 words) - 16:08, 13 December 2017
  • | series = SSA/5 | clock multiplier = 1.5
    3 KB (294 words) - 16:08, 13 December 2017
  • | series = SSA/5 | clock multiplier = 1.5
    3 KB (308 words) - 16:07, 13 December 2017
  • | series = SSA/5 | clock multiplier = 1.5
    3 KB (304 words) - 16:07, 13 December 2017
  • | clock multiplier = 1.5 | core family = 5
    3 KB (296 words) - 16:07, 13 December 2017
  • | clock multiplier = 1.5 | core family = 5
    3 KB (296 words) - 16:07, 13 December 2017
  • | clock multiplier = 1.5 | core family = 5
    3 KB (296 words) - 16:07, 13 December 2017
  • | clock multiplier = 1.5 | core family = 5
    3 KB (296 words) - 16:07, 13 December 2017
  • | core family = 5 | socket 0 = Socket 5
    3 KB (298 words) - 16:07, 13 December 2017
  • | core family = 5 | socket 0 = Socket 5
    3 KB (296 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Socket 5
    3 KB (296 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Socket 5
    3 KB (317 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Socket 5
    3 KB (324 words) - 16:08, 13 December 2017
  • | clock multiplier = 2.5 | core family = 5
    3 KB (333 words) - 16:09, 13 December 2017
  • | core family = 5 | v core tolerance = 5%
    3 KB (333 words) - 16:09, 13 December 2017
  • | clock multiplier = 2.5 | core family = 5
    3 KB (343 words) - 16:09, 13 December 2017
  • | clock multiplier = 2.5 | core family = 5
    3 KB (298 words) - 16:09, 13 December 2017
  • | core family = 5 | v core tolerance = 5%
    3 KB (298 words) - 16:09, 13 December 2017
  • | core family = 5 | v core tolerance = 5%
    3 KB (314 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (322 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (298 words) - 16:09, 13 December 2017
  • | first launched = March 5, 1998 | core family = 5
    3 KB (310 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (314 words) - 16:09, 13 December 2017
  • | first launched = March 5, 1998 | clock multiplier = 3.5
    3 KB (314 words) - 16:09, 13 December 2017
  • | first launched = March 5, 1998 | clock multiplier = 3.5
    3 KB (295 words) - 16:09, 13 December 2017
  • | first launched = March 5, 1998 | core family = 5
    3 KB (314 words) - 16:09, 13 December 2017
  • | core family = 5 | v core tolerance = 5%
    3 KB (316 words) - 01:23, 9 November 2020
  • | first launched = March 5, 1998 | core family = 5
    3 KB (295 words) - 16:09, 13 December 2017
  • | first launched = March 5, 1998 | clock multiplier = 4.5
    3 KB (314 words) - 16:09, 13 December 2017
  • | first launched = March 5, 1998 | clock multiplier = 4.5
    3 KB (329 words) - 16:09, 13 December 2017
  • | socket = Socket 7 | socket 2 = Super Socket 7
    13 KB (1,969 words) - 18:07, 2 October 2019
  • |introduction=October 5, 2017 |decode=5-way
    30 KB (4,192 words) - 13:48, 10 December 2023
  • |core family=5 |socket 0=Super 7
    2 KB (291 words) - 11:11, 5 January 2019
  • | clock multiplier = 3.5 | core family = 5
    3 KB (317 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (317 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (344 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (398 words) - 16:08, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (381 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (375 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (387 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | clock multiplier = 5.5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (338 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (364 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (369 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (364 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (369 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (364 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (368 words) - 16:08, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (343 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (353 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (344 words) - 16:08, 13 December 2017
  • | clock multiplier = 5.5 | core family = 5
    3 KB (338 words) - 16:08, 13 December 2017
  • | clock multiplier = 5.5 | core family = 5
    3 KB (338 words) - 16:09, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (336 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 5.5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (340 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (361 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (361 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (361 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (362 words) - 16:08, 13 December 2017
  • | clock multiplier = 6.5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (339 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (340 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (340 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = BGA-360
    3 KB (335 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (340 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (341 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (341 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (340 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (341 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = BGA-360
    3 KB (335 words) - 16:08, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (336 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (335 words) - 16:08, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (336 words) - 16:08, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (347 words) - 16:08, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (345 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (345 words) - 16:09, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (345 words) - 16:09, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (345 words) - 16:09, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (345 words) - 16:09, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (346 words) - 16:09, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (345 words) - 16:09, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (346 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (344 words) - 16:09, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (344 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (344 words) - 16:09, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (344 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (344 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (344 words) - 16:09, 13 December 2017
  • | socket = Socket 7 | socket 2 = Super Socket 7
    9 KB (1,264 words) - 02:29, 19 January 2017
  • | socket = Socket A ...the end user to future upgrades. AMD moved in the same direction, using [[Socket A]] for {{amd|Athlon}} and the new Duron family.
    19 KB (2,874 words) - 17:30, 3 December 2016
  • | first announced = June 5, 2000 | clock multiplier = 5.5
    4 KB (423 words) - 16:07, 13 December 2017
  • | first announced = June 5, 2000 | socket 0 = Socket A
    4 KB (438 words) - 16:07, 13 December 2017
  • | first announced = June 5, 2000 | clock multiplier = 6.5
    4 KB (423 words) - 16:07, 13 December 2017
  • | first announced = June 5, 2000 | socket 0 = Socket A
    4 KB (423 words) - 16:07, 13 December 2017
  • | first announced = September 5, 2000 | first launched = September 5, 2000
    4 KB (423 words) - 16:07, 13 December 2017
  • | first announced = June 5, 2000 | v core = 1.5 V
    4 KB (427 words) - 16:07, 13 December 2017
  • | first announced = June 5, 2000 | v core = 1.5 V
    4 KB (419 words) - 16:07, 13 December 2017
  • | first announced = June 5, 2000 | clock multiplier = 6.5
    4 KB (419 words) - 16:07, 13 December 2017
  • | first announced = September 5, 2000 | first launched = September 5, 2000
    4 KB (419 words) - 16:07, 13 December 2017
  • | package 0 pitch = 0.5 mm | socket 0 = QFP-208
    6 KB (731 words) - 15:41, 5 July 2018
  • |extension 5=SSE |core name 5=Applebred
    6 KB (923 words) - 16:48, 3 March 2022
  • |cores 5=16 |extension 5=SSE3
    79 KB (12,095 words) - 15:27, 9 June 2023
  • |cores 5=16 |extension 5=SSE3
    57 KB (8,701 words) - 22:11, 9 October 2022
  • | socket 0 = BGA-1296 | socket 0 type = BGA
    6 KB (633 words) - 16:25, 13 December 2017
  • |socket 0=BGA-1296 |socket 0 type=BGA
    5 KB (584 words) - 18:02, 9 February 2019
  • | socket 0 = BGA-1296 | socket 0 type = BGA
    6 KB (639 words) - 12:32, 9 May 2018
  • | socket 0 = BGA-1296 | socket 0 type = BGA
    6 KB (642 words) - 16:25, 13 December 2017
  • | socket 0 = BGA-1296 | socket 0 type = BGA
    7 KB (847 words) - 20:58, 21 October 2023
  • | socket 0 = BGA-1296 | socket 0 type = BGA
    7 KB (837 words) - 23:15, 25 August 2019
  • | clock multiplier = 3.5 | core family = 5
    3 KB (362 words) - 16:09, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (374 words) - 16:09, 13 December 2017
  • | core family = 5 | socket 0 = Super 7
    3 KB (371 words) - 16:09, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (349 words) - 16:09, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (349 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (377 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (355 words) - 16:09, 13 December 2017
  • | clock multiplier = 5.5 | core family = 5
    3 KB (355 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (355 words) - 16:09, 13 December 2017
  • | clock multiplier = 3.5 | core family = 5
    3 KB (355 words) - 16:09, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (355 words) - 16:09, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    4 KB (551 words) - 19:10, 27 October 2018
  • | clock multiplier = 4.5, 6 (2x is changed for 6x) | core family = 5
    4 KB (569 words) - 15:16, 26 October 2018
  • | clock multiplier = 5 | core family = 5
    3 KB (368 words) - 16:09, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (368 words) - 16:09, 13 December 2017
  • | core family = 5 | tdp = 9.5 W
    3 KB (361 words) - 09:39, 27 July 2020
  • |clock multiplier=5.0 |core family=5
    2 KB (299 words) - 06:06, 24 March 2023
  • | core family = 5 | tdp = 9.5 W
    4 KB (557 words) - 03:30, 26 October 2018
  • | clock multiplier = 4.5 | core family = 5
    3 KB (361 words) - 16:09, 13 December 2017
  • | clock multiplier = 4.5 | core family = 5
    3 KB (361 words) - 16:09, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (361 words) - 16:09, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (361 words) - 16:09, 13 December 2017
  • | clock multiplier = 5 | core family = 5
    3 KB (361 words) - 16:09, 13 December 2017
  • | package 5 = | socket =
    3 KB (332 words) - 01:56, 28 September 2019
  • | first announced = April 5, 2011 | first launched = April 5, 2011
    11 KB (1,395 words) - 08:36, 4 November 2020
  • | package 0 width = 52.5 mm | package 0 height = 5.316 mm
    6 KB (644 words) - 16:28, 13 December 2017
  • | bus rate = 5 GT/s | package 0 width = 52.5 mm
    5 KB (643 words) - 01:04, 24 December 2017
  • | bus rate = 5 GT/s | package 0 width = 52.5 mm
    5 KB (643 words) - 01:04, 24 December 2017
  • | bus rate = 5 GT/s | package 0 width = 52.5 mm
    5 KB (640 words) - 01:04, 24 December 2017
  • | bus rate = 5 GT/s | package 0 width = 52.5 mm
    5 KB (637 words) - 01:04, 24 December 2017
  • | bus rate = 5 GT/s | package 0 width = 52.5 mm
    5 KB (637 words) - 01:04, 24 December 2017
  • | bus rate = 5 GT/s | package 0 width = 52.5 mm
    4 KB (485 words) - 16:27, 13 December 2017
  • | bus rate = 5 GT/s | package 0 width = 52.5 mm
    4 KB (477 words) - 16:27, 13 December 2017
  • | package 0 width = 52.5 mm | package 0 height = 5.316 mm
    5 KB (535 words) - 16:28, 13 December 2017
  • | package 0 width = 52.5 mm | package 0 height = 5.316 mm
    5 KB (534 words) - 17:04, 15 October 2019
  • | first announced = June 5, 2001 | first launched = June 5, 2001
    11 KB (1,571 words) - 18:57, 17 November 2016
  • | first announced = January 5, 2015 | first launched = January 5, 2015
    5 KB (531 words) - 16:15, 13 December 2017
  • | microarch 5 = Jaguar | proc 5 = 32 nm
    2 KB (292 words) - 02:17, 8 July 2018
  • | socket = Socket 754 | socket 2 = Socket 939
    2 KB (209 words) - 18:21, 17 November 2016
  • | first announced = June 5, 2001 | first launched = June 5, 2001
    4 KB (542 words) - 15:20, 13 December 2017
  • | first announced = June 5, 2001 | first launched = June 5, 2001
    4 KB (538 words) - 15:20, 13 December 2017
  • | first announced = June 5, 2001 | first launched = June 5, 2001
    4 KB (542 words) - 15:20, 13 December 2017
  • | socket = * 5 V
    2 KB (173 words) - 16:55, 2 January 2017
  • | proc 5 = 65 nm | socket =
    7 KB (946 words) - 01:29, 22 November 2016
  • | proc 5 = 180 nm | socket =
    4 KB (538 words) - 15:52, 2 January 2017
  • |socket=Socket G1 ...d QC''') is the core name given by [[Intel]] for their [[quad-core]] using 5 series chipset. These were first generation ({{intel|Nehalem|l=arch}}-based
    2 KB (328 words) - 07:48, 24 December 2019
  • {{title|Socket-G1}}[[File:rPGA988A.svg|300px|right]] ...rocessors designed by [[Intel]] for their {{intel|5 Series}} chipset. This socket was used for various {{intel|Nehalem|l=arch}} and {{intel|Westmere|l=arch}}
    2 KB (295 words) - 04:45, 2 December 2016
  • ...} chipset. It's considered a {{packages|Socket-G1}} type although it's not socket-mounted and is instead permanently soldered on the motherboard.
    2 KB (274 words) - 18:31, 1 December 2016
  • | socket = BGA-1521 | socket 2 =
    6 KB (827 words) - 15:41, 29 December 2016
  • {{amd title|Socket AM4}} |name=Socket AM4
    30 KB (6,098 words) - 01:58, 12 January 2024
  • |cores 5=20 *** 5 stages eliminated from fetch to compute vs {{\\|POWER8}}
    14 KB (1,905 words) - 23:38, 22 May 2020
  • | socket = Socket AM4 Ryzen utilizes AMD's unified {{amd|Socket AM4}}. However, Ryzen 7 processors are a complete [[system on a chip]], int
    15 KB (2,095 words) - 12:18, 2 October 2022
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    4 KB (677 words) - 17:58, 10 May 2023
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    4 KB (579 words) - 23:32, 25 March 2023
  • |package name 1=amd,socket am4 ...y [[AMD]] in early [[2017]]. The 1800X is AMD's flagship model for the AM4 socket. It is based on their {{amd|Zen|Zen microarchitecture|l=arch}}, fabricated
    5 KB (694 words) - 23:32, 25 March 2023
  • | microarch 5 = Cortex-A53 | proc 5 = 14 nm
    10 KB (1,247 words) - 00:25, 8 November 2023
  • {{amd title|Ryzen 5}} | title = AMD Ryzen 5
    14 KB (1,864 words) - 07:09, 7 October 2020
  • | socket = Socket AM4 ...formance and budget processors. Ryzen 3 are situated below the {{amd|Ryzen 5}} family with 4 cores but no [[simultaneous multithreading]].
    11 KB (1,506 words) - 22:12, 6 January 2020
  • {{amd title|Ryzen 5 1600X}} |name=AMD Ryzen 5 1600X
    4 KB (547 words) - 23:32, 25 March 2023
  • {{amd title|Ryzen 5 1500X}} |name=AMD Ryzen 5 1500X
    3 KB (540 words) - 23:32, 25 March 2023
  • |die count=5 ...ltiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    3 KB (563 words) - 11:06, 15 April 2020
  • |cores 5=28 |extension 5=SSE3
    15 KB (1,978 words) - 22:13, 6 April 2023
  • | proc 5 = 14 nm | socket =
    1 KB (85 words) - 05:15, 12 March 2017
  • {{amd title|Ryzen 5 1600}} |name=AMD Ryzen 5 1600
    4 KB (692 words) - 23:32, 25 March 2023
  • {{amd title|Ryzen 5 1400}} |name=AMD Ryzen 5 1400
    3 KB (528 words) - 23:32, 25 March 2023
  • | power = 5 W | socket 0 =
    4 KB (418 words) - 16:31, 13 December 2017
  • | power = 5 W | socket 0 =
    4 KB (428 words) - 16:31, 13 December 2017
  • | power = 5 W | socket 0 = BGA-452
    4 KB (461 words) - 16:31, 13 December 2017
  • | proc 5 = 130 nm | socket =
    4 KB (468 words) - 18:22, 12 April 2017
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    3 KB (508 words) - 23:31, 25 March 2023
  • | socket = LGA-3647 '''Xeon Gold''' is a family of {{arch|64}} [[x86]] dual/quad-socket multi-core high performance server microprocessors introduced by [[Intel]]
    9 KB (1,195 words) - 05:38, 8 June 2021
  • | proc 3 = 5 nm | socket = Socket SP3
    19 KB (2,580 words) - 02:46, 23 November 2022
  • ...s based on the {{amd|Zen 3|l=arch}} microarchitecture for single- and dual-socket server platforms. Launched in March 2021 it succeeded the second generation ...sors are available in a 4094-contact [[land grid array]] package for {{amd|Socket SP3|l=package}} and backwards compatible with motherboards designed for "Ro
    19 KB (2,734 words) - 01:26, 31 May 2021
  • | proc 5 = 0.25 µm | package 5 =
    3 KB (388 words) - 06:17, 18 June 2017
  • | socket = Socket TR4 | socket 2 = Socket TRX4
    13 KB (1,744 words) - 15:33, 16 April 2022
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    4 KB (600 words) - 23:55, 25 March 2023
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    4 KB (604 words) - 23:55, 25 March 2023
  • {{amd title|Ryzen 5 PRO 1600}} |name=Ryzen 5 PRO 1600
    4 KB (580 words) - 23:55, 25 March 2023
  • {{amd title|Ryzen 5 PRO 1500}} |name=Ryzen 5 PRO 1500
    3 KB (551 words) - 23:55, 25 March 2023
  • |package name 1=amd,socket am4 ...ted on a [[14 nm process]]. The PRO 1300 operates at a base frequency of 3.5 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of
    3 KB (546 words) - 23:55, 25 March 2023
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    3 KB (546 words) - 23:55, 25 March 2023
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    4 KB (575 words) - 23:55, 25 March 2023
  • |cores 5=12 |extension 5=SSE3
    52 KB (7,651 words) - 00:59, 6 July 2022
  • |first launched=October 5, 2017 ...}} chipset ({{intel|Platform Controller Hub|HUB}}). Despite using the same socket, those chips are not backwards-compatible with {{intel|Union Point}} (or {{
    4 KB (546 words) - 08:18, 1 January 2020
  • ...for 4 GT/s transfer rate. All Kaby Lake R processors use {{intel|BGA-1356|Socket BGA-1356}}. ** {{intel|UHD Graphics 620}} ({{intel|Gen9.5|l=arch}} GT2)
    5 KB (751 words) - 09:52, 11 February 2019
  • |cores 5=12 |extension 5=SSE3
    11 KB (1,613 words) - 08:39, 3 March 2024
  • | proc 5 = 16 nm | proc 9 = 5 nm
    2 KB (222 words) - 05:56, 10 May 2022
  • | socket = | socket 2 =
    6 KB (795 words) - 20:23, 31 October 2017
  • | proc 4 = 5 nm | socket =
    6 KB (838 words) - 09:33, 9 May 2019
  • | proc = 0.5 µm | proc 5 = 0.13 µm
    3 KB (282 words) - 10:03, 28 November 2017
  • |cores 5=10 |extension 5=SSE3
    32 KB (4,535 words) - 05:44, 9 October 2022
  • {{amd title|Ryzen 5 2400G}} |name=Ryzen 5 2400G
    4 KB (653 words) - 23:55, 25 March 2023
  • {{amd title|Ryzen 5 PRO 2400G}} |name=Ryzen 5 PRO 2400G
    4 KB (649 words) - 23:55, 25 March 2023
  • {{amd title|Ryzen 5 2600}} |name=Ryzen 5 2600
    3 KB (558 words) - 00:02, 26 March 2023
  • | {{mIRC|/sockudp}} | Can write a binary variable to a socket | {{mIRC|/sockwrite}} | Can write a binary variable to a socket
    12 KB (2,006 words) - 11:19, 19 January 2019
  • {{amd title|Ryzen 5 2600X}} |name=Ryzen 5 2600X
    3 KB (531 words) - 00:02, 26 March 2023
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    3 KB (526 words) - 00:02, 26 March 2023
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    3 KB (544 words) - 15:51, 30 May 2023
  • | rowspan="5" | {{amd|Zen 3|l=arch}} || 0xA || 0xF || 0x0 || 0x8 || || || Threadripper 5 ...xF || 0x0 || 0x0 || LN1-B0 || A8, A6, A4 APU "{{amd|Llano|l=core}}" ({{amd|Socket FM1|FM1|l=pack}})
    21 KB (3,215 words) - 13:50, 24 July 2023
  • | socket = | socket 2 =
    2 KB (209 words) - 17:56, 12 April 2018
  • The CRC field consists of 25 bits, allowing up to 5 random bits in error for the largest packet or alternatively, for different ...Us connected in a hybrid cube-mesh NVLink network topology along with dual-socket {{intel|Xeon}} CPUs. The two Xeons communicate with each other over [[Intel
    9 KB (1,518 words) - 04:38, 12 April 2024
  • {{amd title|Ryzen 5 2400GE}} |name=Ryzen 5 2400GE
    4 KB (628 words) - 00:02, 26 March 2023
  • |cores 5=30 * 25% higher [[clock]] (2.5 GHz, up from 2 GHz)
    17 KB (2,449 words) - 22:11, 4 October 2019
  • | socket = ** Up to 4 TiB in dual-socket configuration
    4 KB (494 words) - 20:33, 26 April 2019
  • ...ocesses messages, messages correspond to some kind of event, new data on a socket, a click on a button etc. ;wait 5 millisecond before continuing
    7 KB (1,244 words) - 10:31, 18 August 2020
  • Summit was designed to deliver 5-10x improvement in performance for real big science workload performance ov Weighing over 340 tons, Summit takes up 5,600 sq. ft. of floor space at [[Oak Ridge National Laboratory]]. Summit con
    9 KB (1,496 words) - 20:39, 21 July 2019
  • |process=5 nm |successor=Zen 5
    13 KB (1,821 words) - 19:28, 13 November 2023
  • |cores 5=16 |extension 5=SSE3
    4 KB (477 words) - 18:40, 26 March 2024
  • |package name 1=amd,socket am4 ...icated on a [[12 nm process]]. The 2300X operates at a base frequency of 3.5 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of
    3 KB (543 words) - 00:02, 26 March 2023
  • {{amd title|Ryzen 5 2500X}} |name=Ryzen 5 2500X
    3 KB (543 words) - 00:02, 26 March 2023
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    3 KB (527 words) - 00:02, 26 March 2023
  • {{amd title|Ryzen 5 2600E}} |name=Ryzen 5 2600E
    3 KB (527 words) - 00:02, 26 March 2023
  • | socket = | socket 2 =
    5 KB (656 words) - 05:07, 13 October 2019
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    3 KB (531 words) - 00:34, 26 March 2023
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    3 KB (534 words) - 00:34, 26 March 2023
  • {{amd title|Ryzen 5 PRO 2600}} |name=Ryzen 5 PRO 2600
    3 KB (531 words) - 00:34, 26 March 2023
  • {{amd title|Socket TR4 (SP3r2, sTR4)|package}} |name=Socket TR4
    86 KB (17,313 words) - 02:48, 13 March 2023
  • {{amd title|Socket SP3|package}} |name=Socket SP3
    110 KB (21,122 words) - 02:46, 13 March 2023
  • ...is the first [[ARM]]-based petascale supercomputer. The system consists of 5,184 [[Cavium]] [[ThunderX2 CN9975]] processors with slightly over 1.2 MW po <tr><th>Processors</th><td>5,184<br>2 x 72 x 36</td><td>&nbsp;</td><th>Type</th><td>[[DDR4]]</td><td>[[N
    8 KB (1,133 words) - 23:36, 2 June 2020
  • | first announced = February 5, 2018 | socket =
    4 KB (518 words) - 12:59, 19 May 2021
  • With the advent of [[multi-socket]] and [[multi-core]] architectures, additional levels of explicit paralleli ! colspan="5" | [[Intel]] Microarchitectures
    10 KB (1,204 words) - 15:03, 25 January 2023
  • {{comp table header|main|5:Processor|2:Memory}} {{comp table header|main|5:Processor|2:Memory}}
    8 KB (1,033 words) - 01:25, 26 January 2021
  • |proc=5 nm ...s based on the {{amd|Zen 4|l=arch}} microarchitecture for single- and dual-socket server platforms. Launched in November 2022 it succeeded the third generati
    14 KB (1,983 words) - 01:41, 2 April 2023
  • |transistors=5,000,000,000 Core(s) per socket: 4
    7 KB (917 words) - 02:35, 12 December 2023
  • | socket = Available in single and dual socket configurations using Cavium Coherent Processor Interconnect (CCPI™). Up t
    4 KB (452 words) - 13:02, 19 May 2021
  • |max mem=0.5 TiB Core(s) per socket: 48
    27 KB (4,202 words) - 14:32, 4 December 2018
  • | proc 5 = 7 nm | socket =
    2 KB (162 words) - 22:40, 28 April 2019
  • |package name 1=amd,socket am4 | usb rate = 5 Gbit/s
    4 KB (600 words) - 00:30, 26 March 2023
  • |frequency 5=3,200 MHz |package name 1=amd,socket am4
    3 KB (562 words) - 18:49, 4 May 2023
  • {{amd title|Ryzen 5 3600X}} |name=Ryzen 5 3600X
    3 KB (510 words) - 00:30, 26 March 2023
  • {{amd title|Ryzen 5 3600}} |name=Ryzen 5 3600
    4 KB (598 words) - 23:31, 11 May 2023
  • | socket = Socket AM4 ** {{amd|Ryzen 5}}
    3 KB (410 words) - 01:07, 26 May 2020
  • |decode=5-way |extension 5=SSE3
    5 KB (700 words) - 12:55, 20 November 2021
  • |die count=5 ...ltiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (596 words) - 19:44, 9 January 2021
  • |die count=5 ...configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (593 words) - 19:29, 9 January 2021
  • |die count=5 ...ltiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (596 words) - 19:31, 9 January 2021
  • |die count=5 ...ltiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (596 words) - 19:26, 9 January 2021
  • |die count=5 ...configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (601 words) - 19:19, 9 January 2021
  • |die count=5 ...ltiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (596 words) - 19:21, 9 January 2021
  • |clock multiplier=23.5 |die count=5
    4 KB (597 words) - 12:59, 9 June 2021
  • |die count=5 ...configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (593 words) - 21:00, 8 January 2021
  • |die count=5 ...ltiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (597 words) - 21:02, 8 January 2021
  • |die count=5 ...ltiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
    4 KB (590 words) - 20:55, 8 January 2021
  • {{amd title|Ryzen 5 3500X}} |name=Ryzen 5 3500X
    3 KB (500 words) - 00:34, 26 March 2023
  • {{amd title|Ryzen 5 PRO 3600}} |name=Ryzen 5 3600
    3 KB (505 words) - 00:10, 26 March 2023
  • {{amd title|Ryzen 5 PRO 2400GE}} |name=Ryzen 5 PRO 2400GE
    4 KB (632 words) - 00:10, 26 March 2023
  • HECToR underwent 5 major upgrades. ...re dual-core AMD Opteron operating at 2.8 GHz. There is 6 GB of memory per socket for a total system memory of 33.2 TiB. Rainier had a peak compute performan
    8 KB (1,037 words) - 14:44, 21 October 2019
  • | socket = | socket 2 =
    5 KB (648 words) - 09:21, 1 December 2019
  • {{amd title|Ryzen 5 3500}} |name=Ryzen 5 3500
    3 KB (505 words) - 00:10, 26 March 2023

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