{{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|4:Features}} {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}}

...may also serve as [[graphical processing unit]]s (GPUs), [[digital signal processor|signal processing units]] (DSPs), [[neural processing unit]] (NPUs), [[micr * '''[[digital signal processor]]''' ('''DSP''') - a microprocessor that specializes in the numerical manip

** Some vector instructions are faster, but like on {{\\|Airmont}}, none have throughput > * {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory

...or NOPs, CLC, some vector MOVs and some zeroing instructions (SUB, XOR and vector analogs). * {{x86|AVX2|<code>AVX2</code>}} - Advanced Vector Extensions 2; an extension that extends most integer instructions to 256 bi

* {{x86|AVX|<code>AVX</code>}} - Advanced Vector Extensions ...improved performance while saving power. Intel introduced a number of new vector computation ([[SIMD]]) and security instructions which improved [[floating

*** Incorporates an [[image signal processor]] (ISP) ...emory QoS for higher resolution displays and the integrated [[image signal processor]] (ISP)

...y Lake G processors. And the introduction of the first low power quad core processor. ! colspan="5" | [[Integrated Graphics Processor]] !! colspan="9" | Standards

* {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID ** {{x86|AVX512VL|<code>AVX512VL</code>}} - AVX-512 Vector Length

...rupt handler code. CR0 contains flags which control operating modes of the processor. User-mode code was never able to load values into these registers. Reading

{{comp table header|main|7:Main processor|3:GPU}} {{comp table header|main|7:Main processor|3:GPU|Features}}

{{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}} {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}}

| arch = 32-bit vector/matrix math processor + RISC cpu '''FastMATH''' was a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity

...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==

...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==

...r math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed. == Matrix and Vector Unit ==

...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==

...cture by introducing two additional [[physical cores]] into its mainstream processor die. Those two cores also come with up to 2 MiB of LLC slice per core (for ...[[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=

! colspan="11" | AMD Zen-based processor brands ...c logo.png|75px|link=amd/epyc]] || {{amd|EPYC}} || High-performance Server Processor || [[8 cores|8]]-[[32 cores|32]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|y

! colspan="11" | AMD Zen-based processor brands ...c logo.png|75px|link=amd/epyc]] || {{amd|EPYC}} || High-performance Server Processor || [[8 cores|8]]-[[64 cores|64]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|y

* OpenVG 1.1 vector graphics accelerator * Integrated image signal processor supports 20 MP

* OpenVG 1.1 vector graphics accelerator * Integrated image signal processor supports 20 MP

* OpenVG 1.1 vector graphics accelerator * Integrated image signal processor supports 20 MP

<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="5">Major Feature Diff</th></tr> |?has advanced vector extensions 2

<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr> |?has advanced vector extensions 2

<tr class="comptable-header"><th>&nbsp;</th><th colspan="11">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr> |?has advanced vector extensions 2

<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr> |?has advanced vector extensions 2

'''HD Graphics 610''' is a family of {{intel|Gen 9.5}} [[integrated graphics processor]] designed by [[Intel]] for their {{intel|Kaby Lake|l=arch}}-based micropro <tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="3">IGP</th><th colspan="5">Major Feature Diff</th></tr>

'''HD Graphics 615''' is a family of {{intel|Gen 9.5}} [[integrated graphics processor]] designed by [[Intel]] for their {{intel|Kaby Lake|l=arch}}-based micropro <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="5">Major Feature Diff</th></tr>

'''HD Graphics 620''' is a family of {{intel|Gen 9.5}} [[integrated graphics processor]] designed by [[Intel]] for their {{intel|Kaby Lake|l=arch}}-based micropro <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="5">Major Feature Diff</th></tr>

'''HD Graphics 630''' is a family of {{intel|Gen 9.5}} [[integrated graphics processor]] designed by [[Intel]] for their {{intel|Kaby Lake|l=arch}}-based micropro <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>

...ot offered this iteration). These modules allow IBM to address the various processor models with support for the different configurations such as bandwidth/line ...s including [[integer]] and [[floating point]] supporting [[scalar]] and [[vector]] operations. IBM claims this setup allows for higher utilization of resour

...he form of evaluation systems. At that time the ARM1 was the simplest RISC processor produced. ...cessor sets the [[PC]] to a specific memory address within the [[interrupt vector table]].

! Processor Series !! Cores/Threads !! Market * {{x86|VAES}} - 256-bit Vector AES instructions

'''Godson-2G''' ('''龙芯2G''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of ...iwu Hu, Yunji Chen. "GS464V: A High-Performance Low-Power XPU with 512-Bit Vector Extension". HotChips 22 (2010).

<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="4">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">I |?has advanced vector extensions 2

...way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Tho |theme=vector

...MD EPYC™ 7003 Series CPUs Set New Standard as Highest Performance Server Processor"] (Press release). AMD.com. March 15, 2021. Retrieved April 2021.</ref> ...ng as well as 2-way multithreading with up to 64 cores and 128 threads per processor. AMD claims up to 15% better performance per cost and 25% more performance

<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr> |?has advanced vector extensions 2

'''Skylake H''' ('''SKL-H''') is the processor core for [[Intel]]'s line of performance mobile processors based on the {{i <tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="4">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">I

...file]]). This was increased from 25 in the {{\\|ARM1}} for the purpose of processor status. As with the {{\\|ARM1}}, Register 15 ({{arm|R15}}) is still the [[P ...cessor sets the [[PC]] to a specific memory address within the [[interrupt vector table]].

<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="2">{{intel|Turbo Boost}}</th><th>Memory</th><th colspan="3 |?has advanced vector extensions 2

{{x86 title|Advanced Vector Extensions 512 (AVX-512)}}{{x86 isa main}} '''Advanced Vector Extensions 512''' ('''AVX-512''') is collective name for a number of {{arch

...'''LFM''') and is the lowest frequency-voltage operating point for a given processor. The upper bound is called the '''High Frequency mode''' ('''HFM''') and is ...drop into a lower [[P-State]] when not under any demanding workloads. The processor will switch around between the various P-States as needed and as dictated b

* Central Processor Assist for Cryptographic Function (CPACF) ** Dedicated co-processor for each core

* {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory * {{x86|XSAVES|<code>XSAVES</code>}} - Save processor supervisor-mode extended states to memory.

*** Vector divisions and square roots are faster * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID

{{comp table header|main|10:Main processor|3:IGP|6:Major Feature Diff}} |?has advanced vector extensions

'''Matrix-2000''' ('''MT-2000''') is a {{arch|64}} [[128-core]] [[many-core processor]] designed by [[NUDT]] and introduced in [[2017]]. This chip was designed e ...ended 256-bit vector instruction set architecture along with two 256-bit [[vector processing units]] (VPU). Each core is capable of performing 16 double-prec

...or card featuring 8 cores each capable of 307 GFLOPS/core for accelerating vector processing.]] ...[hardware acceleration|acceleration]] of domain-specific workloads such as vector operations, [[artificial neural network|ANNs]], cryptography, and graphics.

...ng those intense computations to be done by specialized hardware, the main processor's utilization goes down, freeing up resources for other workloads. * Vector Manipulation

...mponent attached to a system, but may also be integrated directly into the processor, sometimes in the form of an [[ISA]] extension. ...Whereas a co-processor is typically connected to the internals of the host processor, which then passes it instructions to execute, a generic accelerator is typ

...analog synapses. The ETANN is also the first commercial [[analog]] neural processor and is considered to be the first successful commercial neural network chip ...volatile EEPROM analog synaptic weight array and a 64-element analog input vector. The chip was reported the calculations to reach 2000 MCPs (million connect

* {{x86|avx512vnni|<code>AVX-512 VNNI</code>}} - AVX-512 Vector Neural Network Instructions ...uses a single heat spreader designed to cover the entire TDP range for all processor models. In total, each package exposes 12 channel DDR4 supporting rates of

{{comp table header|main|9:Processor}} {{comp table header|main|7:Main Processor|2:Integrated Graphics}}

* {{x86|AVX5124VNNI|<code>AVX5124VNNI</code>}} - AVX-512 Vector Neural Network * {{x86|AVX512VPOPCNTDQ|<code>AVX512VPOPCNTDQ</code>}} - AVX-512 Vector Population Count Doubleword and Quadword

...''' ('''SCR''') is the successor to {{\\|Lake Crest}}, a training [[neural processor]] microarchitecture designed by [[Intel Nervana]] for the data center and w ...successor to {{\\|Lake Crest}}, Intel Nervana's first commercial [[neural processor]] that made it to mass production. The chip itself is designed for training

Xavier is an autonomous machine processor designed by [[Nvidia]] and introduced at CES 2018. Silicon came back in the ...ht-core CPU cluster, GPU with additional inference optimizations, [[neural processor|deep learning accelerator]], vision accelerator, and a set of multimedia ac

...cheduler which consists of 32 entries. There is a 96-entry floating point (vector) [[physical register file]] (roughly 35-36 architected). There are two pipe {{comp table header|main|6:Main processor|2:Integrated Graphics}}

****** crypto EU, simple vector EU, vector shuffle/shift/mul, new FP store, new FP conversion ..., the FP FRP has also doubled in capacity with a 192-entry floating point (vector) [[physical register file]] (roughly 35-36 architected). There are three pi

...e]] RISC-V cores capable of running at up to 250 MHz along with a [[neural processor]] designed to accelerate [[convolutional neural network]]s (CNN). The GAP8 ...added for operating on [[Convolutional Neural Networks]] (CNNs), [[Support Vector Machines]] (SVMs), [[Bayesian]], Boosting, Visual Location, [[Fast Fourier

* "''U''" suffix indicates a standard (15 W) mobile processor * "''H''" suffix indicates a high-power (45 W) mobile processor

'''Streaming Hybrid Architecture Vector Engine v2.0''' ('''SHAVE v2.0''') is an accelerator microarchitecture desig * 128-bit vector arithmetic

...{{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}} [[processor families]]. {{comp table header|main|8:Main Processor|1:Cache|2:Memory}}

...eleration, this chip incorporates an Hexagon 685 vector processor with two vector extensions and an {{qualcomm|Adreno 615}} GPU. * {{qualcomm|Hexagon 685}} Vector Processor

...eleration, this chip incorporates an Hexagon 685 vector processor with two vector extensions and an {{qualcomm|Adreno 615}} GPU. * {{qualcomm|Hexagon 685}} Vector Processor

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 685|685}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 250|250}} image sensor processor

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 688|688}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 350|350}} image sensor processor

...quare root unit, a second vector multiplication unit, and a new horizontal vector arithmetic unit. {{comp table header|main|5:Main processor|2:Integrated Graphics|{{abbr|TDP}}|2:TDP down|2:TDP up}}

{{comp table header|main|8:Main processor|3:Integrated Graphics}} |theme=vector

{{comp table header|main|9:Main processor|3:Integrated Graphics}} |theme=vector

<tr><th>Processor</th><td>CPU</td><td>GPU</td><td>&nbsp;</td><th>Rack</th><td>Compute Racks</ ...tivity, they are connected directly to the CPUs. The {{ibm|POWER9|l=arch}} processor has six [[NVLink 2.0]] Bricks which are divided into three groups of two Br

! Processor Series !! Cores/Threads !! Market ! Processor Series !! Cores/Threads !! Market

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 685|685}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} image sensor processor

{{comp table header|main|8:Main processor|3:Integrated Graphics}} |theme=vector

{{comp table header|main|5:Main processor}} ...equencies, simultaneous multithreading support, and Arm’s {{arm|Scalable Vector Extension}} (SVE) extension. Those chips will are also planned to move to D

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 685|685}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 250|250}} image sensor processor

...Gen 1, 2, 3 (6&nbsp;Gb/s) link. Up to 32 SATA ports are available from the processor in total, as well as four USB 3.2 Gen [[wikipedia:USB 3.0#USB 3.2|2×1]] (1 ...onnectors, leveraging few of the CPU's SATA ports. One x8 PCIe link on the processor is reserved to attach the AMD {{amd|TRX40}} (HEDT) or {{amd|WRX80}} (workst

== ARMv8 Extensions and Processor Features == | sve || ARMv8.2-SVE || Scalable Vector Extension (SVE)

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 685|685}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 250|250L}} image sensor processor

...n one of the supplementary interfaces connects the Control Fabrics of each processor, i.e. the {{abbr|PSP}}, {{abbr|SMU}}s and other IPs, primarily for temperat ...plements USB 3.2 Gen 2×1<ref name="AMD-55901-11B1-*">{{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 19h Models 11h, Revision B1 Proc

'''SX-Aurora''' is the successor to the {{\\|SX-ACE}}, a [[16 nm]] [[vector processor]] microarchitecture designed by [[NEC]] and introduced in [[2018]]. ...6 2017 with a complete lineup that ranges from a workstation featuring one vector engine (VE) card to a full supercomputer with 64 VEs. NEC disclosed the arc

** {{nec|SX-Aurora|l=arch}}, a [[vector processor]] microarchitecture by [[NEC]]

** 1.33x larger vector register file (224-entry, up from 168) * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 685|685}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 250|250}} image sensor processor

.... Hewitt Lake processors are a single-chip solution consisting of just the processor chip itself since they incorporate the chipset along with the microprocesso |theme=vector

...chitecture. Broadwell DE are a single-chip solution consisting of just the processor chip itself since they incorporate the chipset along with the microprocesso |theme=vector

{{comp table header|main|8:Main processor|3:Integrated Graphics}} |theme=vector

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 680|680}} DSP with a Hexagon Vector Processor.

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 686|686}} DSP with a Hexagon Vector Processor.

* Central Processor (CP) **** Larger vector physical register files (???, up from 127 entries)

...programmability support beyond what the compute grid can offer. The vector processor and the compute grid communicate and syncronize using hardware synchronizat ...ed to the high-bandwidth 256 KiB TCM which is also connected to the vector processor.

...(Black Widow) vector compute nodes were added. Each node had 4 Cray vector processor. There are 32 GiB of memory for node for a total of 896 GiB of memory. With each vector processor capable of 25.6 gigaFLOPS, the new addition adds 2.87 teraFLOPS of compute

{{nec title|Vector Engine (VE)}} | title = NEC Vector Engine

{{nec title|Vector Engine Type 10A}} |family=Vector Engine

{{nec title|Vector Engine Type 10B}} |family=Vector Engine

{{nec title|Vector Engine Type 10C}} |family=Vector Engine

{{nec title|Vector Engine Type 10AE}} |family=Vector Engine

{{nec title|Vector Engine Type 10BE}} |family=Vector Engine

{{nec title|Vector Engine Type 10CE}} |family=Vector Engine

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 688|688}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 350|350}} image sensor processor

...pports mixed-precision operations including 8-bit, 16-bit, and 32-bit SIMD vector operations for both integer and floating-point. This was done in order to a ...high throughput and low latency one of its key requirements. For the inter-processor communication, Gaudi relies on standard Ethernet. This was done to avoid de

...pproach comprising of a large General Matrix Multiply (GMM) engine, Tensor Processor Cores (TPCs), and a large shared memory pool. === Tensor Processor Cores (TPC) ===

...6]] "CNS" cores along with a brand new clean-sheet design "NCORE" [[neural processor]]. CHA is a fully integrated SoC. It incorporates both the [[source bridge] ===== Floating Point & Vector =====

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 692|692}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 350L|350L}} image sensor processor

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 683|683}} DSP with a Hexagon Vector Processor.

...{qualcomm|Hexagon}} {{qualcomm|Hexagon 683|683}} DSP with a Hexagon Vector Processor.

{{armh title|Machine Learning Processor (MLP)|arch}} '''Machine Learning Processor''' ('''MLP''') is a first-generation [[neural processor]] microarchitecture designed by [[Arm]] for embedded and mobile SoCs as par

...on {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, and {{intel|Xeon Gold}} [[processor families]]. {{comp table header|main|8:Main Processor|1:Cache|2:Memory}}

...000 series of mobile and desktop <abbr title="Accelerated Processing Unit (processor with integrated graphics)">APU</abbr>s based on the {{amd|Zen 3|l=arch}} CP <tr><th>G</th><td>Desktop processor with integrated Radeon Vega Graphics (65 W)</td></tr>

The Cortex-A510 is a brand new ground-up CPU design. It borrows advanced processor components from Arm's high-performance cores - such as the branch predictio *** One shared vector unit

* Vector Tightly-Coupled Memory (VTCM) * Linley Fall Processor Conference 2021

This processor has no integrated graphics processing unit. ** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

This processor has no integrated graphics processing unit. ** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

This processor has no integrated graphics processing unit. ** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

This processor has no integrated graphics processing unit. ** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

This processor has no integrated graphics processing unit. ** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

This processor has no integrated graphics processing unit. ** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

This processor has no integrated graphics processing unit. ** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

This processor has no integrated graphics processing unit. ** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

...embedded microprocessors. Details about Au1 were disclosed at the Embedded Processor Forum in San Jose, CA, on June 13, 2000. The first processor using an Au1 CPU core, the Alchemy Au1000 {{abbr|SoC}}, is rated for core f

...uction in Q2, and in January 2009 the Au13xx models integrating a graphics processor. In October 2009 RMI merged with [[NetLogic Microsystems]] who was in turn * Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets

[[File:inv-day-processor-roadmap-16x9.jpg.rendition.intel.web.1648.927.jpg|thumb|right|Intel Xeon Ro * {{x86|AVX-VNNI-INT8|<code>AVX VNNI INT8</code>}} - AVX Vector Neural Network Instructions INT8

This 4th-generation server processor was first announced during Amazon's AWS re:Invent [[2023]] by Adam Selipsky ...ted to Arm's {{armh|Neoverse V2}} microarchitecture with 2x256b [[Scalable Vector Extension|SVE]] support, also bringing support up to [[Armv9.0]] ISA for th