From WikiChip
Vector Engine Type 10B - NEC
Edit Values | |
VE Type 10B | |
General Info | |
Designer | NEC |
Manufacturer | TSMC |
Model Number | Type 10B |
Market | Server, Workstation |
Introduction | Oct 26, 2017 (announced) 2018 (launched) |
General Specs | |
Family | Vector Engine |
Series | Type 10 |
Frequency | 1,400 MHz |
Microarchitecture | |
Microarchitecture | SX-Aurora |
Platform | SX-Aurora TSUBASA |
Process | 16 nm |
Transistors | 4,800,000,000 |
Technology | CMOS |
Die | 493.68 mm² 14.96 mm × 33.00 mm |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 48 GiB |
Succession | |
Vector Engine Type 10B is an octa-core vector processor designed by NEC and introduced in late 2017. This chip is fabricated on TSMC 16 nm process based on the SX-Aurora mircoarchitecture. VE Type 10B operates at 1.4 GHz and comes with 48 GiB of six 8-hi stacks of HBM2 memory.
Performance[edit]
The Vector Engine Type 10B operates at 1.4 GHz and integrates eight vector cores.
- Per core: 269 gigaFLOPS
- Per chip: 2.15 teraFLOPS2,150,000,000,000 FLOPS
2,150,000,000 KFLOPS
2,150,000 MFLOPS
2,150 GFLOPS
0.00215 PFLOPS
Cache[edit]
- Main article: SX-Aurora § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Card[edit]
The Vector Engine Type 10B supports water cooling or air cooling options.
Water cooled:
Air cooled:
Facts about "Vector Engine Type 10B - NEC"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Vector Engine Type 10B - NEC#pcie + |
base frequency | 1,400 MHz (1.4 GHz, 1,400,000 kHz) + |
core count | 8 + |
designer | NEC + |
die area | 493.68 mm² (0.765 in², 4.937 cm², 493,680,000 µm²) + |
die length | 14.96 mm (1.496 cm, 0.589 in, 14,960 µm) + |
die width | 33 mm (3.3 cm, 1.299 in, 33,000 µm) + |
family | Vector Engine + |
first announced | October 26, 2017 + |
first launched | 2018 + |
full page name | nec/vector engine/type 10b + |
has ecc memory support | false + |
instance of | microprocessor + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
ldate | 2018 + |
main image | + |
manufacturer | TSMC + |
market segment | Server + and Workstation + |
max memory | 49,152 MiB (50,331,648 KiB, 51,539,607,552 B, 48 GiB, 0.0469 TiB) + |
max memory bandwidth | 1,144.595 GiB/s (1,172,065.735 MiB/s, 1,229 GB/s, 1,229,000 MB/s, 1.118 TiB/s, 1.229 TB/s) + |
max memory channels | 48 + |
microarchitecture | SX-Aurora + |
model number | Type 10B + |
name | VE Type 10B + |
peak flops (double-precision) | 2,150,000,000,000 FLOPS (2,150,000,000 KFLOPS, 2,150,000 MFLOPS, 2,150 GFLOPS, 2.15 TFLOPS, 0.00215 PFLOPS, 2.15e-6 EFLOPS, 2.15e-9 ZFLOPS) + |
platform | SX-Aurora TSUBASA + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
series | Type 10 + |
supported memory type | HBM2-1600 + |
technology | CMOS + |
thread count | 8 + |
transistor count | 4,800,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |