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  • c/standard library
    ...nv.h>}} || C99 || Provides a set of functions for controlling the floating-point environment. ...89 || Provides a set of macros defining the implementation of the floating-point environment.
    5 KB (818 words) - 15:28, 9 March 2016
  • mips/mips32 instruction set
    | {{mips|MOVF}} || Move Conditional on Floating Point False | {{mips|MOVT}} || Move Conditional on Floating Point True
    18 KB (2,445 words) - 08:24, 9 November 2019
  • mirc/commands/var
    * '''<number>''' - Any arbitrary numerical value, can be a floating point number * '''<number>''' - Any arbitrary numerical value, can be a floating point number
    7 KB (1,162 words) - 05:34, 22 January 2024
  • mirc/commands/set
    * '''<number>''' - Any arbitrary numerical value, can be a floating point number * '''<number>''' - Any arbitrary numerical value, can be a floating point number
    4 KB (629 words) - 18:04, 12 July 2020
  • mirc/component object model
    |r4 || real, 4-byte floating point number || 1.17549435E-38 to 3.40282347E+38 |r8 || double real, 8-byte floating point number || 2.2250738585072014E-308 - 1.7976931348623157E+308
    27 KB (3,608 words) - 11:41, 25 October 2018
  • c/c11
    ...ment-related facilities, {{C|static assertion}}, Unicode support, floating-point characteristic macros, no-return functions, anonymous structures and unions
    8 KB (1,180 words) - 05:52, 14 September 2019
  • c/variables
    ...83, and 5294. By contrast with float, which is capable of storing floating point values such as 3.4, 30, -943.234, and 2e6. C provides a wide variety of typ
    6 KB (1,016 words) - 15:07, 9 March 2016
  • c/data types
    ...b-categories: char type, signed integer types, unsigned integer types, and floating types. == Floating Types ==
    7 KB (1,131 words) - 07:33, 4 January 2015
  • intel/quark
    ...ers have a Pentium x86-compatible instruction set without the x87 floating point unit.
    4 KB (434 words) - 03:31, 15 February 2016
  • c/c99
    ...th, <code>long long int</code>, extended identifiers, hexadecimal floating-point constants, compound literals, designated initializers, single line, <code>/ ...t}}''' {{C|reserved keywords|keyword}}. Given two pointers, if they do not point to two distinct objects, they are said to be ''aliases''. The ''restrict''
    9 KB (1,258 words) - 09:24, 4 January 2015
  • microprocessor
    ...ntral processing unit]] (CPU), [[arithmetic logic unit]] (ALU), [[floating point unit]] (FPU), [[control unit]] (CU), [[memory management unit]] (MMU), [[in ...oprocessor that specializes in the creation and manipulation of [[floating point]] values.
    8 KB (1,149 words) - 00:41, 16 September 2019
  • fairchild/f9450
    ...has built-in support for both single and extended (32 and 48-bit) floating point operations without the need for a co-processor extension as specified by th
    2 KB (253 words) - 16:27, 20 December 2015
  • fairchild/100k
    ...ple, the [[Floating Point Systems]] {{fps|FPS-264}} {{arch|64}} [[floating-point]] co-processor which was introduced in February [[1985]] performed 4 to 5 t * 1985: [[Floating Point Systems]] {{fps|FPS-264}} FP Coprocessor
    4 KB (521 words) - 14:38, 11 June 2017
  • national semiconductor/mm5700
    | {{national|MM5737}} || 8-digit, 4-function floating point calculator | {{national|MM5777}} || 6-digit, 4-function, floating point calculator
    2 KB (231 words) - 05:26, 10 November 2015
  • boolean algebra/majority function
    ...mentation optimization - such as floating the [[inversion bubble|inversion point]] to a more desired location.
    2 KB (368 words) - 21:04, 15 December 2015
  • intel/microarchitectures/bonnell
    ...then-new {{intel|Atom}} family. Bonnell, which was named after the highest point in [[wikipedia:Austin, Texas|Austin]] - [[wikipedia:Mount Bonnell|Mount Bon | {{intel|Pine Trail}} || {{intel|Tiger Point}} || {{intel|Pineview|l=core}} || Nettops
    38 KB (5,468 words) - 20:29, 23 May 2019
  • intel/microarchitectures/saltwell
    *** floating point & SIMD
    7 KB (872 words) - 19:42, 30 November 2017
  • intel/microarchitectures/haswell (client)
    * {{x86|FMA3|<code>FMA3</code>}} - Floating Point Multiply Accumulate, 3 operands
    27 KB (3,750 words) - 06:57, 18 November 2023
  • intel/microarchitectures/sandy bridge (client)
    ** {{intel|Ibex Peak|l=chipset}} → {{intel|Cougar Point}} ...computation ([[SIMD]]) and security instructions which improved [[floating point]] performance and throughput as well as speedup the throughput of various e
    84 KB (13,075 words) - 00:54, 29 December 2020
  • intel/microarchitectures/skylake (client)
    ** {{intel|Lynx Point|l=chipset}} → {{intel|Sunrise Point|l=chipset}} ...etween the two threads so that each thread gets every other cycle. At this point they are still [[macro-ops]] (i.e. variable-length [[x86]] architectural in
    79 KB (11,922 words) - 06:46, 11 November 2022
  • intel/80486
    ...algorithms were used to implement the new [[FPU]] yielding faster floating point calculations.
    8 KB (953 words) - 08:27, 29 October 2022
  • exponential technology/x704
    ...way pipeline - capable of issuing 1 arithmetic (either integer or floating point, but not both), a single load/store operation, and a branch instruction.
    8 KB (1,228 words) - 20:49, 2 June 2019
  • microarchitecture
    ...complete elements such as [[arithmetic logic unit]]s (ALUs) and [[floating point unit]]s (FPUs). Each of those microarchitectural elements are in turn repre
    3 KB (431 words) - 22:51, 21 November 2017
  • amd/k6-2
    ...ng point]] SIMD instructions. The addition of {{x86|3DNow!}} gave floating point calculations a serious performance boost and a much necessery boost since [
    13 KB (1,969 words) - 18:07, 2 October 2019
  • princeton/piton
    ...dified [[OpenSPARC T1]] core (+L1$), an L1.5 cache, L2 cache, a [[floating-point unit]] (FPU), a CPU Cache-Crossbar (CCX) arbiter, and three [[network on ch
    6 KB (731 words) - 15:41, 5 July 2018
  • amd/microarchitectures/k6
    ** Floating point
    4 KB (578 words) - 18:57, 22 May 2019
  • amd/microarchitectures/zen
    *** Floating Point (96, up from 60) ...e partitioning - every core is an independent core with its own [[floating-point]]/[[SIMD]] units and a [[L2]] cache. Previously, those units were shared be
    79 KB (12,095 words) - 15:27, 9 June 2023
  • amd/microarchitectures/zen 2
    ...rom {{\\|Zen+}} but improves the instruction stream bandwidth and floating-point throughput performance. ...spatch unit distributes macro-ops to the out-of-order integer and floating point execution units. It can dispatch up to six macro-ops per cycle.
    57 KB (8,701 words) - 22:11, 9 October 2022
  • pezy/pezy-scx/pezy-sc2
    ...kloads, the PEZY-SC2 introduced support for 16-bit half precision floating point support. At 1 GHz, the SC2 can peak at 16.4 TFLOPS for half precision.
    5 KB (683 words) - 11:15, 22 September 2018
  • x86/extensions
    ...K6-2|l=arch}} || SIMD extension for manipulating single-precision floating point ...|l=arch}} || Streaming SIMD Extensions, SIMD for single-precision floating point
    6 KB (764 words) - 08:53, 7 June 2020
  • cavium/microarchitectures/cnmips
    ...ed for network applications, the [[FPU]] was omitted as complex [[floating point]] operations are uncommon.
    7 KB (870 words) - 19:38, 23 June 2017
  • intel/microarchitectures/gen9.5
    ...computed in the HS stage) to tessellate U,V parametric domains into domain point topologies. ...lock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental oper
    29 KB (3,752 words) - 13:14, 19 April 2023
  • intel/microarchitectures/gen9
    ** Floating point atomics (min/max/cmpexch) ** 16-bit floating point capability is improved with native support for denormals and gradual underf
    33 KB (4,255 words) - 17:41, 1 November 2018
  • ibm/microarchitectures/power9
    *** Roughly 5 stages were also eliminated for fixed-point operations *** Up to 8 cycles were eliminated for floating-point operations
    14 KB (1,905 words) - 23:38, 22 May 2020
  • phytium/microarchitectures/xiaomi
    ...s can be dispatched each cycle. Everything is done [[in-order]] up to this point. [[File:phytim xiaomi fp eu.png|thumb|right|Floating-point execution unt]]
    7 KB (940 words) - 00:12, 8 March 2021
  • amd/microarchitectures/zen 3
    *** Floating point unit: **** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.
    15 KB (1,978 words) - 22:13, 6 April 2023
  • intel/microarchitectures/merced
    ** FPU can be accessed from the integer side by floating point get and set instructions. ...ree ports are available for branch execution, and two more handle floating point instructions.
    7 KB (978 words) - 21:16, 20 January 2021
  • arm holdings/microarchitectures/cortex-a55
    ** Up to 8x 16-bit [[floating point]] per cycle
    4 KB (603 words) - 04:23, 27 April 2023
  • mirc/identifiers/$int
    ...c title|$int Identifier}}'''$int''' Returns the integer part of a floating point number with no rounding.
    633 bytes (86 words) - 20:40, 13 August 2018
  • dec/microarchitectures/alpha 21064
    ** Support for VAX floating point
    4 KB (527 words) - 02:09, 4 August 2017
  • arm/armv1
    == Multiplication and Floating Point == ...in later ARM versions. Likewise there was no support for hardware floating point or an ability to do such operations on an external FPU coprocessor.
    10 KB (1,558 words) - 15:07, 2 July 2017
  • spec/cpu2017
    <tr><th></th><th>{{\|Integer}}</th><th>{{\|Floating Point}}</th></tr> ...mpiled on the tester's machine, the way compilation is conducted becomes a point disputes (e.g., no optimization?, default optimization?, higher optimizatio
    3 KB (399 words) - 01:10, 27 November 2017
  • x86/avx-512
    ...to pack sixteen [[single-precision]] eight [[double-precision]] [[floating-point]] numbers, or eight 64-bit or sixteen 32-bit integers within 512-bit vector : Adds new and supplemental 32-bit and 64-bit integer and floating point instructions.
    83 KB (13,667 words) - 15:45, 16 March 2023
  • intel/frequency behavior
    ...equency mode''' ('''HFM''') and is the highest frequency-voltage operating point. Note that the HFM frequency is usually referred to by its advertised name: ...ds that make heavy use of complex {{x86|AVX2}} operations (e.g. [[floating point]] and [[integer]] vector multiplications). This also includes the various {
    5 KB (797 words) - 01:10, 1 June 2020
  • ibm/microarchitectures/z14
    * '''FXU''' - Fixed-point unit * '''VFU''' - Vector and Floating point Unit
    8 KB (1,204 words) - 14:02, 23 September 2019
  • amd/microarchitectures/vega
    **Half precision floating point with 2x performance
    4 KB (510 words) - 12:42, 16 June 2020
  • spec/cpu2006
    <tr><th></th><th>Integer</th><th>Floating Point</th></tr> ...mpiled on the tester's machine, the way compilation is conducted becomes a point disputes (e.g., no optimization?, default optimization?, higher optimizatio
    3 KB (416 words) - 23:45, 27 January 2018
  • intel/microarchitectures/goldmont plus
    ...ider for fast scalar/packed single, double and extended precision floating point divides
    9 KB (1,128 words) - 13:28, 17 July 2023
  • microsoft/scorpio engine
    ...oC. The Compute Units operate at 1,172 MHz, each with 64 32-bit [[floating point]] [[multiply-accumulate]] units. At 1.172 GHz with 128 FLOP/cycle this chip | BP_(0-3) || Break Point Indicator
    15 KB (2,390 words) - 02:54, 17 May 2023
  • nudt/matrix-2000
    ...eatures three Fast Interconnect Transport (FIT) links. FITs are a point-to-point interconnect with a bidirectional bandwidth of 25.6 GB/s per link and a rep ...s]] (VPU). Each core is capable of performing 16 double-precision floating point operations each cycle.
    6 KB (894 words) - 07:26, 19 July 2019
  • mirc/identifiers/$round
    {{mirc title|$round Identifier}}'''$round''' returns a floating point number rounded to a number of decimal. '''Note''': mIRC's floating point accuracy is currently at 6 places, so D has no effect outside the range 0-6
    2 KB (208 words) - 14:42, 23 April 2020
  • bitmain/sophon/bm1680
    ...of [[L1D$]]. Additionally, there is also a VPFv2 coprocessor for floating point operations support.
    4 KB (603 words) - 09:59, 11 August 2018
  • accelerator
    The use of accelerators is not a new idea. Already in the 1980s, [[floating point]] co-processors were an early example of accelerator adaptation. However, h
    4 KB (539 words) - 19:47, 2 April 2019
  • coprocessor
    ...r]] typically with a more specialized set of operations such as [[floating point]] arithmetic, [[string processing]], and encryption. Generally, a distincti
    796 bytes (113 words) - 23:15, 20 November 2017
  • spec/cpu2017/floating point
    {{title|Floating Point - SPEC CPU2017}} Below are aggregated [[SPEC CPU2017]] Floating Point test scores.
    5 KB (733 words) - 01:29, 27 November 2017
  • intel/microarchitectures/cascade lake
    ...e was previously two FMA units for doing [[fused multiply-add]] [[floating-point]] operations, in Cascade Lake, new VNNI logic was added to that block which ...The persistence domain is a unique checkpoint. Once data makes it to that point, it’s persistence is guaranteed by the platform interface. This is shown
    32 KB (4,535 words) - 05:44, 9 October 2022
  • risc-v/standard extensions
    ...nctionality beyond the {{risc-v|integer base|core ISA}} such as [[floating point]] and operations and [[bit]] [[bit manipulation|manipulation]]. Extensions | F || Standard Extension for Single-Precision Floating-Point || 2.0 || Frozen || 25
    3 KB (363 words) - 12:04, 30 May 2023
  • esperanto/microarchitectures/et-minion
    ...fficiency. That is, this core was designed to achieve the highest floating point throughput with a high degree of energy efficiency. * Integrated vector floating point unit
    1 KB (150 words) - 04:58, 9 February 2018
  • flexpoint
    ...alues. Flexpoint combines the advantages of [[fixed point]] and [[floating point]] by splitting up the [[mantissa]] and the exponent part which is shared ac ...r their [[neural processor]] in [[2017]]. Flexpoint splits up a [[floating point]] value into its two fundamental components: [[mantissa]] and [[exponent]].
    2 KB (247 words) - 11:33, 7 November 2018
  • samsung/microarchitectures/m1
    ...pecial logic in the rename area to handle the renaming of those [[floating point]] µOPs. For the case of a branch misprediction, M1 has a perform fast map ...ued to the integer cluster and up to 2 µOPs may be issued to the floating point cluster.
    13 KB (1,962 words) - 14:48, 21 February 2019
  • samsung/microarchitectures/m3
    *** Floating Point cluster ...pecial logic in the rename area to handle the renaming of those [[floating point]] µOPs. For the case of a branch misprediction, the M3 has a perform fast
    20 KB (3,149 words) - 10:44, 15 February 2020
  • movidius/microarchitectures/shave v2.0
    ** 16/32-bit [[floating point]] ...ports 128-bit vector operations of all the integer (8-32 bit) and floating point (HP/FP) types. Since those operations can be done at in the same cycle, it'
    12 KB (1,749 words) - 19:05, 20 January 2021
  • qualcomm/microarchitectures/hexagon
    ** Only Fixed Point ** Floating Point
    3 KB (364 words) - 21:32, 27 January 2019
  • mirc/identifiers/$com
    |r4 || real, 4-byte floating point number || 1.17549435E-38 to 3.40282347E+38 |r8 || double real, 8-byte floating point number || 2.2250738585072014E-308 - 1.7976931348623157E+308
    5 KB (701 words) - 21:58, 16 August 2022
  • mirc/identifiers/$comcall
    |r4 || real, 4-byte floating point number || 1.17549435E-38 to 3.40282347E+38 |r8 || double real, 8-byte floating point number || 2.2250738585072014E-308 - 1.7976931348623157E+308
    4 KB (616 words) - 08:28, 17 August 2018
  • intel/microarchitectures/alder lake
    *** Vector floating point addition/subtraction latency decreased from 4 to 2 cycles
    7 KB (975 words) - 10:38, 3 August 2023
  • intel/microarchitectures/polaris
    ...ical capabilities of a [[many-core]] chip performing 1 [[trillion floating point operations]]. Polaris built the foundation that eventually resulted in Inte ...enabled by [[Moore's Law]] in order to achieve a high [[trillion floating point operations]] throughput. Polaris was Intel's first public chip as a direct
    16 KB (2,552 words) - 23:22, 17 May 2019
  • cambricon/mlu/mlu100
    ...xed-point (8-bit int) operations per second and 64 half-precision floating point (16-bit) [[TFLOPS]]. The efficiency of the chip slightly worsens at high-pe
    2 KB (261 words) - 11:06, 21 April 2019
  • cavium/microarchitectures/vulcan
    Vulcan has doubled the number of [[floating point]] units to two and widened them to 128-bit to support [[ARM]]'s {{arm|NEON}
    17 KB (2,449 words) - 22:11, 4 October 2019
  • samsung/microarchitectures/m4
    ** Floating-point execution units reorganized ==== Floating-point cluster ====
    5 KB (680 words) - 14:43, 16 March 2023
  • supercomputers/summit
    ...ations. In other words, each core can execute 16 single-precision floating-point operations per cycle. At 3.07 GHz, this works out to 49.12 gigaFLOPS of pea
    9 KB (1,496 words) - 20:39, 21 July 2019
  • amd/microarchitectures/zen 4
    | Ryzen 7000 APU "{{amd|Phoenix Point|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with GPU ...e and up to 12 Core Complex Dies attached with full-duplex serial point-to-point links. The IOD contains memory controllers, I/O controllers, microcontrolle
    13 KB (1,821 words) - 19:28, 13 November 2023
  • zhongshan subor/fireflight
    ...ts. The Compute Units operate at 1,300 MHz, each with 64 32-bit [[floating point]] [[multiply-accumulate]] units. At 1.3 GHz with 128 FLOP/cycle this chip c
    4 KB (613 words) - 13:48, 12 May 2019
  • arm holdings/microarchitectures/cortex-a77
    **** issue queue (IQ) is now unified for floating points ...more than the {{\\|Enyo}} and is the widest pipeline Arm designed to that point. For narrower 16-bit instructions (i.e., {{arm|Thumb}}), this means up to e
    17 KB (2,555 words) - 06:08, 16 June 2023
  • arm holdings/microarchitectures/cortex-a78
    ...are queued in three independent unified issue queues for integer, floating point, and memory. The floating-point cluster is unchanged from {{\\|Deimos}}. There are two {{arm|ASIMD}}/FP exe
    21 KB (3,067 words) - 09:25, 31 March 2022
  • arm/armv8
    | fp || - || Single-precision and double-precision floating point. | fphp || ARMv8.2-FP16 || Half-precision floating point.
    6 KB (817 words) - 06:37, 24 April 2020
  • arm/a64
    ...\\|A32}}). A64 advanced SIMD added support for [[double-precision floating point]] as well as [[IEE 754]] compliance. Additional instructions were also adde
    3 KB (446 words) - 01:03, 19 January 2022
  • flops
    {{title|Floating-Point Operations Per Second (FLOPS)}} ...performance]] used to quantify the number of [[floating-point]] [[floating-point operations|operations]] a [[physical core|core]], machine, or system is cap
    10 KB (1,204 words) - 15:03, 25 January 2023
  • intel/configurable spatial accelerator
    The push to [[exascale]] computing demands a very high [[floating-point]] performance while maintaining a very aggressive power budget. Intel claim ...rray of processing elements can include integer arithmetic PEs, [[floating-point arithmetic]] PEs, communication circuitry, and in-fabric storage. This grou
    14 KB (2,130 words) - 20:19, 2 October 2018
  • brain floating-point format
    {{title|Brain floating-point format (bfloat16)}} ...g-point number. It is equivalent to a standard [[single-precision floating-point]] value with a truncated [[mantissa field]]. Bfloat16 is designed to be use
    4 KB (582 words) - 12:35, 26 April 2021
  • Brain floating-point format
    #REDIRECT [[brain floating-point format]]
    41 bytes (4 words) - 10:26, 7 November 2018
  • Bfloat16
    #REDIRECT [[brain floating-point format]]
    41 bytes (4 words) - 10:26, 7 November 2018
  • bfloat16
    #REDIRECT [[brain floating-point format]]
    41 bytes (4 words) - 10:26, 7 November 2018
  • nec/microarchitectures/sx-aurora
    ...execution units - two general [[ALUs]] for both [[integer]] and [[floating-point]] pipelines for general scalar arithmetic, a dedicated branch ALU, a single The six execution pipes include three [[floating-point]] pipes, two integer [[ALU]]s, and a complex and store pipe for data output
    16 KB (2,497 words) - 13:30, 15 May 2020
  • bytes per flop
    ...cution unit]] and the off-chip memory relative to the number of [[floating-point operations]] required for a particular task. B/F is a common [[figure of me
    482 bytes (76 words) - 20:25, 23 November 2018
  • arm holdings/microarchitectures/cortex-a15
    ...e <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv
    3 KB (347 words) - 14:40, 31 December 2018
  • arm holdings/microarchitectures/cortex-a9
    ...e <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv
    2 KB (285 words) - 12:27, 28 July 2019
  • arm holdings/microarchitectures/cortex-a8
    ...e <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv
    3 KB (428 words) - 14:30, 31 December 2018
  • samsung/microarchitectures/m5
    ** Floating-point execution units reorganized
    3 KB (333 words) - 22:10, 27 July 2021
  • tesla (car company)/fsd chip
    ...PS, supporting both [[single-precision]] and [[double-precision]] floating point operations.
    13 KB (1,952 words) - 20:34, 16 September 2023
  • hisilicon/microarchitectures/taishan v110
    ...p will have a peak compute of 512 GigaFLOPS of [[double-precision floating point]]. It's worth noting that compared to the {{\\|TaiShan v100}}, the throughp
    7 KB (947 words) - 10:20, 9 September 2022
  • arm holdings/microarchitectures/cortex-a34
    ...y<br />Neon Advanced SIMD<br />DSP and SIMD extensions<br />VFPv4 Floating point<br />Hardware virtualization support
    1 KB (179 words) - 03:34, 4 December 2021
  • microsoft/msfp8
    ...-point number. MSFP8 is equivalent to a standard [[half-precision floating-point]] value with a truncated [[mantissa field]]. It is the 8-bit equivalent of ...follows the same format as a standard IEEE 754 [[single-precision floating-point]] but truncates the [[mantissa field]] from 11 bits to just 2-5 bits. Prese
    1 KB (190 words) - 16:41, 15 October 2019
  • intel/microarchitectures/spring hill
    ...e of performing 4K-MAC/cycle (int8). It supports [[half-precision floating-point]] (FP16) as well as 8-bit, 4-bit, 2-bit, and even 1-bit precision operation
    9 KB (1,292 words) - 08:41, 26 March 2020
  • habana/microarchitectures/gaudi
    ...t, 16-bit, and 32-bit SIMD vector operations for both integer and floating-point. This was done in order to allow accuracy loss tolerance to be controlled o From a programmability point of view, Gaudi supports parameters, tensor, and sub-tensor transfers over E
    5 KB (662 words) - 18:36, 16 July 2020
  • habana/microarchitectures/goya
    ...nference. Since the target market is the data center, the [[thermal design point]] for those chips was relatively high - at around 200 W. Goya relies on [[P ...bit, and 32-bit SIMD vector operations for both [[integer]] and [[floating-point]]. This was done in order to allow accuracy loss tolerance to be controlled
    2 KB (320 words) - 16:29, 28 December 2019
  • centaur/microarchitectures/cha
    ...s – they are physically partitioned into three groups: integer, floating-point (and AVX), and memory. In terms of scheduler width, this is rivaling both I ===== Floating Point & Vector =====
    24 KB (3,792 words) - 04:37, 30 September 2022
  • amd/List of AMD publications
    ...Architecture Programmer’s Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions]||2018-05-25|| ...Architecture Programmer’s Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions]||2018-05-25||
    181 KB (24,861 words) - 16:02, 17 April 2022
  • arm holdings/microarchitectures/cortex-m55
    ...int vectored data types can be implemented without the FPU, while floating-point vector data types must include the FPU. ...-precision]] scalar [[floating-point]] data forms. Half-precision floating-point operations can be processed at twice the throughput per clock cycle as sing
    12 KB (1,806 words) - 10:51, 12 January 2021
  • arm/helium
    ...VE-F''' operates on [[half-precision]] and [[single-precision]] [[floating-point]] values ...instructions can be implemented with or without the MVE-F scalar floating-point extension.
    6 KB (986 words) - 19:09, 2 October 2020
  • x86/avx512 bf16
    ...</code> - Convert two SIMD registers with packed single-precision floating point values to [[bfloat16]] packed in a single register. ...6</code> - Convert one SIMD register with packed single-precision floating-point values to [[bfloat16]] packed in a single register.
    4 KB (578 words) - 16:50, 15 March 2023
  • BF16
    #REDIRECT [[brain floating-point format]]
    41 bytes (4 words) - 21:19, 27 June 2020
  • arm holdings/microarchitectures/neoverse v1
    ...xtract additional performance. In addition to general integer and floating-point performance, Zeus has also been optimized for HPC workloads with wider vect
    5 KB (748 words) - 16:20, 4 July 2022
  • arm holdings/microarchitectures/cortex-a510
    All scalar and floating-point NEON and SVE2 instructions are executed through the vector datapath. There At the peak operating point of the {{\\|Cortex-A55}}, the Cortex-A510 is capable of reaching the same p
    15 KB (2,282 words) - 11:20, 10 January 2023
  • alchemy/microarchitectures/au1
    ...by the MIPS standard, no CP1 (FPU), CP2, or CP3 instructions. All floating-point instructions generate the Reserved Instruction exception, therefore can be
    13 KB (2,114 words) - 16:00, 17 April 2022
  • x86/avx512 vbmi
    ...it words, doublewords, quadwords, and single and double precision floating point values in the same ways.
    6 KB (1,117 words) - 02:25, 14 March 2023
  • x86/avx512 vbmi2
    ...ectors of doublewords, quadwords, and single and double precision floating point values.
    14 KB (2,378 words) - 15:57, 15 March 2023
  • x86/avx512dq
    ...ns operating on 32-bit doublewords and 64-bit quadwords, and some floating point instructions. === Floating point instructions ===
    8 KB (1,307 words) - 15:09, 15 March 2023
  • x86/avx512 4fmaps
    ...not implemented on other chips. Plain parallel, single precision floating point, fused multiply-add instructions became available with the {{x86|FMA}} exte
    4 KB (583 words) - 15:30, 15 March 2023
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