Page title matches

• c/data types
  {{c title|Data Types}} ...s#Variable Declaration|variable declaration}}. There are two categories of types:
  7 KB (1,131 words) - 07:33, 4 January 2015
• Data types - C
  #REDIRECT [[c/data types]]
  26 bytes (4 words) - 07:15, 4 January 2015

Page text matches

• c
  * Structured Types ** {{C|Enumerated types|Enums}}
  5 KB (790 words) - 13:36, 2 October 2017
• c/standard library
  Related functions, necessary types to use those functions and related macros are grouped into headers. Collect ...|inttypes.h|<inttypes.h>}} || C99 || Provides a set of exact width integer types.
  5 KB (818 words) - 15:28, 9 March 2016
• mirc/variables
  '''mIRC variables''' are items which can hold data temporarily, or permanently, for use at a later time.. You can create, edit ...es not exist, it returns the value $null. Likewise, a variable without any data stored in it returns $null as well.
  17 KB (2,690 words) - 06:09, 5 June 2022
• mirc
  ...t test) but not greater-than or less-than comparison test (with mixed data types it is prone to coding error). == Data Storage ==
  10 KB (1,705 words) - 17:47, 1 August 2023
• mirc/sockets
  ...two types of Internet sockets (there are actually more, but only these two types are available natively through mIRC): ...ansmission Control Protocol, '''TCP''', does this by making sure that your data arrives in the correct order and error-free. Most applications like mIRC it
  4 KB (740 words) - 09:43, 22 September 2017
• mirc/sockets/tcp
  ...ings. The most common task scripters want to perform is retrieving a piece data from some website. ...e sockopen event we must send our request to the remote end-point. To send data to the remote end-point through the socket we use the {{mIRC|/sockwrite}} c
  20 KB (3,172 words) - 14:05, 20 October 2018
• c/ctype.h
  ...s|int}}''' which should be representable as an '''{{C|data types#Character Types|unsigned char}}''' or be equal to the value of the macro '''{{C|EOF}}'''. A
  3 KB (431 words) - 10:53, 7 January 2015
• mirc/commands/dde
  '''Dynamic Data Exchange''' ('''DDE''') is a form of communication between two applications The dde command support three different types of transactions:
  1 KB (227 words) - 19:15, 15 June 2017
• mirc/component object model
  ...e have to use the int data type. Below is a list of possible variable data types. ...||can contain string, date, time, boolean, or numeric values. When used, a data type must follow it: for example: variant int 5
  27 KB (3,608 words) - 11:41, 25 October 2018
• c/variables
  == Data Types == {{main|c/data types|l1=Data Types}}
  6 KB (1,016 words) - 15:07, 9 March 2016
• c/data types
  {{c title|Data Types}} ...s#Variable Declaration|variable declaration}}. There are two categories of types:
  7 KB (1,131 words) - 07:33, 4 January 2015
• JSON
  ...imple syntax which makes it both fast and simple to parse, JSON became the data interchange format of choice among many popular programming languages. == Data Types ==
  5 KB (716 words) - 01:27, 15 December 2013
• string manipulation
  ...ovide a [[string]] [[data type]] that holds a sequence of characters. Such types often expose a set of [[function]]s and various other low-level functionali
  3 KB (366 words) - 11:08, 4 January 2015
• microprocessor
  ...circuits operating as a cohesive unit, designed for the processing digital data. ...oadest sense, their basic functionality is to continuously read in digital data consisting of instructions and possibly values; execute them by interpretin
  8 KB (1,149 words) - 00:41, 16 September 2019
• c/basic i/o
  ...'Output'''. Input is the data that is sent into the program; output is the data that is sent out of the program. This article covers the basic I/O faciliti ...ut stream is used to read data that is sent to the program. Typically such data can come from the keyboard or from a file that has been redirected to the p
  11 KB (1,784 words) - 07:13, 4 January 2015
• c/basic arithmetics
  == Operations of mixed types == ...on of two int types. Expressions, however, can involve values of different types. When this happen, a protocol for converting them to a common type is invok
  7 KB (1,081 words) - 07:20, 4 January 2015
• c/usual arithmetic conversions
  ...outinely perform type conversions to get its operands to a common {{C|data types|type}} or extend a short values to the natural integer size used by the mac ..., if both operands have signed integer types or both have unsigned integer types, the operand with the type of lesser integer conversion rank is converted t
  2 KB (328 words) - 07:49, 4 January 2015
• multiplexer
  A '''multiplexer''' ('''mux''') or a '''data selector''' or '''input selector''' is a [[combinational circuit]] device t ...single destination. Multiplexers are also heavily used in I/O operations, data buses, and register files. Additionally multiplexers have also found their
  10 KB (1,445 words) - 11:53, 18 November 2018
• mirc/identifiers/$encode
  ...-v7.53 or other applications accepting them for all cases for all encoding types. ...gnores any padding switches used, and instead searches for all 4 supported types of padding. The attempt to match 'z' padding has a false match with 'n' pad
  33 KB (5,484 words) - 04:32, 16 April 2023
• mirc/regex
  ...\c{ becomes hex 3B ({ is 7B), and \c; becomes hex 7B (; is 3B). If the data item (byte or 16-bit value) following \c has a value greater than 127, a co ...up to three octal digits following the backslash, using them to generate a data character. Any subsequent digits stand for themselves.
  27 KB (4,356 words) - 20:17, 29 June 2021
• Data types - C
  #REDIRECT [[c/data types]]
  26 bytes (4 words) - 07:15, 4 January 2015
• hitachi/hmcs40
  ...hi]] and introduced in the late 1970s and continued well into the 90s. Two types of each component were manufactured, one using [[pMOS]] for low cost and an ...ional 128 Words (10-bit ea) of pattern ROM. 32 to 160 digits (4-bit ea) of data [[RAM]]. Chips also contained Event/Timer-Counter and 22-44 I/O lines. Outp
  4 KB (400 words) - 19:05, 24 May 2016
• output device
  ...[[peripheral]] that converts machine-readable information (e.g. processed data) into human-readable form. Broadly speaking, an output device does the oppo == Types ==
  439 bytes (48 words) - 07:46, 10 November 2015
• input device
  ...for processing. This in contrast with [[output device]]s, where processed data leaves a system. == Types ==
  662 bytes (70 words) - 07:46, 10 November 2015
• general instrument/sba/isa
  | data size = 1 bit The SBA family had 8-bit instructions of two types: with immediate and without [[immediate value]].
  3 KB (449 words) - 21:57, 26 June 2017
• intel/microarchitectures/bonnell
  ** L1 Data Cache *** Tag + data = 4.5 KiB + 17.5 KiB
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/haswell (client)
  ...sists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB. '''{{x86|AVX2}}''' - Integer data types were extended to 256-bit SIMD.
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ...icant performance boost while saving power and bandwidth. Partitioning the data also helps simplify coherency as well as reducing localized contentions and
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ...ons come from the load buffer. Skylake features a dedicated 32 KiB level 1 data cache and a dedicated 32 KiB level 1 instruction cache. It also features a
  79 KB (11,922 words) - 06:46, 11 November 2022
• program
  ...ly bundled along with [[documentation]] and any [[dependency|dependent]] [[data]] and [[libraries]]. This bundle is collectively referred to as [[software] === Types of programs ===
  3 KB (409 words) - 19:03, 4 January 2019
• uc davis/kilocore
  ...pendent MIMD instructions per second. None of the 72 supported instruction types are algorithm-specific. ...ate of 28.5 Gbps. Maximum throughput is 45.5 Gbps per router. Both network types contribute to an array bisection bandwidth of '''4.2 Tbps'''.
  8 KB (1,031 words) - 14:09, 10 May 2019
• mathstar/builder
  Inter-Object communication was done primarily by passing data to the nearest neighbor through a unidirectional synchronous interconnect. There are five different types of components: [[Arithmetic Logic Unit]] (ALU), [[Content Addressable Memor
  5 KB (596 words) - 21:23, 19 November 2017
• intrinsity/fastmath
  ...matrix, vector, and scalar data types with dedicated local register file. Data arrays are directly fetched from L2 cache. This table is generated automatically from the data in the actual articles.
  4 KB (464 words) - 17:41, 3 July 2016
• intrinsity/fastmath/fastmath-1.5
  * Fixed-point matrix, vector, and scalar data types
  3 KB (317 words) - 16:30, 13 December 2017
• intrinsity/fastmath/fastmath-2
  * Fixed-point matrix, vector, and scalar data types
  3 KB (318 words) - 16:30, 13 December 2017
• intrinsity/fastmath/fastmath-lp
  * Fixed-point matrix, vector, and scalar data types
  3 KB (334 words) - 16:31, 13 December 2017
• intrinsity/fastmath/fastmath-3
  * Fixed-point matrix, vector, and scalar data types
  3 KB (306 words) - 16:31, 13 December 2017
• amd/k6-2
  Three different types of K6-2 models were sold: Desktop PCs, Mobile, and Embedded systems. This table is generated automatically from the data in the actual articles.
  13 KB (1,969 words) - 18:07, 2 October 2019
• amd/k6-iii
  Three different types of K6-III models were sold: Desktop PCs, Mobile, and Embedded systems. This table is generated automatically from the data in the actual articles.
  9 KB (1,264 words) - 02:29, 19 January 2017
• amd/microarchitectures/zen 2
  ...error causes a machine check exception, the core recovers by reloading the data from memory. The caches are ECC protected to correct single (and double?) b ...imilarly predicts dependencies between stores and loads accessing the same data in memory, e.g. local variables. Both functions use memory renaming to faci
  57 KB (8,701 words) - 22:11, 9 October 2022
• wall
  == Types of walls == ...cult to extract enough parallelism, coupled with speculative execution and data dependencies
  1 KB (184 words) - 23:37, 15 January 2018
• amd/cores/milan
  ...rollers support [[wikipedia:ECC memory|ECC memory]] and the following DIMM types:<ref name="amd-56873">{{cite techdoc|title=Memory Population Guidelines for ...| DIMM Type || colspan="2" | DIMM Population/Channel || rowspan="2" | Max. Data Rate<br/>(MT/s)
  19 KB (2,734 words) - 01:26, 31 May 2021
• amd/infinity fabric
  ...'') is a proprietary system [[interconnect architecture]] that facilitates data and control transmission across all linked components. This architecture is ...lable Control Fabric''' ('''SCF'''). The SDF is the primary means by which data flows around the system between endpoints (e.g. [[NUMA node]]s, [[PHY]]s).
  8 KB (1,271 words) - 21:50, 18 August 2020
• arm holdings/microarchitectures/arm6
  ...{{arm|history|previous ARM chips}} by featuring a full 32-bit address and data buses. To {{arm|26-bit|facilitate}} the larger address space, ARM (previous Because the ARM6 core now features a full 32-bit address and data buses, it breaks compatibility with prior code. ARM addressed this problem
  11 KB (1,679 words) - 21:00, 15 May 2024
• x86/avx-512
  ...saturation: min(max(0, x), 2^W - 1), where W is the destination data type width in bits. ...hey can perform any bitwise boolean operation with up to three inputs. The data type distinction is necessary because these instructions support write mask
  83 KB (13,667 words) - 15:45, 16 March 2023
• intel/microarchitectures/skylake (server)
  **** Adaptive Double Device Data Correction (ADDDC) ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
  52 KB (7,651 words) - 00:59, 6 July 2022
• neural processor
  ...mplete models. Inference accelerators are designed to input a new piece of data (e.g., a new camera shot), process it through the already trained model and === Data types ===
  5 KB (640 words) - 16:27, 26 September 2023
• accelerator
  == Types of accelerators == * '''Data-driven accelerators''' - accelerators that are operate on a set of data independent of the CPU
  4 KB (539 words) - 19:47, 2 April 2019
• intel/microarchitectures/cascade lake
  ** Higher data rate (2933 MT/s, up from 2666 MT/s) ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
  32 KB (4,535 words) - 05:44, 9 October 2022
• nervana/microarchitectures/spring crest
  ...neural processor]] microarchitecture designed by [[Intel Nervana]] for the data center and workstations. With the acquisition of [[Habana Labs]], Spring Cr ...n and highest power efficiency. Emphasis was placed on the reuse of on-die data and batched workloads.
  11 KB (1,646 words) - 13:35, 26 April 2020
• movidius/microarchitectures/shave v2.0
  * Full support for sparse data structures (matrix/array, random access) SHAVE supports a mixture of many different types of instructions belonging to a number of different classes of architectures
  12 KB (1,749 words) - 19:05, 20 January 2021
• amd/packages/socket tr4
  ...1.33&nbsp;GHz FCLK coupled to the bus clock of DDR4-2666 SDRAM gives a raw data rate of 5.33 GT/s per lane or 21.33&nbsp;GB/s in each direction.<!--Beck201 ...The interfaces were renumbered to reflect this. Two, rather than just one, Data Fabric on-package links connect the dies. Since each die actually implement
  86 KB (17,313 words) - 02:48, 13 March 2023
• amd/packages/socket sp3
  ...on processors which support eight memory channels and both UDIMM and RDIMM types. ...lade motherboard and collaterals including BOM, CAD file, CPLD programming data, Eagle layout, and schematic were published by the [https://opencompute.org
  110 KB (21,122 words) - 02:46, 13 March 2023
• nvidia/microarchitectures/nvdla
  ...fically optimized for [[convolutional neural networks]] (CNNs) as the main types of workloads deal with images and videos, although other [[neural networks| ...f the MACs remain constant for a number of cycles. This also helps reduces data transfers.
  5 KB (713 words) - 18:16, 1 September 2022
• arm/armv8
  ...{{\\|A32}} instruction set. The cryptography extensions, enhanced barrier types, and load acquire and store release which were introduced with the {{\\|A64 | dcpop || ARMv8.2 || Data cache clean to Point of Persistence (DC CVAP)
  6 KB (817 words) - 06:37, 24 April 2020
• brainchip/akida
  ...itecture designed by [[BrainChip]] for the [[edge computing|edge]] and the data center. * Conversion complex used to convert sensory and data to spikes
  3 KB (382 words) - 10:43, 28 September 2018
• amd/cores/genoa
  ...tion Architecture, AMD Brings 4th Gen AMD EPYC™ Processors to The Modern Data Center"] (Press release). AMD.com. November 10, 2022. Retrieved February 20 ...d EC8 DIMMs) and DDR5 DRAMs with 16/24/32 Gb density on the following DIMM types:
  14 KB (1,983 words) - 01:41, 2 April 2023
• brain floating-point format
  .../sup>). This allows for relatively simpler conversion between the two data types. In other words, while some resolution is lost, numbers can still be repres
  4 KB (582 words) - 12:35, 26 April 2021
• nec/microarchitectures/sx-aurora
  ** Removed assignable data buffer (ADB) ...the vector instructions being sent to the VPU in order to ensure that the data is ready by that time. The SPU features a vector coherence control logic wh
  16 KB (2,497 words) - 13:30, 15 May 2020
• scrubbing
  Types: * [[data scrubbing]]
  267 bytes (34 words) - 02:12, 26 November 2018
• intel/microarchitectures/sunny cove
  *** New dedicated queue for store data ** 2x store data ports (up from 1)
  34 KB (5,187 words) - 06:27, 17 February 2023
• pointer chasing
  ...d series of irregular [[memory access patterns]] that require the accessed data to determine the subsequent pointer address to be accessed, forming a seria ...ch operations are found in many types of applications that employ [[linked data structures]] (LDSs). Pointer chasing is therefore inherently both [[memory
  863 bytes (122 words) - 10:22, 4 August 2019
• tesla (car company)/fsd chip
  ...[[Sigmoid Linear Unit]] (SiLU), and TanH. Each cycle, 128 bytes of result data is written back to the SRAM. All the operations are done simultaneously and ...erations to prefetch data prior to use. During [[code generation]], weight data is generated, code is compressed, and a [[CRC checksum]] is generated for r
  13 KB (1,952 words) - 20:34, 16 September 2023
• tsmc/lipincon
  ...'') is a proprietary system [[interconnect architecture]] that facilitates data transmission across all linked components. ...rposer communicating by PHYs over short wires. LIPINCON uses two different types of PHYs: '''PHYC''' for an SoC die and '''PHYM''' for a memory, transceiver
  1 KB (206 words) - 13:36, 22 June 2019
• microsoft/msfp8
  ...5,504). This allows for relatively simpler conversion between the two data types. In other words, while some resolution is lost, numbers can still be repres
  1 KB (190 words) - 16:41, 15 October 2019
• amd/cores/chagall
  ...R}} {{abbr|UDIMM}}, {{abbr|RDIMM}}, {{abbr|LRDIMM}}, or {{abbr|3DS RDIMM}} types This table is generated automatically from the data in the actual articles.
  8 KB (1,180 words) - 14:26, 17 March 2023
• centaur/microarchitectures/cha
  ...code. CNS features four homogenous decoders - each capable of decoding all types of instructions. At the decode, x86 instructions are transformed into micro ...r. Data store operations are done via the execution units that forward the data to the store buffer. On CNS, up to 4 values may be forwarded to store - the
  24 KB (3,792 words) - 04:37, 30 September 2022
• arm holdings/microarchitectures/cortex-m55
  ...types can be implemented without the FPU, while floating-point vector data types must include the FPU. ..., [[single-precision]], and [[double-precision]] scalar [[floating-point]] data forms. Half-precision floating-point operations can be processed at twice t
  12 KB (1,806 words) - 10:51, 12 January 2021
• arm/helium
  * '''MVE-I''' operates on 32-bit, 16-bit, and 8-bit integer data types MVE supports interleaving data streams with strides of 2 and 4. They are done using the <code>VLD{2,4}x</c
  6 KB (986 words) - 19:09, 2 October 2020
• cea-leti/microarchitectures/tsarlet
  ** L1 Data cache Two different types of 3D-Plugs have been implemented: synchronous and asynchronous.
  12 KB (1,895 words) - 10:17, 27 March 2020
• amd/packages/ft1
  This table is generated automatically from the data in the actual articles. |M_DATA[63:0]||B-IO-S||DRAM Data Bus
  14 KB (2,611 words) - 00:31, 4 April 2022
• arm holdings/microarchitectures/neoverse v1
  *** Strictly inclusive of the L1 data cache & non-inclusive of the L1 instruction cache ...sts of a dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).
  5 KB (748 words) - 16:20, 4 July 2022
• 3ds dimm
  ...only with the master chips of a 3DS DIMM. Without the need for a separate data buffer performance can improve at lower power consumption.
  659 bytes (100 words) - 01:17, 2 April 2023
• amd/packages/sp4
  ...-lane multi-function I/O interfaces and other I/O facilities. Both package types are intended for single processor systems so {{abbr|xGMI}} links are not su ...bbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, {{abbr|3DS DIMM}}, {{abbr|NVDIMM-N}} types
  7 KB (1,088 words) - 05:09, 24 March 2023
• amd/packages/sp4r2
  ...-lane multi-function I/O interfaces and other I/O facilities. Both package types are intended for single processor systems so {{abbr|xGMI}} links are not su ** {{abbr|UDIMM}}, {{abbr|RDIMM}}, {{abbr|LRDIMM}}, {{abbr|NVDIMM-N}} types<!-- AMD-54945 -->
  7 KB (1,011 words) - 05:09, 24 March 2023
• amd/packages/socket swrx8
  ...R}} {{abbr|UDIMM}}, {{abbr|RDIMM}}, {{abbr|LRDIMM}}, or {{abbr|3DS RDIMM}} types This table is generated automatically from the data in the actual articles.
  11 KB (1,577 words) - 02:53, 13 March 2023
• amd/packages/socket strx4
  ...ports which extend the Control Fabric to the CCDs, these links run on four data and two clock lanes, as well as USB signals and low speed busses.<!--AMD-55 ...to {{abbr|CCIX}} memory expanders. XGBE is a backplane Ethernet link with data rates up to 10&nbsp;Gbit/s.) TR4 processors do not support PCIe Gen 4.
  14 KB (2,188 words) - 11:45, 6 April 2024
• amd/packages/socket sp5
  ...upports 12 channels of [[DDR5]] memory with two 40-bit subchannels (32 bit data + 8 bit ECC) and up to 2 DIMMs per channel, eight 16-lane PCIe Gen 5 I/O li ...Ms per channel. Each channel has two independent subchannels with a 32-bit data and 8-bit ECC bus. Type-0 processors support {{abbr|SR}}/{{abbr|DR}} RDIMMs
  105 KB (21,123 words) - 02:59, 13 March 2023
• amd/packages/socket am5
  ...pports two channels of [[DDR5]] memory with two 36-bit subchannels (32 bit data + 4 bit ECC) and up to 2 DIMMs per channel, up to 28 lanes PCIe Gen 4/5, fo ** Data rate up to ?
  19 KB (3,162 words) - 17:35, 11 May 2023
• intel/microarchitectures/raptor lake
  *** 1.17x Higher data rate (5,600 MT/s, up from 4,800 MT/s) ...ons. As with {{\\|Alder Lake}}, Raptor Lake integrate two vastly different types of cores - up to eight [[big cores|big]] performance cores ("P-Cores") alon
  9 KB (1,220 words) - 00:23, 17 January 2023