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  • voltage regulator module
    {{title|Voltage Regulator Module (VRM)}}[[File:vrm general.svg|right|500px]] ...(e.g. 0.8 V, 1 V, 1.2 V). VRMs are typically implemented as a [[switching regulator]] such as a [[buck converter]] due to their efficiency.
    18 KB (3,026 words) - 16:55, 19 January 2020
  • Voltage Regulator Module
    #REDIRECT [[voltage regulator module]]
    38 bytes (4 words) - 20:36, 14 October 2017
  • voltage regulator modules
    38 bytes (4 words) - 08:16, 20 September 2018

Page text matches

  • intel/microarchitectures/haswell (client)
    * Fully Integrated Voltage Regulator (FIVR) ...he V<sub>CORE</sub>, V<sub>RING</sub>, and V<sub>SA</sub>. With the memory voltage (V<sub>DDQ</sub> = 1.2 V Nom) provided from the motherboard with to its own
    27 KB (3,750 words) - 06:57, 18 November 2023
  • intel/microarchitectures/sandy bridge (client)
    ** New SVID (Serial Voltage ID bus) ...ithin the same [[clock domain]] as the cores themselves - sharing the same voltage and frequency and scaling along with the cores when needed.
    84 KB (13,075 words) - 00:54, 29 December 2020
  • intel/microarchitectures/skylake (client)
    ** Can now have its own variable voltage and frequency ** The fully integrated voltage regulator (FIVR) is moved back to the motherboard
    79 KB (11,922 words) - 06:46, 11 November 2022
  • amd/am5x86
    ...rd, it either had a manual jumper one has to set or an autodetect version, voltage must be set to 3.45 (± 0.15 tolerance). Likewise the input clock must be s |?core voltage
    7 KB (1,043 words) - 16:50, 14 June 2020
  • amd/microarchitectures/zen
    [[File:zen ccx voltage.png|250px]] ...ke|l=arch}} due to a number of thermal restrictions it created). Zen's new voltage control is an attempt at a much finer power tuning on a per core level base
    79 KB (12,095 words) - 15:27, 9 June 2023
  • amd/packages/socket am4
    |VDDCR_CPU_SENSE||VDDCR_CPU voltage monitor pin |VDDCR_SOC||Supply voltage for the Northbridge
    30 KB (6,098 words) - 01:58, 12 January 2024
  • intel/microarchitectures/skylake (server)
    ...ervers and HEDT models will still incorporate the fully integrated voltage regulator (FIVR) on-die. Those chips also have an entirely new multi-core system arch ...f the channel layout. Command, Control, Clock signals, and process, supply voltage, and temperature (PVT) compensation circuitry are located in the middle sec
    52 KB (7,651 words) - 00:59, 6 July 2022
  • load-line calibration
    ...or normal systems the LLC is usually disabled by default because typical [[voltage droop|V<sub>droop</sub>]] is part of the system specification. ...e predefined [[voltage]], causing a voltage drop. For example, a [[voltage regulator module|VRM]] operating at a constant 10% duty cycle delivering 1.2 V at idl
    6 KB (1,054 words) - 18:55, 26 October 2018
  • voltage regulator module
    {{title|Voltage Regulator Module (VRM)}}[[File:vrm general.svg|right|500px]] ...(e.g. 0.8 V, 1 V, 1.2 V). VRMs are typically implemented as a [[switching regulator]] such as a [[buck converter]] due to their efficiency.
    18 KB (3,026 words) - 16:55, 19 January 2020
  • VRM
    #REDIRECT [[voltage regulator module]]
    38 bytes (4 words) - 20:36, 14 October 2017
  • Voltage Regulator Module
    #REDIRECT [[voltage regulator module]]
    38 bytes (4 words) - 20:36, 14 October 2017
  • Voltage Regulation Module
    #REDIRECT [[voltage regulator module]]
    38 bytes (4 words) - 20:36, 14 October 2017
  • voltage regulation module
    #REDIRECT [[voltage regulator module]]
    38 bytes (4 words) - 20:36, 14 October 2017
  • greenwaves/gap8
    ...ata and 16 KiB instruction caches. The engine sits on an entirely separate voltage and frequency [[power domain|domains]] which can be switched off when not o * Programmable Voltage Regulator
    6 KB (981 words) - 14:11, 28 February 2018
  • amd/packages/socket tr4
    ...PU, SVC_SOC||O-IO18-S||Serial VID Interface Clock for VDDCR_CPU, VDDCR_SOC regulator |VDDCR_CPU||S||Supply voltage for the CPU core
    86 KB (17,313 words) - 02:48, 13 March 2023
  • amd/packages/socket sp3
    ...PU, SVC_SOC||O-IO18-S||Serial VID Interface Clock for VDDCR_CPU, VDDCR_SOC regulator |VDDCR_CPU||S||Supply voltage for the CPU core
    110 KB (21,122 words) - 02:46, 13 March 2023
  • VRMs
    #REDIRECT [[voltage regulator module]]
    38 bytes (4 words) - 07:46, 12 August 2018
  • intel/microarchitectures/lakefield
    ...f a discrete [[voltage regulator module|VR]] or [[fully-integrated voltage regulator|FIVR]] as with its contemporaries such as {{\\|Ice Lake (client)|Ice Lake}}
    5 KB (769 words) - 06:44, 14 August 2021
  • amd/List of AMD publications
    ...ow Voltage Power Supply Circuits (Am486, Am5x86, K5) (August 1995).pdf|Low Voltage Power Supply Circuits]]||1995-08|| ...rs_and_tech_docs/19766.pdf AMD-K5™ PROCESSOR Support for the AMD-K5 Dual Voltage Processor Application Note]||1996-09||
    181 KB (24,861 words) - 16:02, 17 April 2022
  • amd/packages/socket am2
    |M_VREF||DRAM Interface Voltage Reference |PSI_L||Power Status Indicator (low power state) for VDD regulator
    7 KB (1,029 words) - 18:40, 22 February 2020
  • amd/packages/socket am2+
    ...YPE||Indicates that the processor is capable of split core and northbridge voltage plane operation |M_VREF||DRAM Interface Voltage Reference
    8 KB (1,212 words) - 19:01, 22 February 2020
  • cea-leti/microarchitectures/tsarlet
    *** Per-chiplet voltage regulator and power management ...ngth of the wire and the design point. The SoC comes with fully-integrated voltage regulators with per-chiplet [[DVFS]] and IR-drop mitigation. The SoC suppor
    12 KB (1,895 words) - 10:17, 27 March 2020
  • amd/packages/socket am3
    ...YPE||Indicates that the processor is capable of split core and northbridge voltage plane operation |M_VREF||DRAM Interface Voltage Reference
    12 KB (1,960 words) - 12:23, 18 July 2020
  • amd/packages/fp6
    |SLP_S3/S5_L||S3/S5 Sleep State Power Plane Control Signals for voltage regulator |SVC0||Serial VID Clock; {{amd|SVI2}} interface to VDDCR/VDDCR_SOC regulator
    20 KB (3,273 words) - 17:47, 10 May 2023
  • amd/packages/socket f
    |M_VREF||DRAM Interface Voltage Reference |VDDA||Filtered PLL supply voltage
    11 KB (1,717 words) - 17:25, 5 February 2021
  • x86/hardware thermal control
    ...o throttle the CPU if it detects that another component, such as a voltage regulator, memory module, or the chipset, has reached a critical temperature.
    852 bytes (127 words) - 18:45, 12 January 2021
  • amd/packages/socket s1g1
    |MEMVREF||DRAM Interface Voltage Reference |PSI_L||Power Status Indicator (low power state) for VDD regulator
    8 KB (1,126 words) - 18:53, 12 January 2021
  • amd/packages/socket s1g2
    ...g feature. S1g2 processors support dual plane platforms supplying the same voltage to both cores, but not a single plane supplying the northbridge as well. |M_VREF||DRAM Interface Voltage Reference
    8 KB (1,211 words) - 19:08, 12 January 2021
  • amd/packages/socket s1g4
    ...memory. As the number of CPU cores in the package grew to three and four, voltage regulators were integrated on the chip and support for two core power plane |A3||PSI_L||RSVD||RSVD||Power Status Indicator (low power mode) for VDD regulator
    10 KB (1,781 words) - 19:23, 12 January 2021
  • amd/packages/socket g34
    |M_VREF[1:0]||DRAM Interface Voltage Reference |VDD_SENSE||VDD voltage monitor pin
    36 KB (7,214 words) - 15:50, 23 April 2022
  • amd/packages/socket sp5
    ...VID Bus 0/1 Clock; Bus 0: VDDCR_CPU0, VDDCR_SOC; Bus 1: VDDCR_CPU1; VDDIO regulator supported by both busses |VDD_33_S5||S||3.3&nbsp;V I/O Supply Voltage
    105 KB (21,123 words) - 02:59, 13 March 2023
  • amd/packages/socket am5
    |SLP_S3/S5_L||S3/S5 Sleep State Power Plane Control Signals for voltage regulator |SVC||Serial VID Clock; ({{amd|SVI3}}) interface to VDDCR/VDDCR_SOC regulator
    19 KB (3,162 words) - 17:35, 11 May 2023
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