x86
Instruction Set Architecture

General

• History
• Families

Variants

• x86-16
• x86-32
• x86-64

Topics

• Instructions
• Addressing Modes
• Registers
• Model-Specific Register
• Assembly
• Interrupts
• Micro-Ops
• Timer
• Calling Convention
• Microarchitectures
• CPUID

CPUIDs

• AMD's CPUIDs
• Intel's CPUIDs

Modes

• Real
• Protected
• Long

Extensions(all)

• 3DNow!
• ABM
• ADX
• AES
• AMX
• AVX
• AVX2
• AVX-512
• BMI1
• BMI2
• CLMUL
• E3DNow!
• EMMX
• F16C
• FMA3
• FMA4
• FPU
• MKTME
• MMX
• MPX
• PMEM
• PREFETCH
• RdRAND
• SEV
• SGX
• SHA
• SME
• SMM
• SMX
• SSE
• SSE2
• SSE3
• SSE4.1
• SSE4.2
• SSE4a
• SSE5
• SSSE3
• TBM
• TME
• TSME
• TSX
• XOP

The x86 ISA has gone through numerous iterations that added new instructions to performs specific tasks. These collections of new instructions are grouped into extensions. Different microprocessor models have different levels of support for certain extensions.

Overview

The x86 ISA has been developed over the course of forty years. Various extensions have been proposed and implemented by various vendors in order to enhance the functionality of the base instruction set.

Timeline

	Extension	First µarch	Description
1978	Real	8086	Original Real mode
1982	Protected	80286	Protected mode
1985	SMM	80386	System Management Mode
1989	FPU	80486	Incorporates the x87 FPU into the same die
1996	MMX	P5	First implementation for SIMD instructions
1998	3DNow!	K6-2	SIMD extension for manipulating single-precision floating point
1999	SSE	P5	Streaming SIMD Extensions, SIMD for single-precision floating point
1999	E3DNow!	K7	Extended 3DNow! (New DSP instructions + some MMX instructions)
1999	Professional 3DNow!		A name given by AMD for E3DNow! + SSE
1999	EMMX	P6	Extended MMX; an extension to MMX
2001	SSE2	P6	Attempt to replace the original MMX instructions; wider XMM registers offer better performance
2004	SSE3	Core	Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register
2006	SSSE3	Core	Supplemental Streaming SIMD Extensions 3; additional instructions for working with packed integers
2007	SSE4.1	Penryn	Streaming SIMD Extensions 4.1; initial set of instructions for manipulating media data
2007	SSE4a	K10	4 SIMD instructions, not related to 4.1/4.2
2007	ABM	K10	Advanced Bit Manipulation; bit counting instructions
2008	SSE4.2	Nehalem	Streaming SIMD Extensions 4.2; second set of instructions for manipulating media data
2007	SSE5		Proposed by AMD in 2007 but was never implemented
2008	SSE4		Streaming SIMD Extensions 4; Another name for SSE4.1 + SSE4.2
2010	CLMUL	Westmere	Carry-less multiplication of two registers
2011	AVX	Sandy Bridge	Advanced Vector Extensions; introduces 256-bits integer operations
2012	F16C	Ivy Bridge	Extension for performing half-precision <-> single-precision conversions
2011	XOP	Bulldozer	eXtended Operations; various vector operations
2011	FMA4	Bulldozer	4-operands fused multiply-add
2011	LWP	Bulldozer	Lightweight Profiling
2011	SMX	Nehalem	Safer Mode Extensions; instructions needed to facilitate trust decisions (Part of Intel's Trusted Execution Technology)
2011	AES	Westmere	Instructions for optimizing AES operations
2012	TBM	Piledriver	Trailing Bit Manipulation; bit manipulation instructions designed to be compiler intrinsics
2013	BMI1	Jaguar	Bit Manipulation Instruction Set 1; introduces a number of bit manipulation instructions
2013	BMI2	Haswell	Bit Manipulation Instruction Set 2; introduces additional bit manipulation instructions
2013	FMA3	Haswell	3-operands fused multiply-add
2013	TSX	Haswell	Transactional Synchronization Extensions; adds transactional memory support
2013	AVX2	Haswell	Advanced Vector Extensions; additional instructions
2014	ADX	Broadwell	Multi-Precision Add-Carry Instruction extension
2014	RdRand	Broadwell	Part of Secure Key Technology extension (RdRand, RDSEED)
2014	PREFETCH	Broadwell	PREFETCH instructions (previously part of 3DNow!)
2015	AVX-512	Airmont	512 bit register operations
2015	MPX	Skylake	Memory Protection Extensions
2015	SGX	Skylake	Software Guard Extensions
2016	SHA	Goldmont	SHA Extensions
2017	SME	Zen	Secure Memory Extensions
2019	TME	Ice Lake	Total Memory Encryption

Experimental Extensions

	Extension	First µarch	Description
2008	L1OM	Larrabee	512-bit vector extension
2010	K1OM	Knights Corner	512-bit vector extension

Backwards compatibility

Generally speaking, all extensions are supported from their introductory date to present day. Extensions introduced by AMD's K6-2 (i.e., 3DNow! & E3DNow!) and those introduced by AMD's Bulldozer (i.e., FMA4, XOP, LWP, and later TBM) have been obsoleted. Note that Zen, at least for first stepping, still offered FMA4 support even though it's not indicated by CPUID.

See also

• ARM's Versions