Zen 5 - Microarchitectures - AMD

	Edit Values
	Zen 5 µarch
	General Info
Arch Type	CPU
Designer	AMD
Manufacturer	TSMC
Introduction	2024
Process	4 nm, 3 nm
Core Configs	192, 160, 144, 128, 96, 64, 48, 32, 24, 20, 16, 12, 10, 8, 6
PE Configs	384, 320, 288, 256, 192, 128, 96, 64, 48, 40, 32, 24, 20, 16, 12
	Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
	Instructions
ISA	AMD64, x86-64
Extensions	AMX, AVX, AVX2, AVX-512
	Cores
Core Names	Turin,; Shimada Peak,; Granite Ridge,; Fire Range,; Strix Point
	Succession
	Zen 4 Zen 6

Zen 5 is a microarchitecture Already released and sold being by AMD as a successor to Zen 4

History[edit]

Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018 ^[1]

Codenames[edit]

Product Codenames:

Core	Model	C/T	Target
Turin	EPYC 9005	Up to 128/256	High-end EPYC 5th Gen series server multiprocessors
Turin Dense	EPYC 9005	Up to 192/384	High-performance EPYC server processors
Shimada Peak	Ryzen 9000	Up to 32/64 ?	Threadripper Workstation & enthusiasts market processors
Granite Ridge	Ryzen 9000	Up to 16/32	Mainstream to high-end desktops & PC market processors (Gaming Desktop CPU)
Fire Range	Ryzen 9000	Up to 16/32	Mainstream desktop & mobile processors
Strix Point	Ryzen AI 300	Up to 12/24	Mainstream mobile processors with GPU (Gaming APU with RDNA3 or RDNA4)
Strix Halo	Ryzen AI 300	Up to 16/32	High-performance ultrathin notebook processors
Krackan Point	Ryzen AI 300	Up to ?/?	High-performance ultrathin mobile processors
Sonoma Valley	Ryzen APU Family	Up to ?/?	AMD Low-end Ryzen APU Family, Samsung 4 nm (TSMC) (Zen 5c Quad-core CPU, RDNA3 2CU GPU, TDP 35W)

The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server

processors (codenamed "Turin"), and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").

Architectural Codenames:

Arch	Codename
Core	Nirvana
CCD	Eldora

Comparison[edit]

Core		Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4	Zen 4c	Zen 5	Zen 5c	Zen 6	Zen 6c
Codename	Core			Valhalla	Cerberus		Persephone	Dionysus	Nirvana	Prometheus	Morpheus	Monarch
Codename	CCD			Aspen Highlands	Brecken Ridge		Durango	Vindhya	Eldora
Cores (threads)	CCD			8 (16)	8 (16)		8 (16)	16 (32)	8 (16)	16 (32)
Cores (threads)	CCX			4 (8)	8 (16)		8 (16)	8 (16)	8 (16)
L3 cache	CCD			32 MB	32 MB		32 MB	32 MB	32 MB	32 MB
L3 cache	CCX			16 MB	32 MB		32 MB	16 MB	32 MB
Die size	CCD area	44 mm²		74 mm²	80.7 mm²		66.3 mm²	72.7 mm²	70.6 mm²
Die size	Core area (Fab node)	7 mm² (14 nm)	(12 nm)	2.83 mm² (7 nm)	3.24 mm² (7 nm)	(7 nm)	3.84 mm² (5 nm)	2.48 mm² (5 nm)	(4 nm)	(3 nm)	(2 nm)	(2 nm)

Process Technology[edit]

Zen 5 is to be produced on a 4 nm process, Zen 5c is to be produced on a 3 nm process.

Architecture[edit]

AMD Zen 5 released in July 2024. The seventh microarchitecture in the Zen microarchitecture series.

Codenamed Granite Ridge, Strix Point, and Turin, it is slated for TSMC 4 nm or 3 nm manufacturing.

LITTLE design

- Improved 16% IPC and clock speed

- possibly more L3 cache per chiplet

Key changes from Zen 4[edit]

Core level (vs. Zen 4 microarchitectures)

Instruction set

AVX-512 VP2INTERSECT support

AVX-VNNI support

Front end

• Branch prediction improvements

- L1 BTB size increased significantly from 1.5K → 16K (10.7x)

- L2 BTB size increases from 7K → 8K

- Increased size of TAGE

- Introduction of 2-ahead predictor structure

- Return stack size increased from 32 → 52 entries (+62.5%)

• Improved instruction cache latency and bandwidth

- Instruction fetch bandwidth increased from 32B → 64B per cycle

- L2 instruction TLB size increased from 512 → 2048 entries (4x)

• Introducing a dual decode pipeline

- Decoder throughput scaled from 4 to 8 (2x4) per cycle (4 per thread, 4 in single thread)

- Op cache throughput expanded from 9 → 12 (2x6) per cycle (6 per thread, 6 for single thread)

- Unlike Intel E-Core, where a single thread can utilize multiple clusters, one cluster is used per SMT thread.

Back end

• Dispatch width of integer operations expanded from 6 → 8

• The size of ROB (reorder buffer) has been expanded from 320 to 448 entries (+40%)

• Integer register file capacity expanded from 192 → 240 entries (+25%)

• Floating point register file capacity expanded from 192 to 384 entries (2x)

• Flag register file capacity expanded to 192 entries

• Increased size of integer scheduler

- Scheduler size expanded from 4x24 (=96) → 88+56 (=144) entries (+50%)

- Adoption of integrated scheduler configuration similar to Intel P-Core

• Increased size of floating point scheduler

- The size of the pre-scheduler queue has been expanded from 64 to 96 entries (+50%).

- Scheduler size expanded from 2x32 (=64) → 3x38 (=114) entries (+78%)

• Number of ALUs increased from 4 → 6 (+50%)

• Number of multiplication units increases from 1 → 3 (3x)

• Number of branch units increased from 2 → 3 (+50%)

• Number of AGU increased from 3 → 4 (+33%)

- Number of loads that can be processed per cycle increased from 3 → 4 (same as 2 for 128 bits or more)

- Number of 128/256 bit stores that can be processed per cycle increased from 1 → 2

Desktop and server products such as Granite Ridge can process AVX-512 SIMD in one cycle.

However, mobile products process 256 bits in two cycles like the previous Zen 4.

Memory subsystem

• Load/Store Queue

- Increased size

• Prefetcher

- Added 2D stride prefetcher

- Improved stream & region prefetcher

• L1 data cache

- Capacity increased from 32 KB → 48 KB

- Associativity increases from 8-way → 12-way

- Bandwidth doubled

• L2 data cache

- Associativity increases from 8-way → 16-way

- Bandwidth increases from 32B → 64B per cycle

• L3 data cache

- Slight improvement in latency

- Maximum number of in-flight misses increased to 320

Physical design

Improved power gating technology

The overall expansion of the architecture has improved performance per clock

by an average of 16% compared to the previous generation.

Members[edit]

EPYC 9005 Series[edit]

"Turin/Turin Dense" (Server)

The fifth generation of EPYC processors was launched on October 10, 2024, at AMD's Advancing AI event, with general availability beginning in November 2024. Based on the Zen 5 microarchitecture, the 9005 series, codenamed "Turin", is manufactured by TSMC using a 4 nm process for standard Zen 5 cores and a 3 nm process for Zen 5c cores.

It utilizes the Socket SP5 socket, maintaining compatibility with the previous generation. The series offers core counts ranging from 8 cores to 192 cores, with support for up to 12 channels of DDR5-6000 memory (up to 6 TiB per socket) and 128 PCIe 5.0 lanes, enhancing performance and efficiency for high-performance computing, cloud, and AI workloads.

The series includes standard Zen 5 models, high-frequency "F" SKUs, single-socket "P" SKUs, and dense Zen 5c models, with TDPs ranging from 155 W to 500 W.

	List of Zen 5-based EPYC Processors
	Main Specs								Frequency
Model	Price	Launched	Cores	Threads	L2$	L3$	TDP	Memory	Base Freq	Max Boost
	Uniprocessors
EPYC 9015P	$ 527	November 2024	8	16	8 MiB	32 MiB	155 W	DDR5-6000	3.8 GHz	4.1 GHz
EPYC 9125P	$ 1,121	November 2024	16	32	16 MiB	64 MiB	200 W	DDR5-6000	4.0 GHz	4.3 GHz
EPYC 9355P	$ 4,771	November 2024	32	64	32 MiB	256 MiB	300 W	DDR5-6000	3.65 GHz	4.05 GHz
EPYC 9755P	$ 12,984	November 2024	128	256	128 MiB	256 MiB	400 W	DDR5-6000	2.7 GHz	4.1 GHz
	Multiprocessors (dual-socket)
EPYC 9015	$ 527	November 2024	8	16	8 MiB	32 MiB	155 W	DDR5-6000	3.8 GHz	4.1 GHz
EPYC 9115	$ 744	November 2024	12	24	12 MiB	32 MiB	155 W	DDR5-6000	3.6 GHz	4.0 GHz
EPYC 9125	$ 1,121	November 2024	16	32	16 MiB	64 MiB	200 W	DDR5-6000	4.0 GHz	4.3 GHz
EPYC 9175F	$ 2,624	November 2024	16	32	16 MiB	512 MiB	320 W	DDR5-6000	4.2 GHz	5.0 GHz
EPYC 9215	$ 1,518	November 2024	20	40	20 MiB	64 MiB	200 W	DDR5-6000	3.7 GHz	4.1 GHz
EPYC 9255	$ 2,238	November 2024	24	48	24 MiB	96 MiB	240 W	DDR5-6000	3.65 GHz	4.05 GHz
EPYC 9275F	$ 3,224	November 2024	24	48	24 MiB	96 MiB	300 W	DDR5-6000	4.1 GHz	4.8 GHz
EPYC 9335	$ 2,991	November 2024	32	64	32 MiB	128 MiB	240 W	DDR5-6000	3.35 GHz	3.9 GHz
EPYC 9355	$ 4,771	November 2024	32	64	32 MiB	256 MiB	300 W	DDR5-6000	3.65 GHz	4.05 GHz
EPYC 9375F	$ 5,198	November 2024	32	64	32 MiB	256 MiB	320 W	DDR5-6000	4.0 GHz	4.8 GHz
EPYC 9455	$ 5,987	November 2024	48	96	48 MiB	256 MiB	300 W	DDR5-6000	3.25 GHz	3.85 GHz
EPYC 9535	$ 6,876	November 2024	64	128	64 MiB	256 MiB	300 W	DDR5-6000	2.9 GHz	3.75 GHz
EPYC 9555	$ 9,251	November 2024	64	128	64 MiB	256 MiB	360 W	DDR5-6000	3.2 GHz	4.0 GHz
EPYC 9575F	$ 10,166	November 2024	64	128	64 MiB	256 MiB	400 W	DDR5-6000	3.5 GHz	5.0 GHz
EPYC 9655	$ 10,592	November 2024	96	192	96 MiB	256 MiB	400 W	DDR5-6000	2.7 GHz	4.1 GHz
EPYC 9745	$ 11,494	November 2024	128	256	128 MiB	256 MiB	400 W	DDR5-6000	2.4 GHz	3.8 GHz
EPYC 9755	$ 12,984	November 2024	128	256	128 MiB	256 MiB	400 W	DDR5-6000	2.7 GHz	4.1 GHz
EPYC 9565	$ 12,593	November 2024	96	192	96 MiB	384 MiB	400 W	DDR5-6000	2.8 GHz	4.0 GHz
EPYC 9665	$ 13,630	November 2024	96	192	96 MiB	384 MiB	400 W	DDR5-6000	3.0 GHz	4.2 GHz
EPYC 9755F	$ 13,999	November 2024	128	256	128 MiB	256 MiB	500 W	DDR5-6000	3.1 GHz	4.4 GHz
EPYC 9825	$ 13,999	November 2024	144	288	144 MiB	384 MiB	400 W	DDR5-6000	2.6 GHz	3.9 GHz
EPYC 9845	$ 14,399	November 2024	160	320	160 MiB	384 MiB	400 W	DDR5-6000	2.4 GHz	3.7 GHz
EPYC 9965	$ 14,813	November 2024	192	384	192 MiB	384 MiB	500 W	DDR5-6000	2.25 GHz	3.7 GHz
	Frequency-optimized SKUs
EPYC 9175F	$ 2,624	November 2024	16	32	16 MiB	512 MiB	320 W	DDR5-6000	4.2 GHz	5.0 GHz
EPYC 9275F	$ 3,224	November 2024	24	48	24 MiB	96 MiB	300 W	DDR5-6000	4.1 GHz	4.8 GHz
EPYC 9375F	$ 5,198	November 2024	32	64	32 MiB	256 MiB	320 W	DDR5-6000	4.0 GHz	4.8 GHz
EPYC 9575F	$ 10,166	November 2024	64	128	64 MiB	256 MiB	400 W	DDR5-6000	3.5 GHz	5.0 GHz
EPYC 9755F	$ 13,999	November 2024	128	256	128 MiB	256 MiB	500 W	DDR5-6000	3.1 GHz	4.4 GHz
Count: 0
32 :

Ryzen Threadripper Series[edit]

"Shimada Peak" (Zen 5) • Socket sTR5 (4 nm)

Model Name  	Cores/Threads Base/Boost Clock	 Socket	     Process  L3 Cache   TDP	Released

Ryzen TR 9960X		24/48	4.2/5.3 GHz	Socket sTR5	4 nm	128 MB	350 W	Jul 2025
Ryzen TR 9970X		32/64	4.0/5.4 GHz	Socket sTR5	4 nm	128 MB	350 W	Jul 2025
Ryzen TR 9980X		64/128	3.2/5.4 GHz	Socket sTR5	4 nm	256 MB	350 W	Jul 2025
Ryzen TR PRO 9945WX	12/24	4.7/5.4 GHz	Socket sTR5	4 nm	 64 MB	350 W	Jul 2025
Ryzen TR PRO 9955WX	16/32	4.5/5.4 GHz	Socket sTR5	4 nm	 64 MB	350 W	Jul 2025
Ryzen TR PRO 9965WX	24/48	4.2/5.4 GHz	Socket sTR5	4 nm	128 MB	350 W	Jul 2025
Ryzen TR PRO 9975WX	32/64	4.0/5.4 GHz	Socket sTR5	4 nm	128 MB	350 W	Jul 2025
Ryzen TR PRO 9985WX	64/128	3.2/5.4 GHz	Socket sTR5	4 nm	256 MB	350 W	Jul 2025
Ryzen TR PRO 9995WX	96/192	2.5/5.4 GHz	Socket sTR5	4 nm	384 MB	350 W	Jul 2025

Ryzen 9000 Series[edit]

"Granite Ridge" (Desktop) • Memory DDR5-5600, Socket AM5 (4 nm)

Model Name  	Cores/Threads Base/Boost Clock Cache (L3/L2)  Graphics (int.)	 TDP	Released

Ryzen 9 9950X3D2	16/32	4.3/5.6 GHz	192/16 MB	2x RDNA 2 CUs	200 W
Ryzen 9 9950X3D		16/32	4.3/5.7 GHz	128/16 MB	2x RDNA 2 CUs	170 W	Jan 2025
Ryzen 9 9950X		16/32	4.3/5.7 GHz	 64/16 MB	2x RDNA 2 CUs	170 W	Aug 2024
Ryzen 9 PRO 9945	12/24	3.4/TBD GHz	 64/12 MB	2x RDNA 2 CUs	 65 W
Ryzen 9 9900X3D		12/24	4.4/5.5 GHz	128/12 MB	2x RDNA 2 CUs	120 W	Jan 2025
Ryzen 9 9900X		12/24	4.4/5.6 GHz	 64/12 MB	2x RDNA 2 CUs	120 W	Aug 2024
Ryzen 7 9850X3D		 8/16	4.7/5.6 GHz	 96/8 MB	2x RDNA 2 CUs	120 W
Ryzen 7 9800X3D		 8/16	4.7/5.2 GHz	 96/8 MB	2x RDNA 2 CUs	120 W	Nov 2024
Ryzen 7 PRO 9745	 8/16	3.8/TBD GHz	 32/8 MB	2x RDNA 2 CUs	 65 W
Ryzen 7 9700X		 8/16	3.8/5.5 GHz	 32/8 MB	2x RDNA 2 CUs  65/105W	Aug 2024
Ryzen 7 9700F		 8/16	3.8/5.5 GHz	 32/8 MB	N/A		 65 W	Sep 2025
Ryzen 5 PRO 9645	 6/12	3.9/TBD GHz	 32/6 MB	2x RDNA 2 CUs	 65 W
Ryzen 5 9600X3D		 6/12	3.9/TBD GHz	 96/6 MB	2x RDNA 2 CUs	 65 W
Ryzen 5 9600X		 6/12	3.9/5.4 GHz	 32/6 MB	2x RDNA 2 CUs  65/105W	Aug 2024
Ryzen 5 9600		 6/12	3.8/5.2 GHz	 32/6 MB	2x RDNA 2 CUs	 65 W
Ryzen 5 9500F		 6/12	3.8/5.0 GHz	 32/6 MB	N/A		 65 W	Sep 2025

"Fire Range" (Desktop & Mobile) • Socket FL1 (4 nm)

Model Name  	Cores/Threads Base/Boost Clock   Socket     Process  L3 Cache	 TDP	Released

Ryzen 9 9850HX		12/24	3.0/5.2 GHz	Socket FL1	4 nm	 64 MB	 55 W	Jan 2025
Ryzen 9 9955HX		16/32	2.5/5.4 GHz	Socket FL1	4 nm	 64 MB	 55 W	Jan 2025
Ryzen 9 9955HX3D	16/32	2.5/5.4 GHz	Socket FL1	4 nm	128 MB	 55 W	Jan 2025

Ryzen AI (Max) 300 Series[edit]

"Krackan Point" (HPU Mobile) • Socket FP8 (4 nm)

Model Name  	Cores/Threads Base/Boost Clock	  Socket     Process  L3 Cache	 TDP	Released

Ryzen AI 5 330 (KP2)	4/8	2.0/4.5 GHz	Socket FP8	4 nm	 4 MB	 28 W	Jul 2025
Ryzen AI 5 340		6/12	2.0/4.8 GHz	Socket FP8	4 nm	 8 MB	 28 W	Jan 2025
Ryzen AI 5 PRO 340	6/12	2.0/4.8 GHz	Socket FP8	4 nm	 8 MB	 28 W	Jan 2025
Ryzen AI 7 350		8/16	2.0/5.0 GHz	Socket FP8	4 nm	 8 MB	 28 W	Jan 2025
Ryzen AI 7 PRO 350	8/16	2.0/5.0 GHz	Socket FP8	4 nm	 8 MB	 28 W	Jan 2025

"Strix Point" (Mobile w/ GPU & APU) • Socket FP8 (4 nm)

Model Name  	Cores/Threads Base/Boost Clock	  Socket     Process  L3 Cache	 TDP	Released

Ryzen AI 7 PRO 360	 8/16	2.0/5.0 GHz	Socket FP8	4 nm	 8 MB	 28 W	Jan 2025
Ryzen AI 9 365		10/20	2.0/5.0 GHz	Socket FP8	4 nm	16 MB	 28 W	Jul 2024
Ryzen AI 9 HX 370	12/24	2.0/5.1 GHz	Socket FP8	4 nm	16 MB	 28 W	Jul 2024
Ryzen AI 9 HX 375	12/24	2.0/5.1 GHz	Socket FP8	4 nm	16 MB	 28 W	Jul 2024
Ryzen AI 9 HX PRO 370	12/24	2.0/5.1 GHz	Socket FP8	4 nm	16 MB	 28 W	Jan 2025
Ryzen AI 9 HX PRO 375	12/24	2.0/5.1 GHz	Socket FP8	4 nm	16 MB	 28 W	Jan 2025

"Strix Halo" (HPU Notebook) • Socket FP11 (4 nm)

Model Name  	Cores/Threads Base/Boost Clock	  Socket     Process  L3 Cache	 TDP	Released

Ryzen AI Max 385	 8/16	3.6/5.0 GHz	Socket FP11	4 nm	32 MB	 55 W	Jan 2025
Ryzen AI Max 390	12/24	3.2/5.0 GHz	Socket FP11	4 nm	64 MB	 55 W	Jan 2025
Ryzen AI Max+ 395	16/32	3.0/5.1 GHz	Socket FP11	4 nm	64 MB	 55 W	Jan 2025
Ryzen AI Max PRO 380	 6/12	3.6/4.9 GHz	Socket FP11	4 nm	16 MB	 55 W	Jan 2025
Ryzen AI Max PRO 385	 8/16	3.6/5.0 GHz	Socket FP11	4 nm	32 MB	 55 W	Jan 2025
Ryzen AI Max PRO 390	12/24	3.2/5.0 GHz	Socket FP11	4 nm	64 MB	 55 W	Jan 2025
Ryzen AI Max+ PRO 395	16/32	3.0/5.1 GHz	Socket FP11	4 nm	64 MB	 55 W	Jan 2025

Ryzen AI 400 Series[edit]

"Gorgon Point" (APU)

Model Name  	Cores/Threads	Boost Clock	Cache	NPU	GPU	   Lanes  	TDP

Ryzen AI 9 HX 470	12/24	5.25 GHz+	36 MB	16 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 9 465		10/20	5.00 GHz	34 MB	12 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 7 460		 8/16	5.20 GHz+	24 MB	 8 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 7 450		 8/16	5.15 GHz+	24 MB	 8 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 7 445		 6/12	TBD		TBD	 4 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 5 440		 6/12	4.80 GHz	22 MB	 4 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 5 435		 6/12	4.70 GHz	14 MB	 4 CU RDNA 3.5	14 PCIe Gen4	15-45W
Ryzen AI 5 430		 4/8	TBD		12 MB	 4 CU RDNA 3.5	14 PCIe Gen4	15-45W
Ryzen AI 3 420		 4/8	4.60 GHz	12 MB	 2 CU RDNA 3.5	14 PCIe Gen4	15-45W

EPYC Embedded 4005 Series[edit]

"Grado" EPYC Embedded (Zen 5)

Model Name  	Cores/Threads	Base/Max Freq.	L3 Cache	TDP

EPYC Embedded 4585PX	16/32	4.3/5.7 GHz	128 MB		170W
EPYC Embedded 4565P	16/32	4.3/5.7 GHz	64 MB		170W
EPYC Embedded 4545P	16/32	3.0/5.4 GHz	64 MB		65W
EPYC Embedded 4465P	12/24	3.4/5.4 GHz	64 MB		65W
EPYC Embedded 4345P	 8/16	3.8/5.5 GHz	32 MB		65W
EPYC Embedded 4245P	 6/12	3.9/5.4 GHz	32 MB		65W

EPYC Embedded 2005 Series[edit]

EPYC Embedded (Zen 5)

Model Name  	Cores/Threads	Base/Max Freq.	L3 Cache	TDP

EPYC Embedded 2875	16/32	3.0/4.5 GHz	64 MB		75 W
EPYC Embedded 2655	12/24	2.7/4.5 GHz	64 MB		55 W
EPYC Embedded 2435	 8/16	2.8/4.5 GHz	32 MB		45 W

Designers[edit]

David Suggs, chief architect

Bibliography[edit]

↑ Ryzen Processors: One Year Later

codename	Zen 5 +
core count	192 +, 160 +, 144 +, 128 +, 96 +, 64 +, 48 +, 32 +, 24 +, 20 +, 16 +, 12 +, 10 +, 8 + and 6 +
designer	AMD +
first launched	2024 +
full page name	amd/microarchitectures/zen 5 +
instance of	microarchitecture +
instruction set architecture	AMD64 + and x86-64 +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Zen 5 +
process	4 nm (0.004 μm, 4.0e-6 mm) + and 3 nm (0.003 μm, 3.0e-6 mm) +
processing element count	384 +, 320 +, 288 +, 256 +, 192 +, 128 +, 96 +, 64 +, 48 +, 40 +, 32 +, 24 +, 20 +, 16 + and 12 +

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